High-efficiency data processing IC architecture based on heterogeneous computing and dynamic resource scheduling

Abstract

The invention relates to a high-efficiency data processing IC architecture based on heterogeneous computing and dynamic resource scheduling, and belongs to the technical field of integrated circuits, the high-efficiency data processing IC architecture comprises a heterogeneous computing unit module, a dynamic resource scheduling module and a storage and computing integrated module, the heterogeneous computing unit module integrates various computing units of different types and is used for executing data processing tasks of different characteristics, and the dynamic resource scheduling module is used for scheduling dynamic resources. The dynamic resource scheduling module is used for monitoring the load state of each computing unit in real time and dynamically allocating computing resources according to the demand of the data processing task; the storage and calculation integrated module tightly couples the storage unit and the calculation unit and is used for directly carrying out data calculation at a storage position so as to reduce data transmission; the method has the beneficial effects that the data processing efficiency is improved through the integration of the heterogeneous computing unit module and the resource allocation of the dynamic resource scheduling module.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling. Background Art

[0002] In the current data processing landscape, with the explosive growth of data volumes and the increasing demand for real-time data processing, traditional IC architectures face numerous challenges. The "memory wall" problem severely restricts data processing efficiency. This problem involves data transmission bandwidth and latency between the processor and memory, limiting the computing unit's ability to quickly access data. This results in the computing unit constantly waiting for data, unable to fully utilize its computing power. Furthermore, the "power wall" problem is becoming increasingly prominent. The massive data movement and inefficient use of computing resources in traditional architectures lead to excessive power consumption, increasing equipment operating costs and placing significant pressure on heat dissipation hardware design.

[0003] While some solutions exist, most fail to effectively address both the "memory wall" and the "power wall" simultaneously. For example, simply increasing memory bandwidth or cache capacity, while alleviating data transmission issues to some extent, results in increased chip area and power consumption, making it difficult to fundamentally meet the growing demand for data processing. Simple heterogeneous computing architectures, lacking effective dynamic resource scheduling mechanisms, are unable to flexibly allocate computing resources based on varying task requirements, resulting in low resource utilization. Therefore, a new IC architecture is urgently needed to overcome these bottlenecks and improve data processing efficiency. Summary of the Invention

[0004] The present invention provides a high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling, which is used to solve the technical problem of how to improve data processing efficiency. The data processing efficiency is improved through the integration of heterogeneous computing unit modules and the resource allocation of dynamic resource scheduling modules.

[0005] In order to achieve the above object, the present invention is implemented by the following technical solutions: High-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling, including: Heterogeneous computing unit module, which integrates multiple different types of computing units to perform data processing tasks with different characteristics; Dynamic resource scheduling module, which is used to monitor the load status of each computing unit in real time and dynamically allocate computing resources according to the needs of data processing tasks; The storage and computing module tightly couples the storage unit with the computing unit, allowing data calculations to be performed directly at the storage location to reduce data transmission. The heterogeneous computing unit module is connected to the dynamic resource scheduling module, and the dynamic resource scheduling module is connected to the storage and computing integrated module.

[0006] Optionally, the heterogeneous computing unit module includes at least one general-purpose processor unit, at least one dedicated accelerator unit, and at least one graphics processor unit; The general-purpose processor unit adopts a superscalar pipeline architecture, including: instruction prefetch unit, instruction decoding unit, execution unit, data cache unit and result write-back unit, which are used to execute control instructions and conventional data processing tasks; Dedicated accelerator units are customized based on domain-specific algorithms and have built-in dedicated arithmetic logic circuits to perform accelerated computing tasks in specific areas such as artificial intelligence reasoning and cryptographic calculations. The graphics processor unit adopts a massively parallel processing architecture, which includes: multiple stream processor clusters, each of which is configured with an independent register file, arithmetic logic unit and memory access unit for performing graphics rendering and parallel computing tasks.

[0007] Optionally, the instruction prefetch unit of the general processor unit predicts the instruction execution path through a branch prediction algorithm and fetches instructions from the memory in advance; The instruction decoding unit supports multiple instruction set architectures and can parse the fetched instructions into micro-operations; The execution unit includes an integer arithmetic unit, a floating-point arithmetic unit, and a multimedia processing unit, which are used to perform various arithmetic operations; The data cache unit adopts a multi-level cache structure, including: L1 and L2 cache, which are used to reduce memory access latency; The result write-back unit writes the result of the execution unit back to the register or memory.

[0008] Optionally, the dynamic resource scheduling module includes a load monitoring unit, a task analysis unit, and a resource allocation unit; The load monitoring unit obtains the computing load, memory usage, and energy consumption data of each computing unit in real time through performance counters. Performance counters are set on the critical path of each computing unit to count instruction execution cycles and data access times. The task analysis unit uses natural language processing and machine learning algorithms to parse the input data processing tasks, determine the task type through semantic analysis, and determine the data size and computational complexity through data feature extraction; The resource allocation unit dynamically adjusts the resource allocation ratio of each computing unit using a genetic algorithm or a simulated annealing algorithm according to the results of the load monitoring unit and the task analysis unit.

[0009] Optionally, the resource allocation unit dynamically adjusts the operating frequency and data transmission bandwidth of each computing unit through the bus control module and the clock management module; The bus control module uses time division multiplexing technology to allocate bus access time slices to each computing unit according to the resource allocation strategy; The clock management module dynamically adjusts the clock frequency of each computing unit through a phase-locked loop circuit, reducing power consumption while meeting task processing performance requirements.

[0010] Optionally, the storage and computing module includes a storage array and a computing logic unit; The storage array adopts a three-dimensional stacked structure and contains multiple layers of storage units. The layers are vertically interconnected through silicon via technology. Each storage unit in the storage array is equipped with an independent read-write control circuit and data selector to enable the computing logic unit to quickly access the stored data.

[0011] The computing logic units are distributed among the storage cells of the storage array and are used to directly perform logical operations and arithmetic operations on the data in the storage cells.

[0012] Optionally, the calculation logic unit includes an adder, a multiplier, a comparator and a logic gate circuit, and the calculation logic unit is connected to the storage unit via a high-speed interconnection line; The adder adopts a carry-lookahead adder structure to increase the speed of addition operation; The multiplier uses Booth's algorithm and Wallace tree structure to achieve fast multiplication operation; High-speed interconnect lines use low-power differential signal transmission technology to reduce signal transmission delay and power consumption.

[0013] Optionally, a data preprocessing module is included, which is connected to the heterogeneous computing unit module and the storage and computing integrated module. The data preprocessing module is used to convert the format of the input data, filter noise, and extract features to optimize the execution efficiency of the data processing task in the heterogeneous computing unit module and the storage and computing integrated module; The data preprocessing module includes a format conversion unit, a noise filtering unit and a feature extraction unit; the format conversion unit supports the conversion of multiple data formats and implements the format conversion logic using a state machine designed in a hardware description language; the noise filtering unit uses median filtering and Gaussian filtering algorithms to reduce noise on the data; the feature extraction unit extracts key features of the data based on a convolutional neural network or feature selection algorithm.

[0014] Optionally, a power consumption management module is further included. The power consumption management module is connected to the heterogeneous computing unit module, the dynamic resource scheduling module, and the storage and computing integrated module, and is used to dynamically adjust the power supply voltage and operating frequency of each module according to the load of the data processing task to reduce the overall power consumption; The power management module uses voltage-frequency island technology to divide the IC architecture into multiple independent voltage-frequency domains. Each voltage-frequency domain can independently adjust the supply voltage and operating frequency according to actual needs. Power gating technology is used to shut down temporarily inactive modules to further reduce static power consumption.

[0015] Optionally, the heterogeneous computing unit module, the dynamic resource scheduling module and the storage and computing integrated module communicate data and interact with each other through a high-speed on-chip network; The high-speed on-chip network uses a wormhole routing mechanism, where only the forwarding header information of the data packet is stored in the routing node, reducing the data packet transmission delay; A high-speed on-chip network quality of service (QoS) mechanism is adopted to allocate network bandwidth and transmission delay according to the priority of data processing tasks, ensuring the data transmission needs of critical tasks.

[0016] Beneficial effects of the present invention: The present invention provides a diversified computing power foundation through heterogeneous computing unit modules, a dynamic resource scheduling module ensures efficient allocation of computing power, and integrated storage and computing solves the bottleneck of data transmission. The combination of the three forms a closed loop of efficient computing power supply-intelligent resource management-low-consumption data processing. Specifically, the heterogeneous computing unit module significantly optimizes the response speed of complex tasks of big data, supports more intensive computing scenarios, and improves data processing efficiency by executing accelerated computing tasks in specific areas of artificial intelligence reasoning and cryptographic calculations; the dynamic resource scheduling module uses a simulated annealing algorithm to dynamically adjust the resource allocation ratio of each computing unit, thereby improving data processing efficiency; therefore, the present invention improves data processing efficiency through the integration of heterogeneous computing unit modules and the resource allocation of the dynamic resource scheduling module. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 Schematic diagram of the system architecture of the present invention. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0020] Example 1 like Figure 1 As shown, this embodiment provides a high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling, including: Heterogeneous computing unit module, which integrates multiple different types of computing units to perform data processing tasks with different characteristics; Dynamic resource scheduling module, which is used to monitor the load status of each computing unit in real time and dynamically allocate computing resources according to the needs of data processing tasks; The storage and computing module tightly couples the storage unit with the computing unit, allowing data calculations to be performed directly at the storage location to reduce data transmission. The heterogeneous computing unit module is connected to the dynamic resource scheduling module, and the dynamic resource scheduling module is connected to the storage and computing integrated module.

[0021] Heterogeneous computing units provide a diversified computing power foundation, dynamic resource scheduling ensures efficient allocation of computing power, and integrated storage and computing solve the bottleneck of data transmission. The combination of the three forms a closed loop of efficient computing power supply-intelligent resource management-low-consumption data processing, ultimately achieving: significantly optimized response speed for complex big data tasks and support for more intensive computing scenarios (such as edge computing nodes and supercomputing centers).

[0022] Through the integration of heterogeneous computing units, dynamic resource allocation and integrated storage and computing architecture, we can break through the "memory wall" and "power consumption wall" and improve data processing efficiency.

[0023] Example 2 Based on embodiment 1, specifically, the heterogeneous computing unit module includes at least one general-purpose processor unit, at least one dedicated accelerator unit, and at least one graphics processor unit; The general-purpose processor unit adopts a superscalar pipeline architecture, including: instruction prefetch unit, instruction decoding unit, execution unit, data cache unit and result write-back unit, which are used to execute control instructions and conventional data processing tasks; Dedicated accelerator units are customized based on domain-specific algorithms and have built-in dedicated arithmetic logic circuits to perform accelerated computing tasks in specific areas such as artificial intelligence reasoning and cryptographic calculations. For artificial intelligence reasoning, convolution operations are performed, which convert two-dimensional convolution into matrix multiplication (such as Winograd algorithm optimization).

[0024] The convolution operation formula is: 2D convolution (input feature map , convolution kernel , output feature map ): ; The convolution is converted into matrix multiplication by sliding window, and multiple parallel calculations are performed using systolic array. ; The output feature map (or processed data) is at position The value at is the input data (such as original image, intermediate feature map), the range is (The formula simplifies the channel dimension and focuses on spatial convolution); is the convolution kernel (filter), with a size of ; and are the height and width of the convolution kernel respectively; and is the spatial coordinate of the output feature map (traversing each pixel of the output); and is the local coordinate of the convolution kernel (traversing each weight of the convolution kernel). is the double summation symbol, and is the size of the convolution kernel, which represents the input data neighborhood covered by the convolution kernel (size is ), element-by-element multiplication and accumulation complete a convolution calculation.

[0025] The operation process is to input data Each position , using the convolution kernel Covering its local neighborhood ( The center is Neighborhood window), element-by-element multiplication and summation, the result is The value of is essentially a weighted sum, and the weight is determined by the convolution kernel Definition. If the convolution kernel is an edge detection operator (such as Sobel operator), then Will stand out Edge areas where pixel values ​​change dramatically.

[0026] For specific areas of cryptographic calculations, RSA modular exponentiation is used; , ; in, For plain text, is the ciphertext, and is the public-private key exponent, is the modulus, that is, the large number Do After the power operation, take The remainder of the ciphertext , using the public key Plaintext Encryption, the sender converts the plaintext into ciphertext through this formula. Since the encryption process is based on modular exponentiation in number theory, and the public key is public but the private key cannot be reversed, the security of encryption is guaranteed; decryption is the ciphertext Do Raise to the power The remainder of the plaintext is restored using the private key Ciphertext Decryption, the recipient only has the private key , the ciphertext can be restored to plaintext through this formula; because the private key is kept secret, others cannot decrypt it, thus ensuring the confidentiality of the communication.

[0027] Using Montgomery Modular Multiplication: ; in, ( is the modulus bit) to facilitate computer binary operations acceleration, for In the model The inverse element below, Are the two input numbers involved in the modular multiplication operation, which are The basic data for performing "multiplication-like" operations, such as plaintext, ciphertext, or intermediate calculations in the RSA cryptographic algorithm; Is the modulus, limiting the range of the operation result to , is the core parameter of the modular operation, which determines the period of the remainder class. The essence of RSA encryption / decryption is large number modular exponentiation, and Montgomery modular multiplication is not a direct calculation. , but first introduce the cardinality Do pre-transformation, by The core of converting the result back is to use more efficient calculation logic (for example, shifting and subtraction instead of division to find the modulus) to speed up the modular multiplication operation. The Montgomery algorithm converts modular multiplication into unsigned integer operation to avoid the high overhead of direct modular operation. It uses pipeline Montgomery modular multiplier to decompose the exponent into binary bits (such as fast power algorithm) to calculate the partial product in parallel and reduce the operation cycle. Montgomery modular multiplication is not a direct operation. , but first Switch to Montgomery Domain, The two numerical parameters are input, which can be understood as the basic data involved in the operation, such as integers or real numbers. After multiplication in the domain, they are converted back. It is a power of 2 characteristic, using shifting instead of division. Montgomery modular multiplication is a modular multiplication optimization algorithm created for hardware acceleration. By domain conversion + shifting instead of division, the complexity of large number modular multiplication is reduced from extremely difficult division to simple shifting and multiplication. That is, multiplying a, b with the inverse of R, and then taking the modulus of N to get the final result.

[0028] The graphics processor unit adopts a massively parallel processing architecture, which includes: multiple stream processor clusters, each of which is configured with an independent register file, arithmetic logic unit and memory access unit for performing graphics rendering and parallel computing tasks.

[0029] The instruction prefetch unit of the general processor unit predicts the instruction execution path through the branch prediction algorithm and fetches instructions from the memory in advance; The instruction decoding unit supports multiple instruction set architectures and can parse the fetched instructions into micro-operations; The execution unit includes an integer arithmetic unit, a floating-point arithmetic unit, and a multimedia processing unit, which are used to perform various arithmetic operations; The data cache unit adopts a multi-level cache structure, including: L1 and L2 cache, which are used to reduce memory access latency; among them, the L1 cache is the high-speed cache closest to the CPU core integrated inside the processor, usually divided into two parts: instruction cache (Instruction Cache) and data cache (Data Cache), which directly interacts with the CPU core for data and is the first line of defense in the multi-level cache structure; the L2 cache is located after the L1 cache, usually integrated into the CPU chip (or in the same package as the CPU core), and is the next level of cache after the L1 cache, used to store data that L1 misses, further reducing memory access latency.

[0030] The result write-back unit writes the result of the execution unit back to the register or memory.

[0031] The dynamic resource scheduling module includes a load monitoring unit, a task analysis unit, and a resource allocation unit; The load monitoring unit obtains the computing load, memory usage, and energy consumption data of each computing unit in real time through performance counters. Performance counters are set on the critical path of each computing unit to count instruction execution cycles and data access times. The task analysis unit uses natural language processing and machine learning algorithms to parse the input data processing tasks, determine the task type through semantic analysis, and determine the data size and computational complexity through data feature extraction; The resource allocation unit dynamically adjusts the resource allocation ratio of each computing unit using a genetic algorithm or a simulated annealing algorithm according to the results of the load monitoring unit and the task analysis unit.

[0032] The simulated annealing algorithm dynamically adjusts the resource allocation ratio of each computing unit, specifically: Total Computational unit, Units are iterating The resource allocation ratio is ,satisfy , the dynamic adjustment formula is based on the Boltzmann distribution: ; in, is the adjustment range (usually positively correlated with the current resource ratio, such as: , is the adjustment factor); For the The change in the objective function of each unit processing task (i.e., the energy difference between the new solution and the current solution); For iteration The temperature at , follows the temperature decay function; To adjust the probability, it is defined as: ;in, is the Boltzmann constant (often simplified to 1).

[0033] The iterative process is: Initial state: assign initial proportions to each unit , set the initial temperature .

[0034] Iterative updates: Calculate the value of each unit (e.g., changes in task duration and error objective functions); use Decide whether to accept the adjustment and update ; According to the temperature decay function (such as: ) Lower the temperature.

[0035] Convergence termination: When the temperature drops to the threshold (or the number of iterations is sufficient), resource allocation tends to be stable and focuses on the optimal solution direction.

[0036] temperature Corresponding to thermodynamic temperature: at high temperatures, particles are active (the algorithm explores new solutions), and at low temperatures, particles are stable (the algorithm converges to the optimal solution); Energy gap Corresponding to particle energy changes: In the algorithm, this is the change in solution quality, guiding resource allocation optimization.

[0037] The resource allocation unit dynamically adjusts resource allocation for many computing tasks (such as large-scale optimization and machine learning training). The complexity of these tasks changes dynamically with the computing process. In optimization problems, it may be necessary to search the solution space extensively in the early stages, and then perform fine iterations in local areas in the later stages. This allows the algorithm to allocate matching resources (such as CPU time, memory, and storage bandwidth) to different computing units (such as different processor cores, nodes, or task modules) based on the complexity of the current stage of the problem.

[0038] The resource allocation unit dynamically adjusts the operating frequency and data transmission bandwidth of each computing unit through the bus control module and the clock management module; The bus control module uses time division multiplexing technology to allocate bus access time slices to each computing unit according to the resource allocation strategy; The clock management module dynamically adjusts the clock frequency of each computing unit through a phase-locked loop circuit, reducing power consumption while meeting task processing performance requirements.

[0039] The storage and computing module includes a storage array and a computing logic unit; The storage array adopts a three-dimensional stacked structure and contains multiple layers of storage units. The layers are vertically interconnected through silicon via technology. Each storage unit in the storage array is equipped with an independent read-write control circuit and data selector to enable the computing logic unit to quickly access the stored data.

[0040] The computing logic units are distributed among the storage cells of the storage array and are used to directly perform logical operations and arithmetic operations on the data in the storage cells.

[0041] The computational logic unit includes an adder, a multiplier, a comparator, and a logic gate circuit, and the computational logic unit is connected to the storage unit via a high-speed interconnection line; The adder adopts a carry-lookahead adder structure to increase the speed of addition operation; The multiplier uses Booth's algorithm and Wallace tree structure to achieve fast multiplication operation; High-speed interconnect lines use low-power differential signal transmission technology to reduce signal transmission delay and power consumption.

[0042] There is also a data preprocessing module, which is connected to the heterogeneous computing unit module and the storage and computing module. The data preprocessing module is used to convert the format of the input data, filter noise, and extract features to optimize the execution efficiency of data processing tasks in the heterogeneous computing unit module and the storage and computing module; The data preprocessing module includes a format conversion unit, a noise filtering unit and a feature extraction unit; the format conversion unit supports the conversion of multiple data formats and implements the format conversion logic using a state machine designed in a hardware description language; the noise filtering unit uses median filtering and Gaussian filtering algorithms to reduce noise on the data; the feature extraction unit extracts key features of the data based on a convolutional neural network or feature selection algorithm.

[0043] There is also a power consumption management module, which is connected to the heterogeneous computing unit module, dynamic resource scheduling module, and storage and computing integrated module. It is used to dynamically adjust the power supply voltage and operating frequency of each module according to the load of data processing tasks to reduce overall power consumption. The power management module uses voltage-frequency island technology to divide the IC architecture into multiple independent voltage-frequency domains. Each voltage-frequency domain can independently adjust the supply voltage and operating frequency according to actual needs. Power gating technology is used to shut down temporarily inactive modules to further reduce static power consumption.

[0044] The heterogeneous computing unit module, dynamic resource scheduling module and storage and computing integrated module communicate data and exchange instructions with each other through a high-speed on-chip network; The high-speed on-chip network uses a wormhole routing mechanism, where only the forwarding header information of the data packet is stored in the routing node, reducing the data packet transmission delay; It adopts a high-speed on-chip network quality of service (QoS) mechanism (a technical system for managing and optimizing network resource allocation and ensuring the quality of service of key applications. By classifying network traffic, setting priorities and controlling bandwidth, it ensures that different types of services receive corresponding service guarantees during network transmission). It allocates network bandwidth and transmission delay according to the priority of data processing tasks to ensure the data transmission needs of key tasks.

[0045] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope of the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling, characterized by: include: A heterogeneous computing unit module, which integrates multiple different types of computing units to perform data processing tasks with different characteristics; A dynamic resource scheduling module, which is used to monitor the load status of each computing unit in real time and dynamically allocate computing resources according to the requirements of data processing tasks; A storage and computing module tightly couples the storage unit with the computing unit, allowing data calculations to be performed directly at the storage location to reduce data transmission. The heterogeneous computing unit module is connected to the dynamic resource scheduling module, and the dynamic resource scheduling module is connected to the storage and computing integrated module.

2. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 1, characterized in that: The heterogeneous computing unit module includes at least one general-purpose processor unit, at least one dedicated accelerator unit and at least one graphics processor unit; The general processor unit adopts a superscalar pipeline architecture, including: an instruction prefetch unit, an instruction decoding unit, an execution unit, a data cache unit and a result write-back unit, for executing control instructions and conventional data processing tasks; The dedicated accelerator unit is customized based on a specific domain algorithm and has built-in dedicated arithmetic logic circuits for performing accelerated computing tasks in the specific fields of artificial intelligence reasoning and cryptographic calculations. The graphics processor unit adopts a large-scale parallel processing architecture, including: multiple stream processor clusters, each stream processor cluster is configured with an independent register file, arithmetic logic unit and memory access unit, and is used to perform graphics rendering and parallel computing tasks.

3. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 2, characterized in that: The instruction prefetch unit of the general processor unit predicts the instruction execution path through a branch prediction algorithm and fetches instructions from the memory in advance; The instruction decoding unit supports multiple instruction set architectures and can parse the fetched instructions into micro-operations; The execution unit includes an integer operation unit, a floating point operation unit and a multimedia processing unit, which are used to perform various types of operation operations; The data cache unit adopts a multi-level cache structure, including: L1 and L2 cache, for reducing memory access latency; The result write-back unit writes the calculation result of the execution unit back to the register or memory.

4. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 1, characterized in that: The dynamic resource scheduling module includes a load monitoring unit, a task analysis unit and a resource allocation unit; The load monitoring unit obtains the computing load, memory usage and energy consumption data of each computing unit in real time through performance counters. The performance counters are set on the critical path of each computing unit to count the instruction execution cycle and data access number information; The task analysis unit uses natural language processing and machine learning algorithms to parse the input data processing tasks, determine the task type through semantic analysis, and determine the data size and computational complexity through data feature extraction; The resource allocation unit dynamically adjusts the resource allocation ratio of each computing unit using a genetic algorithm or a simulated annealing algorithm according to the results of the load monitoring unit and the task analysis unit.

5. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 4, characterized in that: The resource allocation unit dynamically adjusts the operating frequency and data transmission bandwidth of each computing unit through the bus control module and the clock management module; The bus control module uses time division multiplexing technology to allocate bus access time slices to each computing unit according to the resource allocation strategy; The clock management module dynamically adjusts the clock frequency of each computing unit through a phase-locked loop circuit, reducing power consumption while meeting task processing performance requirements.

6. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 1, characterized in that: The storage and computing integrated module includes a storage array and a computing logic unit; The memory array adopts a three-dimensional stacked structure, including multiple layers of memory cells, with vertical interconnection between layers achieved through silicon via technology. Each memory cell in the memory array is equipped with an independent read-write control circuit and data selector to enable the computing logic unit to quickly access the stored data. The computing logic units are distributed among the storage units of the storage array and are used to directly perform logical operations and arithmetic operations on the data in the storage units.

7. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 6, characterized in that: The calculation logic unit includes an adder, a multiplier, a comparator and a logic gate circuit, and the calculation logic unit and the storage unit are connected via a high-speed interconnection line; The adder adopts a carry-lookahead adder structure to increase the speed of addition operation; The multiplier adopts Booth's algorithm and Wallace tree structure to achieve fast multiplication operation; The high-speed interconnection line adopts low-power differential signal transmission technology to reduce signal transmission delay and power consumption.

8. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 1, characterized in that: The data preprocessing module is connected to the heterogeneous computing unit module and the storage-computing integrated module. The data preprocessing module is used to convert the format of the input data, filter noise, and extract features to optimize the execution efficiency of the data processing task in the heterogeneous computing unit module and the storage-computing integrated module. The data preprocessing module includes a format conversion unit, a noise filtering unit and a feature extraction unit; the format conversion unit supports the conversion of multiple data formats and implements the format conversion logic using a state machine designed in a hardware description language; the noise filtering unit uses median filtering and Gaussian filtering algorithms to reduce noise on the data; the feature extraction unit extracts key features of the data based on a convolutional neural network or a feature selection algorithm.

9. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 1, characterized in that: It also includes a power consumption management module, which is connected to the heterogeneous computing unit module, the dynamic resource scheduling module, and the storage and computing integrated module, and is used to dynamically adjust the power supply voltage and operating frequency of each module according to the load of the data processing task to reduce the overall power consumption; The power management module uses voltage-frequency island technology to divide the IC architecture into multiple independent voltage-frequency domains. Each voltage-frequency domain can independently adjust the supply voltage and operating frequency according to actual needs. Power gating technology is used to shut down temporarily inactive modules to further reduce static power consumption.

10. The high-performance data processing IC architecture based on heterogeneous computing and dynamic resource scheduling according to claim 1, characterized in that: The heterogeneous computing unit module, dynamic resource scheduling module and storage and computing integrated module communicate data and exchange instructions with each other through a high-speed on-chip network; The high-speed on-chip network adopts a wormhole routing mechanism, in which only the forwarding header information of the data packet is stored in the routing node, thereby reducing the transmission delay of the data packet; A high-speed on-chip network quality of service mechanism is adopted to allocate network bandwidth and transmission delay according to the priority of data processing tasks, ensuring the data transmission needs of critical tasks.

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