Power supply anti-backflow method and circuit for multiprocessor cooperation

Abstract

The invention belongs to the technical field of multiprocessor power supply circuits, and particularly discloses a power supply anti-backflow method and circuit for multiprocessor collaboration, and the method comprises the steps: 1, firstly electrifying ports, except for IO ports interconnected with secondary processors, on a main processor; 2, the main processor outputs an enabling control signal to a power supply chip of the secondary processor to enable the secondary processor to be powered on, the enabling control signal is used for controlling the power-on time sequence of each port on the secondary processor, and when the IO port on the secondary processor is powered on, the IO port, connected with the secondary processor, on the main processor is powered on synchronously. According to the invention, the problem of abnormal work caused by influence on the normal power-on time sequence of the processors due to voltage and current backward flow caused by port interconnection among the processors in the cooperative work process of the processors can be avoided, the reliability of the system can be improved, and the normal work of the product can be ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of multi-processor power supply circuits, and specifically discloses a power supply backflow prevention method and circuit for multi-processor collaboration. Background Art

[0002] With the diversification of electronic product functions and miniaturization, system design has become increasingly complex, and the design of the central processing unit has also become more complex. The previous single processor is no longer competent.

[0003] Today's central processing units often require multiple processors to work together, inevitably requiring interconnected ports. Because each processor circuit has different power supply voltages and power-up sequences, improper handling can lead to port voltage and current backflow, disrupting the processor's power-up sequence and causing startup anomalies and malfunction. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention proposes a method for preventing power backflow for multi-processor collaboration, comprising the following steps:

[0005] Step 1: Power on all ports on the main processor except the IO port interconnected with the secondary processor.

[0006] Step 2: The main processor outputs an enable control signal to the power chip of the secondary processor to power on the secondary processor. The enable control signal is used to control the power-on timing of each port on the secondary processor. When the IO port on the secondary processor is powered on, the IO port on the main processor that is interconnected with the secondary processor is powered on synchronously.

[0007] The present invention also proposes a power backflow prevention circuit for multi-processor collaboration, comprising a main processor and a secondary processor, wherein the main processor is configured to implement the above-mentioned power backflow prevention method.

[0008] Furthermore, the main processor is an FPGA, and the secondary processor is a DSP.

[0009] Furthermore, signals on the same DSP are connected to the same BANK of the FPGA.

[0010] This invention perfectly solves the problem of power backflow during multi-processor collaborative operation through a series of power supply system optimizations. This invention ensures that during multi-processor collaborative operation, voltage and current backflow caused by port interconnection between processors will not affect the normal power-on sequence of the processors and cause operational anomalies. This invention can improve system reliability and ensure the normal operation of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of port interconnection between multiple processors in a specific embodiment of the present invention;

[0012] Figure 2 This is a principle block diagram of a system power supply design solution in a specific embodiment of the present invention;

[0013] Figure 3 A schematic diagram of a power-on timing sequence of a DSP processor in a specific embodiment of the present invention;

[0014] Figure 4 FIG. 1 is a power supply timing diagram of the DSP1 processor and the DSP2 processor in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0015] To better understand the objectives, technical solutions, and functions of the present invention, the present invention is described in further detail below with reference to the accompanying drawings. However, the present invention may be implemented in a variety of different ways as defined and covered by the claims. The accompanying drawings, which constitute a part of this invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute undue limitations of the present invention.

[0016] In a specific embodiment of the present invention, three processors are included, wherein the main processor can be FPGA, and the secondary processor can be DSP, respectively, one FPGA processor, model can be JFM7VX690T, and two DSP processors, model can be FT-M6678N. The port interconnection relationship between the above three processors is as follows: Figure 1 shown.

[0017] Among them, the interconnection interface between the DSP processor and the FPGA processor includes: EMIF bus interface, GPIO interface, high-speed SRIO interface and DSP-side reset signal, control signal, etc.; the high-speed SRIO interface is between the two DSP processors.

[0018] The system power supply is divided into three blocks, namely FPGA power supply system, DSP1 power supply system, and DSP2 power supply system. To prevent voltage backflow between processors after the system is powered on, the connection relationship between the three power supply systems of the processor is designed as follows: Figure 2 shown.

[0019] In one specific embodiment of the present invention, the HCE4644 power chip provides power to the core power supply, auxiliary power supply, and some I / O ports of the FPGA processor. After the FPGA boots up, it outputs an enable signal to two other power chips, which then power the corresponding DSP chips and the corresponding I / O pins of the FPGA chip connected to the DSP chip. The enable signal output by the FPGA controls the power timing of the DSP, ensuring normal chip startup.

[0020] In one specific embodiment of the present invention, hardware circuit design is used to achieve a power supply design that meets the timing requirements of each of the three processors and ensures that the interconnect pins between the processors do not backflow due to power timing issues, affecting their own timing. Specifically, the design controls the FPGA processor to complete power-up first. After the FPGA completes power-up and normal startup, software is designed to output an enable control signal to the enable pin of the power chip that powers the DSP processor. This output signal is designed to achieve power-up timing on the DSP side through a delay design. Furthermore, the corresponding bank power supply of the FPGA processor with interconnect pins to the DSP is set to the same power supply voltage as the IO power supply of the DSP processor, and they are powered on simultaneously.

[0021] In one embodiment of the present invention, signals from a single DSP processor are connected to the same bank of the FPGA processor to avoid signal fragmentation. This reduces the power supply from the DSP to the FPGA bank. This prevents voltage backflow when the three processors work together.

[0022] The following describes in detail the power supply system design of the FPGA processor and the power supply system design of the DSP processor in a specific embodiment of the present invention.

[0023] Part 1: FPGA power supply system design

[0024] 1) FPGA processor power supply requirements

[0025] The JFM7VX690T power supply list is shown in Table 1:

[0026] Table 1 JFM7VX690T power supply list

[0027]

[0028]

[0029] JFM7VX690T power-on sequence requirements:

[0030] VCCINT>VCCBRAM>VCCAUX>VCCO, VCCINT and VCCBRAM can be combined;

[0031] GTX / GTH power-on sequence requirements:

[0032] VCCINT>MGTAVCC>MGTAVTT>MGTVCCAUX.

[0033] 2) Power system design

[0034] This invention uses the HCE4644 DC / DC power supply chip from Sevenstar Huachuang to power the FPGA processor. This DC / DC power supply chip has an input voltage range of 4 to 14V and an adjustable output voltage of 0.6V to 5.5V. By controlling the enable pins of each channel of the power supply chip, each power supply can be powered on according to the required timing.

[0035] Here’s how it works:

[0036] The HCE4644 power chip connects the inverting input of each channel's error amplifier through the downstream FB pin. Inside the HCE4644 power chip, a precision resistor (e.g., 60.4kΩ) is connected between the FB pin and VOUT. Different output voltages can be set by connecting an external resistor between the FB pin and GND.

[0037] POOD pin: The indicator terminal of each channel to show whether the output is normal. When the channel level reaches the design value, the signal of the POOD pin is pulled up to 3.3V.

[0038] RUN pin: Enable pin. When the pin voltage is higher than 1.27V, the corresponding channel of the HCE4644 power chip starts to work; when the pin voltage is pulled down below 1V, the corresponding channel of the HCE4644 power chip stops and is disconnected.

[0039] The POOD pin of the previous channel controls the RUN pin of the next channel to realize the control of the two power supply timings, and realize the design of the power-on and power-on timing of each voltage of the FPGA processor.

[0040] Part 2: Design of DSP1 and DSP2 power supply system

[0041] 1) Power supply requirements for DSP processors

[0042] The power supply list of FT-M6678N is shown in Table 2:

[0043] Table 2 FT-M6678N (1GHz) power supply list

[0044]

[0045] FT-M6678 power-on sequence requirements:

[0046] VDD18>VDD>VDDQ>VDDP15>VDDP.

[0047] 2) Power system design

[0048] The difference is that the enable pin of the power chip is controlled by the FPGA processor. The power-on sequence is controlled by designing a delayed output logic.

[0049] like Figure 3 As shown in the figure, when designing the system power supply for DSP1 and DSP2 processors, the control signal output by the FPGA is sent to the RUN pin of the power supply chip to ensure that the power supply timing requirements of each power supply are met. In addition, the VDD18 powering the IO pins of the DSP chip also supplies the corresponding BANK of the interconnected FPGA to prevent backflow of the interconnection.

[0050] FPGA output control signal and timing requirements:

[0051] VDD18 control signal:

[0052] DSP1_VDD18_V7, output after V7 is powered on for 5ms (T0=5ms),

[0053] DSP2_VDD18_V7, output after V7 is powered on for 5ms (T0=5ms);

[0054] VDD control signal:

[0055] DSP1_VDD_V7, VDD18 output 20ms later,

[0056] DSP2_VDD_V7, VDD18 output after 20ms;

[0057] VDDQ control signal:

[0058] DSP1_VDDQ_V7, VDD output 5ms later,

[0059] DSP2_VDDQ_V7, VDD output 5ms later;

[0060] VDDP control signal:

[0061] DSP1_VDDP_V7, VDDQ output 10ms later,

[0062] DSP2_VDDP_V7, VDDQ output after 10ms;

[0063] VDDP15 control signal:

[0064] DSP1_VDDP15_V7, after VDDP output 5ms,

[0065] DSP2_VDDP15_V7, VDDP output after 5ms.

[0066] The power supply timing of DSP1 and DSP2 processors is as follows Figure 4 shown.

[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art may make various changes or modifications within the scope of the claims, which should all be included in the scope of protection of the present invention.

Claims

1. A method for preventing power backflow in multi-processor collaboration, characterized in that: The steps include: Step 1: Power on all ports on the main processor except the IO port interconnected with the secondary processor. Step 2: The main processor outputs an enable control signal to the power chip of the secondary processor to power on the secondary processor. The enable control signal is used to control the power-on timing of each port on the secondary processor. When the IO port on the secondary processor is powered on, the IO port on the main processor that is interconnected with the secondary processor is powered on synchronously.

2. A power backflow prevention circuit for multi-processor collaboration, characterized in that: The invention comprises a main processor and a secondary processor, wherein the main processor is configured to implement the method of claim 1.

3. The power backflow prevention circuit for multi-processor collaboration according to claim 2, characterized in that: The main processor is FPGA, and the secondary processor is DSP.

4. The power backflow prevention circuit for multi-processor collaboration according to claim 3, characterized in that: The signals on the same DSP are connected to the same BANK of the FPGA.

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