Memory management unit and request processing method based on RISC-V architecture
By classifying memory management unit requests and optimizing the processing flow, the problem of slow memory management unit address conversion is solved, and memory access efficiency and system performance are improved.
Patent Information
- Application Number
- CN202510822482.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-19
- Publication Date
- 2025-09-26
AI Technical Summary
Existing memory management units process address translation requests slowly, resulting in memory access delays and overall system performance degradation.
By classifying the requests of the memory management unit and adding priority judgment actions in the processing process, including access permission requests, page fault requests and general requests, the virtual-to-real address conversion process is optimized and the main memory access in the case of cache miss is reduced.
It speeds up the conversion from virtual addresses to physical addresses, reduces memory access latency, and improves the overall performance and resource utilization efficiency of the chip.
Smart Images
Figure CN120705081A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a memory management unit and a request processing method based on a RISC-V architecture. Background Art
[0002] The Memory Management Unit (MMU) used in RISC-V processors plays a key role in computer architecture. The two basic functions of MMU are virtual-to-real address translation and memory protection. Figure 1 The RISC-V architecture diagram shown in the figure shows the main functions of the memory management unit (MMU), including address translation, memory protection, cache management, exception handling, translation lookaside buffer (TLB), and multi-level page tables. Through address translation, the MMU maps virtual addresses to physical addresses, enabling programs to access actual memory. The basic process is that the execution unit requests data from main memory via the address bus. For system architectures with an MMU module, the VA to PA conversion is completed, and then the data is requested from main memory. The CPU obtains the data via the data bus. The TLB is used to store the mapping between recently used virtual addresses and physical addresses to accelerate the address translation process. Multi-level page table structures (such as two-level or three-level page tables) support large memory spaces and flexible address mapping. The memory management unit (MMU) performs address translation through the TLB. In the event of a TLB miss, the page table is searched and the corresponding address translation information is updated in the TLB.
[0003] The current virtual-to-real address conversion process in MMU is as follows Figure 2 As shown in , its address conversion includes two cases:
[0004] (1) When the processor requests access to a virtual address VA and the MMU's TLB hits Hit, the MMU generates a PTE and requests it from the cache; the cache returns the PTE to the MMU; the MMU constructs a physical address and passes the physical address to the cache, and the cache returns the requested data to the processor.
[0005] (2) When the processor issues a request to access the virtual address VA and the MMU's TLB does not hit a Miss, the PTEA (PTE address) in the main memory page table is traversed through the TWU. The main memory returns the PTE to the MMU. The valid bit in the PTE is 0, and the MMU triggers an exception. The CPU responds with a page fault exception and runs the corresponding handler. The page fault exception handler selects the victim page in the physical memory. If this page has been modified, it is swapped out to the EMMC. The page fault exception handler loads the new page from the EMMC and updates the PTE in the page table in memory. The page fault exception handler returns to the original process and executes the instruction that caused the page fault again. The CPU resends the virtual address that caused the page fault exception to the MMU. Since the virtual page is now cached in the main memory, the main memory returns the content corresponding to the requested address to the cache and the processor.
[0006] The MMU obtains the base address of the first-level page table PGD by accessing the page table base register, and then finds the base address of the next-level page table PTE in combination with the PGD index in the virtual address; after obtaining the base address of the PTE, it finds the PFN in combination with the PTEindex in the virtual address, and then adds it to the VA to obtain the physical address.
[0007] Currently, the MMU virtual-to-real address translation request process is as follows: Figure 3 As shown, the process can be roughly divided into four parts. When an access request is received from the processor, it is first determined whether the TLB hits. ① TLB replacement process: TLB miss (Miss), access the main memory page table and determine whether the page table exists. If it exists, update the TLB and convert VA to PA. ② Page fault replacement process: When the page table is not in the main memory and there are free page frames, replace it and update the page table and TLB. ③ VA to PA process: After the TLB hit (Hit), it means that there is a mapping relationship between the virtual address (VA) and the physical address (PA) in the page table. The corresponding data or instruction in the cache does not need to be further retrieved from the main memory. ④ Cache replacement process: When the corresponding data or instruction does not exist in the cache, determine whether there is a free line in the cache, retrieve data from the main memory and replace it in the cache, and implement the corresponding position data replacement process.
[0008] However, frequent address translation requests result in cache misses, which require data or instructions to be retrieved from the main memory, increasing the latency of memory access. Compared with directly retrieving data from the cache, reading data from the main memory takes more time, thereby reducing the processing speed of address translation requests and reducing conversion efficiency.
[0009] At the same time, the processor will be idle while waiting for main memory to obtain data, which leads to a waste of resources. Frequent cache misses will prevent the processor from executing other instructions while waiting for data, thereby affecting the overall efficiency and performance of the system. Summary of the Invention
[0010] The purpose of the present invention is to provide a memory management unit and a request processing method based on the RISC-V architecture to solve the problem of slow processing speed of address translation requests in existing memory management units.
[0011] In order to achieve the above objectives, in a first aspect, the present invention provides a request processing method for a memory management unit based on the RISC-V architecture, comprising:
[0012] receiving an access request sent by a processor;
[0013] Classifying the access request to obtain a classification result;
[0014] Execute corresponding virtual-to-real address conversion operations according to the classification results.
[0015] Furthermore, the classification result includes one of the following:
[0016] Access rights requests;
[0017] Page fault request;
[0018] General Requests;
[0019] The general request is a request other than an access permission request and a page fault request.
[0020] Furthermore, performing a corresponding virtual-to-real address conversion operation according to the classification result includes:
[0021] If the classification result is a general request, a response request operation is performed.
[0022] Furthermore, performing a corresponding virtual-to-real address conversion operation according to the classification result includes:
[0023] If the classification result is an access permission request, a mapping relationship is found in the TLB and the corresponding data or instruction is found and returned.
[0024] Furthermore, performing a corresponding virtual-to-real address conversion operation according to the classification result includes:
[0025] If the classification result is a page fault request, determining whether a TLB hit occurs;
[0026] If the TLB misses, perform TLB update page table and replacement operations;
[0027] If the TLB hits, the corresponding data or instruction is searched in the cache; or, when the corresponding data or instruction does not exist in the cache, it is determined whether there is a free line in the cache, and the data is taken from the main memory and replaced in the cache.
[0028] In a second aspect, the present invention further provides a memory management unit based on the RISC-V architecture, comprising:
[0029] A request receiving module, configured to receive an access request sent by a processor;
[0030] A request classification module, configured to classify the access request and obtain a classification result;
[0031] An operation execution module is used to execute the corresponding virtual-to-real address conversion operation according to the classification result.
[0032] Furthermore, the classification result includes one of the following:
[0033] Access rights requests;
[0034] Page fault request;
[0035] General Requests;
[0036] The general request is a request other than an access permission request and a page fault request.
[0037] Furthermore, the operation execution module is specifically used to:
[0038] If the classification result is a general request, a response request operation is performed.
[0039] Furthermore, the operation execution module is specifically used to:
[0040] If the classification result is an access permission request, a mapping relationship is found in the TLB and the corresponding data or instruction is found and returned.
[0041] Furthermore, the operation execution module is specifically used to:
[0042] If the classification result is a page fault request, determining whether a TLB hit occurs;
[0043] If the TLB misses, perform TLB update page table and replacement operations;
[0044] If the TLB hits, the corresponding data or instruction is searched in the cache; or, when the corresponding data or instruction does not exist in the cache, it is determined whether there is a free line in the cache, and the data is taken from the main memory and replaced in the cache.
[0045] In the request processing method of the memory management unit based on the RISC-V architecture provided by the present invention, the memory management unit first classifies the various types of requests received, and then performs corresponding operations on the classified requests according to the processing flow, and adds priority judgment actions in the processing process to speed up the speed of looking up missing table entries. In addition, it solves the conflict problem between lookup requests and access permission requests to a certain extent, speeds up the speed of virtual-to-real address conversion while reducing memory access latency, thereby improving the overall performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 A simplified diagram based on the RISC-V architecture provided as background technology for this application;
[0047] Figure 2 The MMU virtual-to-real address conversion process provided by the background technology of this application;
[0048] Figure 3 The existing MMU request processing flow provided by the background technology of this application;
[0049] Figure 4 A flowchart of a request processing method for a memory management unit based on the RISC-V architecture provided in an embodiment of the present application;
[0050] Figure 5 The improved MMU request processing process provided in the embodiment of the present application;
[0051] Figure 6 A structural block diagram of a memory management unit based on the RISC-V architecture provided in an embodiment of the present application;
[0052] In the figure, 201 is a request receiving module; 202 is a request classification module; and 203 is an operation execution module. DETAILED DESCRIPTION
[0053] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.
[0054] The English abbreviations in this embodiment are defined as:
[0055] CPU: Central Processing Unit;
[0056] MMU: memory management unit;
[0057] TLB: Translation Lookaside Buffer;
[0058] Cache: cache memory;
[0059] First, as Figure 4 As shown, an embodiment of the present invention provides a request processing method for a memory management unit based on the RISC-V architecture. The method includes the following:
[0060] Step S100: receiving an access request sent by a processor.
[0061] Step S200: classify the access request to obtain a classification result.
[0062] Specifically, the classification result includes one of the following: access permission request; page fault request; general request; wherein the general request is a request other than the access permission request and the page fault request.
[0063] Specifically, in this embodiment, in order to improve the efficiency of processing requests, a priority judgment action is added during the process of classifying the access requests, such as Figure 5 As shown, when classifying the access request, it is first determined whether the access request sent by the processor is a general request; if not, it is then determined whether it is an access permission request; if not, the access request is identified as a page fault request.
[0064] It should be noted that after determining that the access request is an access permission request, if the mapping relationship cannot be found in the TLB and the corresponding data or instruction cannot be returned, the access request will be re-identified as a page fault request.
[0065] In this embodiment, an access permission request is defined as the CPU sending an address translation request to the MMU, providing a virtual address so that the MMU can convert it into the corresponding physical address, thereby correctly accessing the data or instructions in the memory. The CPU may request the MMU to perform an access permission check to ensure that the read, write, or execute operation on the memory complies with the set permission rules. In this case, the MMU verifies the access permission bits to determine whether to allow access to the memory area.
[0066] The definition of a page fault request is: the CPU may request the MMU to access the TLB to speed up the address translation process. The TLB is a high-speed cache that stores the most recent mappings from virtual addresses to physical addresses. The CPU can directly access the TLB to obtain the translation result without having to request the MMU to perform a complete address translation process every time. If the page accessed by the CPU is not in memory, the MMU will cause a page fault exception. The CPU may request the MMU to handle this exception, triggering the operating system to load the missing page to satisfy the access request. If the required address mapping is not in the TLB, the CPU may request the MMU to handle the TLB miss, that is, to re-execute the complete address translation process to obtain the required address mapping information.
[0067] Step S300: performing corresponding virtual-to-real address conversion operations according to the classification results.
[0068] like Figure 5 As shown, there are three specific situations:
[0069] The first type: if the classification result is a general request, perform a response request operation.
[0070] The second method: if the classification result is an access permission request, a mapping relationship is found in the TLB and the corresponding data or instruction is found and returned.
[0071] The third type: If the classification result is a page fault request, determine whether the TLB hits; if the TLB does not hit, perform TLB update page table and replacement operations; if the TLB hits, search for the corresponding data or instruction in the cache; or, when the corresponding data or instruction does not exist in the cache, determine whether there is a free line in the cache, take the data from the main memory and replace it in the cache.
[0072] Based on the same inventive concept, in a second aspect, an embodiment of the present invention further provides a memory management unit based on the RISC-V architecture. Figure 6 As shown, the memory management unit includes:
[0073] A request receiving module 201 is configured to receive an access request sent by a processor;
[0074] A request classification module 202 is configured to classify the access request and obtain a classification result;
[0075] The operation execution module 203 is configured to execute a corresponding virtual-to-real address conversion operation according to the classification result.
[0076] Specifically, the classification result includes one of the following: access permission request; page fault request; general request; wherein the general request is a request other than the access permission request and the page fault request.
[0077] Specifically, in this embodiment, in order to improve the efficiency of processing requests, the request classification module 202 adds a priority judgment action in the process of classifying the access request, such as Figure 5 As shown, when classifying the access request, it is first determined whether the access request sent by the processor is a general request; if not, it is then determined whether it is an access permission request; if not, the access request is identified as a page fault request.
[0078] It should be noted that after determining that the access request is an access permission request, if the mapping relationship cannot be found in the TLB and the corresponding data or instruction cannot be returned, the access request will be re-identified as a page fault request.
[0079] In this embodiment, an access permission request is defined as the CPU sending an address translation request to the MMU, providing a virtual address so that the MMU can convert it into the corresponding physical address, thereby correctly accessing the data or instructions in the memory. The CPU may request the MMU to perform an access permission check to ensure that the read, write, or execute operation on the memory complies with the set permission rules. In this case, the MMU verifies the access permission bits to determine whether to allow access to the memory area.
[0080] The definition of a page fault request is: the CPU may request the MMU to access the TLB to speed up the address translation process. The TLB is a high-speed cache that stores the most recent mappings from virtual addresses to physical addresses. The CPU can directly access the TLB to obtain the translation result without having to request the MMU to perform a complete address translation process every time. If the page accessed by the CPU is not in memory, the MMU will cause a page fault exception. The CPU may request the MMU to handle this exception, triggering the operating system to load the missing page to satisfy the access request. If the required address mapping is not in the TLB, the CPU may request the MMU to handle the TLB miss, that is, to re-execute the complete address translation process to obtain the required address mapping information.
[0081] In this embodiment, the operation execution module is specifically used to:
[0082] If the classification result is a general request, executing a response request operation;
[0083] If the classification result is an access permission request, find a mapping relationship in the TLB and return the corresponding data or instruction;
[0084] If the classification result is a page fault request, determine whether the TLB hits; if the TLB does not hit, perform TLB update page table and replacement operations; if the TLB hits, search and obtain the corresponding data or instructions in the cache; or, when the corresponding data or instructions do not exist in the cache, determine whether there is a free line in the cache, take data from the main memory and replace it in the cache.
[0085] In summary, in the memory management unit and request processing method based on the RISC-V architecture provided by the present invention, the memory management unit first classifies the various types of requests received, and then performs corresponding operations on the classified requests according to the processing flow, and adds priority judgment actions in the processing process to speed up the search for missing table entries. In addition, it solves the conflict problem between search requests and access permission requests to a certain extent, speeds up the conversion of virtual and real addresses, and reduces memory access delays, thereby improving the overall performance of the chip.
[0086] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.
[0087] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.
[0088] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0089] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.
Claims
1. A request processing method for a memory management unit based on a RISC-V architecture, characterized in that: include: receiving an access request sent by a processor; Classifying the access request to obtain a classification result; Execute corresponding virtual-to-real address conversion operations according to the classification results.
2. A request processing method for a memory management unit based on a RISC-V architecture as claimed in claim 1, characterized in that: The classification result includes one of the following: Access rights requests; Page fault request; General Requests; The general request is a request other than an access permission request and a page fault request.
3. A request processing method for a memory management unit based on a RISC-V architecture as claimed in claim 2, characterized in that: The performing of the corresponding virtual-to-real address conversion operation according to the classification result includes: If the classification result is a general request, a response request operation is performed.
4. A request processing method for a memory management unit based on a RISC-V architecture as claimed in claim 2, characterized in that: The performing of the corresponding virtual-to-real address conversion operation according to the classification result includes: If the classification result is an access permission request, a mapping relationship is found in the TLB and the corresponding data or instruction is found and returned.
5. The request processing method of a memory management unit based on the RISC-V architecture according to claim 2, characterized in that: The performing of the corresponding virtual-to-real address conversion operation according to the classification result includes: If the classification result is a page fault request, determining whether a TLB hit occurs; If the TLB misses, perform TLB update page table and replacement operations; If the TLB hits, the corresponding data or instruction is searched in the cache; or, when the corresponding data or instruction does not exist in the cache, it is determined whether there is a free line in the cache, and the data is taken from the main memory and replaced in the cache.
6. A memory management unit based on RISC-V architecture, characterized in that: include: A request receiving module, configured to receive an access request sent by a processor; A request classification module, configured to classify the access request and obtain a classification result; An operation execution module is used to execute the corresponding virtual-to-real address conversion operation according to the classification result.
7. A memory management unit based on RISC-V architecture according to claim 6, characterized in that: The classification result includes one of the following: Access rights requests; Page fault request; General Requests; The general request is a request other than an access permission request and a page fault request.
8. A memory management unit based on RISC-V architecture according to claim 7, characterized in that: The operation execution module is specifically used to: If the classification result is a general request, a response request operation is performed.
9. A memory management unit based on RISC-V architecture according to claim 7, characterized in that: The operation execution module is specifically used to: If the classification result is an access permission request, a mapping relationship is found in the TLB and the corresponding data or instruction is found and returned.
10. A memory management unit based on RISC-V architecture according to claim 7, characterized in that: The operation execution module is specifically used to: If the classification result is a page fault request, determining whether a TLB hit occurs; If the TLB misses, perform TLB update page table and replacement operations; If the TLB hits, the corresponding data or instruction is searched in the cache; or, when the corresponding data or instruction does not exist in the cache, it is determined whether there is a free line in the cache, and the data is taken from the main memory and replaced in the cache.