STA time sequence analysis optimization method and device based on OPC, medium, program product and terminal

Abstract

The invention provides an OPC-based STA time sequence analysis optimization method and device, a medium, a program product and a terminal, and the method comprises the steps: obtaining layout data before extracting parasitic parameters, executing first STA time sequence analysis, rapidly positioning a key path, carrying out the optical proximity effect correction and fitting of the key path, generating a layout which is highly fitted with a real manufacturing state, and carrying out the optimization of the STA time sequence analysis. And through second STA time sequence analysis, comprehensive and fine evaluation of a correction path is realized, and accurate verification and optimization of time sequence convergence are guaranteed. The problems that design resources are wasted, time sequence verification is not accurate and chip time sequence risks are difficult to control due to the fact that traditional time sequence verification is too conservative and insufficient in accuracy are solved. The time sequence verification precision and efficiency are remarkably improved, redundant calculation and resource consumption of a non-critical area are reduced, the method is suitable for advanced process chip design, efficient and reliable time sequence convergence under the manufacturing deviation environment is achieved, and the chip performance and the production yield are ensured.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to an OPC-based STA timing analysis optimization method, device, medium, program product, and terminal. Background Art

[0002] As process nodes continue to shrink and chip logic complexity increases, layout variations that occur during the manufacturing process, such as line width variations and proximity effects, are increasingly impacting chip timing performance. Currently, designers typically reserve timing margins during static timing analysis (STA), conservatively estimating performance fluctuations caused by manufacturing variations to ensure timing closure after chip fabrication. These methods often use empirical models to roughly estimate process variations, assisting with STA timing verification during the design phase.

[0003] However, conservative estimation methods fail to accurately reflect actual layout variations caused by the manufacturing process and their impact on timing. Consequently, the margins reserved in the design are often overly pessimistic, wasting design resources while failing to accurately predict timing deviations caused by manufacturing errors. Ignoring true manufacturing effects can significantly increase STA timing analysis errors, in some cases as high as 15%. Timing closure is particularly problematic at advanced process nodes and with complex logic chips. The lack of effective means to comprehensively assess manufacturing impacts during the design phase makes it difficult to accurately control the timing risk of the final chip. Summary of the Invention

[0004] In view of the shortcomings of the existing technology mentioned above, the purpose of this application is to provide an OPC-based STA timing analysis optimization method, device, medium, program product and terminal to solve the problem that manufacturing deviations have a significant impact on chip timing performance under advanced process nodes, and the existing design methods are too conservative and lack precision, resulting in inaccurate timing verification, waste of design resources and difficulty in effectively controlling the final chip timing risks.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an OPC-based STA timing analysis optimization method, including: obtaining a first layout; when the first layout meets a first preset standard, performing a first STA timing analysis operation on the first layout to generate a critical path; based on the critical path, performing an OPC correction operation on the first layout to generate a second layout; performing an OPC fitting operation on the second layout to generate a third layout; performing the second STA timing analysis operation on the third layout to generate an STA analysis result.

[0006] In some embodiments of the first aspect of the present application, the first preset standard includes: if the advanced process node in the first layout shown is greater than a preset threshold, then the first layout does not meet the first preset standard; if the advanced process node in the first layout shown is less than or equal to the preset threshold, then the first layout meets the first preset standard.

[0007] In some embodiments of the first aspect of the present application, the process of performing a first STA timing analysis operation on the first layout to generate a critical path includes: extracting corresponding circuit description data from the first layout; constructing a timing network model based on the circuit description data; in the timing network model, calculating the signal arrival time from the input port to each node to generate arrival time data; calculating the timing margin corresponding to each node through the arrival time data and preset timing constraints; based on the time margin, identifying and extracting the path that meets the preset conditions as the critical path.

[0008] In some embodiments of the first aspect of the present application, the process of identifying and extracting paths that meet preset conditions as critical paths includes: identifying and extracting paths with timing violations as critical paths; and / or identifying and extracting paths that cannot converge as critical paths.

[0009] In some embodiments of the first aspect of the present application, based on the critical path, an OPC correction operation is performed on the first layout to generate a second layout. The process includes: obtaining and loading an OPC model file; in the first layout, performing a simulated exposure calculation for the corresponding area of ​​the critical path to generate light intensity distribution data; based on the light intensity distribution data, calculating the edge offset of the corresponding area of ​​the critical path, and performing an offset correction on the corresponding area of ​​the critical path in the first layout to generate a second layout.

[0010] In some embodiments of the first aspect of the present application, the process of performing an OPC fitting operation on the second layout to generate a third layout includes: performing manufacturing process simulation and fitting calculation on the second layout based on the process sub-model in the OPC model file to generate a third layout representing the actual process deformation.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an OPC-based STA timing analysis and optimization device, including: a data acquisition module: used to acquire a first layout; a path optimization module: used to perform a first STA timing analysis operation on the first layout when the first layout meets a first preset standard to generate a critical path; based on the critical path, perform an OPC correction operation on the first layout to generate a second layout; perform an OPC fitting operation on the second layout to generate a third layout; and a STA analysis module: used to perform the second STA timing analysis operation on the third layout to generate an STA analysis result.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the OPC-based STA timing analysis optimization method when executed by a processor.

[0013] To achieve the above-mentioned objectives and other related objectives, the fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code is run on a computer, the computer implements the OPC-based STA timing analysis optimization method.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the OPC-based STA timing analysis optimization method.

[0015] As described above, the OPC-based STA timing analysis optimization method, device, medium, program product and terminal of the present application have the following beneficial effects: The present application adopts a layered and targeted STA analysis process, which effectively avoids the blind optimization of the entire layout in the traditional method, thereby realizing efficient utilization of design resources. By focusing on the precise optimization of the critical path, not only the problem of insufficient accuracy in the existing timing verification is solved, but also the overall verification efficiency is significantly improved. In addition, the present application also reduces redundant calculations and resource waste in non-critical areas, further enhancing the rationality and economy of the design process. With this optimization strategy, the present application is particularly suitable for chip design under advanced processes, and can achieve efficient and reliable timing convergence in an environment with a large impact of manufacturing deviations, ultimately ensuring the stability of chip performance and a significant improvement in production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of an embodiment of the OPC-based STA timing analysis optimization method of the present application is shown.

[0017] Figure 2 A flow chart of another embodiment of the OPC-based STA timing analysis and optimization method of the present application is shown.

[0018] Figure 3 A schematic diagram of the timing constraints of setup time and hold time in an embodiment of the OPC-based STA timing analysis and optimization method of the present application is shown.

[0019] Figure 4 A structural diagram of an embodiment of an OPC-based STA timing analysis and optimization device of the present application is shown.

[0020] Figure 5 A structural diagram of an embodiment of an OPC-based STA timing analysis and optimization terminal of the present application is shown. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0022] Before further explaining the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

[0023] <1> OPC correction operation: In integrated circuit manufacturing, OPC (Optical Proximity Correction) correction operation refers to the pre-adjustment of the geometric shape of the mask pattern to compensate for the pattern distortion caused by optical effects such as diffraction and interference during the photolithography process, ensuring that the circuit structure formed on the silicon wafer is highly consistent with the design drawing.

[0024] <2> OPC fitting operation: OPC fitting operation refers to the comparison of actual lithography imaging results with ideal design patterns through mathematical models and algorithms during the OPC correction process, and the calculation of optimal correction parameters and correction patterns to minimize lithography errors and achieve higher pattern fidelity.

[0025] <3> Static Timing Analysis (STA) is a method for verifying the timing performance of digital integrated circuits by calculating the delays of all possible signal propagation paths in a circuit without running the circuit. It is used to ensure that signals arrive in time and meet timing requirements such as setup and hold times at a given clock frequency.

[0026] <4> Circuit description data: Circuit description data refers to the digital information used to fully describe the function, structure, and interconnection relationships of integrated circuits. This includes gate-level netlists, transistor-level netlists, physical layout information, timing models, power consumption models, and other information. It is the foundation for circuit design, verification, and manufacturing.

[0027] <5> Timing network model: A timing network model is an abstract model used to represent the signal propagation paths and delay characteristics in integrated circuits. It typically consists of logic gates, interconnects, and the timing relationships between them (such as propagation delay, setup time, and hold time). It serves as the basis for static timing analysis and timing verification.

[0028] <6> Advanced process nodes: Advanced process nodes refer to semiconductor manufacturing processes where transistor feature sizes (such as gate length) reach or exceed a specific micron or nanometer level. For example, 28nm, 14nm, 7nm, and 5nm are all advanced process nodes, which generally indicate higher transistor density, lower power consumption, and higher performance.

[0029] <7> Setup time: Setup time is the minimum time a data signal must remain stable before the clock's active edge arrives. If the data signal changes within the setup time window, the D-type flip-flop may not capture the data correctly, resulting in a timing violation.

[0030] <8> Hold time: Hold time is the minimum time a data signal must remain stable after the clock's active edge. If the data signal changes within the hold time window, the D-type flip-flop may not capture the data correctly, resulting in a timing violation.

[0031] <9> A D-type flip-flop is a basic digital logic storage unit with a data input (D), a clock input (CLK), and an output (Q). It latches the state of the data input to the output on a specific clock edge (usually a rising or falling edge), storing one bit of data.

[0032] <10> Timing Margin: Timing margin is the difference between the actual signal arrival time and the expected signal arrival time in a circuit. A positive timing margin indicates that the circuit meets the timing requirements with margin; a negative timing margin indicates that the circuit has a timing violation and the signal fails to arrive in time.

[0033] <11> Parasitics: Parasitics refer to non-ideal electrical effects in integrated circuits, such as parasitic resistance, capacitance, and inductance, that arise from the physical properties of device structures and interconnects. These parameters affect circuit performance, power consumption, and reliability, requiring precise modeling and analysis during design.

[0034] To facilitate understanding of the embodiments of the present application, first Figure 1 Provide explanation. Figure 1 A flow chart of an OPC-based STA timing analysis optimization method in an embodiment of the present application is shown. Figure 2 The following is a flow chart of another embodiment of the present application. The OPC-based STA timing analysis optimization method in this embodiment mainly includes the following steps:

[0035] Step S11: Obtain a first layout.

[0036] In one embodiment of the present application, the first layout refers to the graphic data layer contained in a GDSII (Graphic Data System II) format layout file before parasitic parameter extraction. It should be noted that the method proposed in this application considers the influence of the optical proximity effect (OPC) when extracting chip parasitic parameters RC to obtain RC values ​​that are closer to actual conditions. This application helps improve the accuracy of chip timing analysis, thereby achieving more effective timing closure.

[0037] Step S12: When the first layout meets the first preset standard, perform a first STA timing analysis operation on the first layout to generate a critical path; based on the critical path, perform an OPC correction operation on the first layout to generate a second layout; perform an OPC fitting operation on the second layout to generate a third layout.

[0038] In one embodiment of the present application, the first preset standard includes: if the advanced process node in the first layout shown is greater than a preset threshold, then the first layout does not meet the first preset standard; if the advanced process node in the first layout shown is less than or equal to the preset threshold, then the first layout meets the first preset standard.

[0039] In this embodiment, the first preset standard includes a judgment on the relationship between the advanced process node in the layout and the preset threshold. When the value of the advanced process node in the first layout shown is greater than the preset threshold, the first layout is considered to not meet the first preset standard. Conversely, when the value of the advanced process node in the first layout shown is less than or equal to the preset threshold, the first layout is considered to meet the first preset standard. More preferably, the preset threshold is set to 28nm. That is, if the advanced process node shown in the layout is 28nm or less, the layout is judged to meet the first preset standard; if the advanced process node shown in the layout is greater than 28nm, the layout is judged to not meet the first preset standard. This setting is intended to screen out layouts that may make STA timing analysis difficult to converge.

[0040] In one embodiment of the present application, the process of performing a first STA timing analysis operation on the first layout to generate a critical path includes: extracting corresponding circuit description data from the first layout; constructing a timing network model based on the circuit description data; in the timing network model, calculating the signal arrival time from the input port to each node to generate arrival time data; calculating the timing margin corresponding to each node through the arrival time data and preset timing constraints; based on the time margin, identifying and extracting the path that meets the preset conditions as the critical path.

[0041] The process of identifying and extracting paths that meet preset conditions as critical paths includes: identifying and extracting paths that violate timing as critical paths; and / or identifying and extracting paths that fail to converge as critical paths. Failure to converge means that a stable arrival time and delay result cannot be achieved after multiple iterations.

[0042] In this embodiment, circuit description data is first extracted from the first layout. This circuit description data includes, but is not limited to, a netlist, unit delays, and a topology. The netlist fully characterizes the interconnections between circuit units, the unit delay represents the delay variation of each gate circuit or flip-flop under different input transition times and load conditions, and the topology explicitly describes the signal propagation path through each unit and network node.

[0043] Furthermore, the process of constructing a timing network model based on the circuit description data includes establishing the combinational logic of all clock-related triggers and data paths and their connection methods. Specifically, by parsing the netlist and topology structure, combined with unit delays, a timing network model covering the data and clock propagation paths of the entire circuit is established. The timing network model includes mapping the signal flow on each data path, as well as key nodes such as clock enable and data sampling associated with the signal initiation port to each downstream node. In the timing network model, each propagation path is accompanied by corresponding timing constraints, including setup time, hold time, and other time windows for synchronization with the clock signal.

[0044] Specifically, Figure 3 A schematic diagram of the timing constraints for setup and hold times in one embodiment of the present application is shown. It consists of two D-type flip-flops, DFF1 and DFF2, and a logic module in between. The clock signal (clk) is synchronously fed to the CK terminals of the two DFFs through a buffer. The Q terminal of DFF1 is connected to the D terminal of DFF2 via a logic module, forming a data timing path. The buffer reflects clock delay. This model is the basis for STA timing analysis and is used to evaluate key parameters such as data path delay, clock path delay, setup time, and hold time. This embodiment compares the signal arrival time (Data Arrival Time) and the required time (Data Required Time) with the trigger timing requirements to determine whether there is a timing violation (Timing Violation) and ensure the correctness of circuit functionality.

[0045] Furthermore, after the model is established, a detailed signal arrival time calculation is performed for each data path. The calculation process is shown in formula 1. Indicates the delay of the port initiated by the clock, Indicates the response delay from the trigger CK to Q, Indicates the corresponding delay of the combinational logic path. For a specific data path, such as from the first-level trigger (DFF1) through the combinational logic to the next trigger (DFF2), calculate the propagation time of the data along the maximum and minimum logic delay paths respectively. The latest time point that the data needs to arrive The calculation process is shown in Formula 2, where Represents one clock cycle, It represents the delay time of the clock signal reaching the clock input of the flip-flop DFF2. Indicates the setup time of the trigger.

[0046] (Formula 1)

[0047] (Formula 2)

[0048] In this embodiment, the process of calculating the timing margin corresponding to each node using the arrival time data and preset timing constraints includes: using the setup time of the current node according to Formula 3 to characterize the margin for early or late arrival of the data. When the margin is positive, it indicates that the data arrived within the agreed window and did not violate the timing constraint; if the margin is negative, a timing violation occurs, indicating that the path cannot meet the setup time requirement; and calculating the hold time of the current node according to Formula 4. It is also necessary to ensure that the result is greater than zero. Once a negative margin occurs, the path is a timing abnormal path.

[0049] (Formula 3)

[0050] (Formula 4)

[0051] Finally, based on the timing margins, the process of identifying and extracting problematic paths that meet preset conditions involves traversing all signal paths and determining each path's setup and hold margins based on their timing margins. Paths with setup or hold margin violations are directly identified as critical paths for optimization. Preferably, paths with near-critical timing margins, unreliable stability, or difficulty converging under various process corner cases (e.g., Cmax, Cmin, RCmax, RCmin, etc.) are also identified as critical paths.

[0052] The above criteria are adopted because the formation of critical paths is not only affected by cell delay, combinational logic delay, and network topology, but is also closely related to metal layer resistance, capacitance, and manufacturing process parameters. Fluctuations in process parameters such as metal layer width, thickness, and insulation spacing directly affect RC parameter changes, thereby affecting signal propagation time, causing the timing margin of these paths to become a performance and stability bottleneck. Therefore, by extracting these paths with timing risks, subsequent OPC correction operations can better avoid chip timing risks.

[0053] In one embodiment of the present application, the process of performing a first STA timing analysis operation on the first layout to generate a critical path also includes: the circuit description data also includes register clock pins and their clock tree topology information, and the topology information is used to build a timing network model. In the process of building the timing network model, clock edges are established for the chip's external start and end ports and each register CK pin, and their weights are set to clk2reg delay. Subsequently, for each data node, the arrival time of the data signal from the input port to the register D end is calculated; and for each clock node, the arrival time of the clock signal from the chip's external start and end ports to the register CK end is calculated to obtain clk2reg. Using clk2reg as the arrival time of the register clock end, it is calculated with the preset setup / hold time constraints to obtain the timing margin corresponding to each node.

[0054] In one embodiment of the present application, based on the critical path, an OPC correction operation is performed on the first layout to generate a second layout. The process includes: obtaining and loading an OPC model file; in the first layout, performing a simulated exposure calculation for the corresponding area of ​​the critical path to generate light intensity distribution data; based on the light intensity distribution data, calculating the edge offset of the corresponding area of ​​the critical path, and performing an offset correction on the corresponding area of ​​the critical path in the first layout to generate a second layout.

[0055] In this embodiment, an OPC model file is obtained and loaded. The OPC model file contains parameters and algorithms for performing optical proximity effect correction. In the first layout, a simulated exposure calculation is performed for a specific area corresponding to the critical path to simulate the propagation of light through the mask during the photolithography process, thereby generating light intensity distribution data, which reflects the intensity distribution of light in the layout area. Subsequently, based on the generated light intensity distribution data, the edge offset of the area corresponding to the critical path is calculated. The offset characterizes the deviation between the layout edge and the ideal design position due to the optical proximity effect. Finally, based on the calculated edge offset, the area corresponding to the critical path in the first layout is offset corrected, that is, the layout pattern of the area is adjusted to compensate for the influence of the optical proximity effect, thereby generating a corrected second layout.

[0056] Preferably, OPC corrections can be performed on specific layers using OPC scripts provided by a foundry. Foundry refers to semiconductor wafer foundries that provide integrated circuit manufacturing services and offer specialized OPC scripts and models to ensure pattern manufacturability under their manufacturing processes. Applying OPC corrections effectively improves pattern manufacturability and enhances pattern consistency between the wafer's edge and center regions, thereby ensuring chip performance and yield.

[0057] In one embodiment of the present application, the process of performing an OPC fitting operation on the second layout to generate a third layout includes: based on the process sub-model in the OPC model file, performing manufacturing process simulation and fitting calculation on the second layout to generate a third layout representing the actual process deformation.

[0058] In this embodiment, manufacturing process simulation and fitting calculations are performed on the second layout based on the process sub-model included in the OPC model file. Specifically, after all wiring layers have completed OPC processing and obtained corrected graphic shapes, graphic fitting is performed on different layers based on the layer model for a specific process node provided by the foundry. This ensures that the graphic of each layer is adjusted according to its corresponding process model parameters, simulating the deformation of the layer under actual manufacturing conditions.

[0059] It should be noted that this application uses a hierarchical STA timing analysis strategy, in which the operations of the first STA timing analysis and the second STA timing analysis can be the same or different. When the two operations are different, the first STA timing analysis is first performed on the post-routing layout to perform basic screening and quickly identify critical paths (i.e., paths with timing violations or difficult-to-converge paths). Subsequently, OPC corrections and fitting are performed only on these critical paths to generate a third layout of the actual wafer state. Finally, a more comprehensive second STA timing analysis is performed to accurately evaluate the correction effect and ensure timing convergence. This process achieves precise positioning, targeted processing of critical paths, and full-process resource optimization through differentiated STA analysis, significantly improving efficiency while ensuring performance.

[0060] Step S13: performing the second STA timing analysis operation on the third layout to generate a STA analysis result.

[0061] In one embodiment of the present application, based on the above steps, a parasitic parameter extraction operation is further performed on the third layout. The parasitic parameters include but are not limited to the resistance, capacitance and inductance on the interconnect. Accurate parasitic parameters are crucial for STA timing analysis, which relies on accurate R, C, and L parasitic parameters to accurately calculate and evaluate the timing characteristics of the circuit, such as delay, setup time and hold time. By extracting layout parasitic parameters that more realistically reflect the manufacturing situation, more accurate input data can be provided for the STA process, thereby significantly improving the accuracy and reliability of timing verification, effectively reducing unnecessary design margins, and ultimately achieving precise control of chip timing risks.

[0062] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same function or effect. For example, the first and second layouts are used solely to distinguish between different layouts and do not define their order. Those skilled in the art will understand that terms such as "first" and "second" do not define the quantity or order of execution, and do not necessarily imply that the terms are different.

[0063] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" represent examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0064] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0065] Figure 4 4 is a schematic block diagram of an OPC-based STA timing analysis and optimization device 400 provided in an embodiment of the present application. Figure 4 As shown, the device includes a data acquisition module 401 , a path optimization module 402 and a STA analysis module 403 .

[0066] Data acquisition module 401: used to acquire a first layout.

[0067] Path optimization module 402: used to perform a first STA timing analysis operation on the first layout to generate a critical path when the first layout meets a first preset standard; based on the critical path, perform an OPC correction operation on the first layout to generate a second layout; and perform an OPC fitting operation on the second layout to generate a third layout.

[0068] STA analysis module 403: configured to perform the second STA timing analysis operation on the third layout to generate a STA analysis result.

[0069] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0070] It should also be understood that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0071] Figure 5 This is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 5 As shown, the electronic terminal includes: at least one processor 501, a memory 502, at least one network interface 503 and a user interface 505. The various components in the device are coupled together via a bus system 504. It is understood that the bus system 504 is used to achieve connection and communication between these components. In addition to including a data bus, the bus system 504 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 5 Various buses are labeled as bus systems.

[0072] The user interface 505 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0073] It will be appreciated that the memory 502 may be a volatile memory or a non-volatile memory, and may also include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present application is intended to include, but is not limited to, these and any other suitable categories of memories.

[0074] The memory 502 in the embodiment of the present application is used to store various categories of data to support the operation of the electronic terminal 500. Examples of these data include: any executable program for operating on the electronic terminal 500, such as an operating system 5021 and an application 5022; the operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 5022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The OPC-based STA timing analysis optimization method provided in the embodiment of the present application can be included in the application 5022.

[0075] The method disclosed in the above-mentioned embodiment of the present application can be applied to the processor 501 or implemented by the processor 501. The processor 501 may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above-mentioned method can be completed by the integrated logic circuit of the hardware in the processor 501 or by instructions in the form of software. The above-mentioned processor 501 can be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 501 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor 501 can be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in conjunction with the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above-mentioned method in combination with its hardware.

[0076] In an exemplary embodiment, the electronic terminal 500 may be configured to execute the aforementioned method using one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0077] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute the OPC-based STA timing analysis optimization method of any of the embodiments shown above.

[0078] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores program code. When the program code runs on a computer, the computer executes the OPC-based STA timing analysis optimization method of any embodiment shown in the above embodiments.

[0079] As used in this specification, the terms "component," "module," "system," and the like are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a single computer and / or distributed across two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0080] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0083] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0084] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0085] In the above embodiments, the functions of each functional unit can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When these computer program instructions (programs) are loaded and executed on a computer, they fully or partially produce the processes or functions according to the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0086] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the existing technology, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0087] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0088] In summary, the present application provides an OPC-based STA timing analysis optimization method, device, medium, program product and terminal, which obtains layout data before extracting parasitic parameters, performs a first STA timing analysis, quickly locates the critical path, and then performs optical proximity effect correction and fitting on the critical path to generate a layout that highly fits the actual manufacturing state. A comprehensive and detailed evaluation of the corrected path is achieved through a second STA timing analysis to ensure accurate verification and optimization of timing convergence. It solves the problem that traditional timing verification is too conservative and lacks accuracy, resulting in waste of design resources, inaccurate timing verification and difficult to control chip timing risks. It significantly improves the accuracy and efficiency of timing verification, reduces redundant calculations and resource consumption in non-critical areas, is suitable for advanced process chip design, and achieves efficient and reliable timing convergence in a manufacturing deviation environment, ensuring chip performance and production yield. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0089] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A STA timing analysis optimization method based on OPC, characterized in that: include: Get the first version; When the first layout meets a first preset standard, performing a first STA timing analysis operation on the first layout to generate a critical path; Based on the critical path, performing an OPC correction operation on the first layout to generate a second layout; performing an OPC fitting operation on the second layout to generate a third layout; The second STA timing analysis operation is performed on the third layout to generate an STA analysis result.

2. The OPC-based STA timing analysis and optimization method according to claim 1, characterized in that: The first preset standard includes: If the advanced process node in the first layout is greater than a preset threshold, then the first layout does not meet the first preset standard; If the advanced process node in the first layout is less than or equal to a preset threshold, then the first layout meets the first preset standard.

3. The OPC-based STA timing analysis and optimization method according to claim 1, characterized in that: The process of performing a first STA timing analysis operation on the first layout to generate a critical path includes: Extracting corresponding circuit description data from the first layout; Constructing a timing network model according to the circuit description data; In the timing network model, the signal arrival time from the input port to each node is calculated to generate arrival time data; Calculate the timing margin corresponding to each node using the arrival time data and preset timing constraints; Based on the time margin, a path meeting a preset condition is identified and extracted as a critical path.

4. The OPC-based STA timing analysis and optimization method according to claim 3, characterized in that: The process of identifying and extracting paths that meet preset conditions as critical paths includes: Identify and extract the paths with timing violations as critical paths; and / or, identifying and extracting paths that fail to converge as critical paths.

5. The OPC-based STA timing analysis and optimization method according to claim 1, characterized in that: The process of performing an OPC correction operation on the first layout based on the critical path to generate a second layout includes: Get and load OPC model file; In the first layout, performing a simulated exposure calculation for a corresponding area of ​​the critical path to generate light intensity distribution data; The edge offset of the area corresponding to the critical path is calculated according to the light intensity distribution data, and the offset correction is performed on the area corresponding to the critical path in the first layout to generate a second layout.

6. The OPC-based STA timing analysis and optimization method according to claim 5, characterized in that: The process of performing the OPC fitting operation on the second layout to generate the third layout includes: Based on the process sub-model in the OPC model file, manufacturing process simulation and fitting calculation are performed on the second layout to generate a third layout representing the actual process deformation.

7. An OPC-based STA timing analysis and optimization device, characterized in that: include: Data acquisition module: used to obtain the first layout; A path optimization module: configured to perform a first STA timing analysis operation on the first layout to generate a critical path when the first layout meets a first preset standard; Based on the critical path, performing an OPC correction operation on the first layout to generate a second layout; performing an OPC fitting operation on the second layout to generate a third layout; STA analysis module: used to perform the second STA timing analysis operation on the third layout to generate STA analysis results.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the OPC-based STA timing analysis and optimization method according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program code, and when the computer program code is run on a computer, the computer is enabled to implement the OPC-based STA timing analysis and optimization method according to any one of claims 1 to 6.

10. An electronic terminal comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the OPC-based STA timing analysis and optimization method according to any one of claims 1 to 6.

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