SiC layer etching method and semiconductor process equipment

Abstract

The invention discloses a SiC layer etching method and semiconductor process equipment, and belongs to the technical field of semiconductors. The SiC layer etching method comprises the following steps: forming a mask layer with a predetermined pattern on the surface of a SiC layer; the mask layer is used as a mask, first etching gas is used for etching the SiC layer so as to form a groove with a fillet at the bottom in the SiC layer, and the first etching gas comprises Si element and halogen element; wherein the halogen elements comprise at least two different elements, and the ratio of the Si element to the halogen elements ranges from 1: 5 to 1: 30. The semiconductor process equipment comprises a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, the controller comprises at least one processor and at least one memory, a computer program is stored in the memory, and the SiC layer etching method is realized when the computer program is executed by the processor.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a SiC layer etching method and semiconductor process equipment. Background Art

[0002] Semiconductor etching is not only a method of semiconductor surface processing, but also a very important graphic method in the semiconductor device preparation process.

[0003] As a third-generation semiconductor material, SiC has excellent performance in breakdown field strength, thermal conductivity, saturated electron rate, etc., and is mainly used to make semiconductor field-effect transistors and other devices.

[0004] In the prior art, in the etching process of SiC materials, chlorine and oxide are usually used to etch the SiC substrate. However, the smoothness of the grooves formed in the substrate after etching is poor. That is, the sidewalls and bottom walls of the grooves are both relatively straight structures, and the sidewalls and the bottom wall tend to be perpendicular to each other, making the connection between the sidewalls and the bottom wall relatively sharp. Therefore, the electric field is enhanced by the focusing effect at the connection between the sidewalls and the bottom wall, which easily leads to electric field concentration, thereby affecting the performance of the device. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a SiC layer etching method and semiconductor process equipment, which can solve the problem of easy electric field concentration in the grooves formed in the SiC layer in the related art.

[0006] In a first aspect, an embodiment of the present application provides a SiC layer etching method, comprising:

[0007] forming a mask layer having a predetermined pattern on a surface of the SiC layer;

[0008] Using the mask layer as a mask, etching the SiC layer with a first etching gas to form a groove with a rounded bottom in the SiC layer, wherein the first etching gas includes Si and a halogen element;

[0009] The halogen elements include at least two different elements, and the ratio of the Si element to the halogen elements is within a range of 1:5 to 1:30.

[0010] In a second aspect, an embodiment of the present application further provides a semiconductor process equipment, comprising a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that the controller comprises at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned SiC layer etching method is implemented.

[0011] In an embodiment of the present application, the SiC layer is etched using a first etching gas. Since the first etching gas includes Si elements and halogen elements, the Si elements dissociated from the first etching gas accumulate on the bottom wall of the trench, and the accumulation phenomenon is more obvious at the connection between the bottom wall and the side wall. The accumulated Si elements will hinder the etching process, so the etching rate at the bottom wall of the trench and the connection between the bottom wall and the side wall is lower than the etching rate at other positions, and the Si element accumulation phenomenon is more obvious at the connection between the bottom wall and the side wall, which will cause a difference in etching rate between the center of the bottom wall of the trench and the connection, resulting in a slower etching rate at the connection between the bottom wall and the side wall, so that the structure formed at the connection is relatively smooth, so that the bottom wall of the trench has a certain degree of roundness, that is, the bottom of the trench has a rounded corner, then the side wall and the bottom wall of the trench are not perpendicular, and the connection between the two will not be too sharp, effectively avoiding the problem of electric field concentration, which is beneficial to improving the performance of devices made of the SiC layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a flow chart of a SiC layer etching method disclosed in one embodiment of the present application;

[0013] Figure 2 is a flow chart of a SiC layer etching method disclosed in another embodiment of the present application;

[0014] Figure 3 is a flow chart of the SiC layer etching process disclosed in the embodiment of the present application;

[0015] Figure 4 This is an etching effect diagram of the SiC layer disclosed in the embodiment of the present application;

[0016] Figure 5 This is a scanning electron microscope image of the SiC layer after etching disclosed in the embodiment of the present application;

[0017] Figure 6 It is a structural schematic diagram of the semiconductor process equipment disclosed in the embodiment of this application.

[0018] Description of reference numerals:

[0019] 100-SiC layer, 110-trench, 111-sidewall, 112-bottom wall,

[0020] 200-mask layer, 210-opening,

[0021] 300-photoresist layer,

[0022] 400-Semiconductor process equipment,

[0023] 40-process chamber,

[0024] 40A-Intake assembly,

[0025] 40B-upper electrode assembly, 41-RF coil, 43-upper RF power supply, 45-upper matching device,

[0026] 40C-lower electrode assembly, 42-wafer carrier, 44-lower RF power supply, 46-lower matching device,

[0027] 40D-exhaust assembly,

[0028] 500-Plasma. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0030] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0031] In a first prior art technique, SiN is deposited on the surface of a SiC layer. Using the SiN as a mask, the SiC layer is etched using SF6 and O2 to form a groove on the surface of the SiC layer. However, the sidewalls and bottom walls of the resulting grooves are at right angles, meaning the junction between the sidewalls and bottom walls is relatively sharp. This makes it prone to electric field concentration at the junction, which in turn affects device performance.

[0032] In the second prior art, SiO2 is grown on an epitaxial wafer of a SiC layer as a mask layer, and a mixed gas of SF6 or CF4 and O2 is used to etch the SiC layer for a period of time to form grooves on the surface of the SiC layer. The SiC layer is then placed in a process tube and Cl2 and an oxidizing gas are introduced for annealing. A combination of dry etching and oxidation etching is used in the preparation process. However, the use of oxidation etching makes it easy to produce micromasks and damaged layers in the process of forming the grooves, resulting in a relatively rough etching effect. An additional process is required to remove the micromasks, which increases the preparation cost of the device.

[0033] Based on this, an embodiment of the present application discloses a SiC layer etching method to solve the above-mentioned problems of electric field concentration and the need to additionally remove the micromask.

[0034] The SiC layer etching method and semiconductor process equipment provided in the embodiments of the present application are described in detail below with reference to specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0035] Please refer to Figure 1-Figure 5 , the SiC layer etching method disclosed in the embodiment of the present application includes:

[0036] S100, forming a mask layer 200 with a predetermined pattern on the surface of the SiC layer 100, referring to Figure 3 Optionally, a mask layer 200 may be provided on the substrate layer of the SiC layer 100 , or a mask layer 200 may be provided on the intermediate layer of the SiC layer 100 .

[0037] Optionally, a mask layer 200 is deposited on the surface of the SiC layer 100 using chemical vapor deposition equipment. The mask layer 200 can be SiO2 or SiN. The mask layer 200 is used as a protective layer for subsequent etching of the groove 110 to protect the SiC layer 100 that does not need to be etched, preventing this part from being etched by the first etching gas.

[0038] Among them, the thickness of the mask layer 200 is greater than 0.8μm. For the conventional SiC etching process of etching 1μm-3μm, the selectivity ratio of SiO2 to SiC is between 2-5, so correspondingly, 0.2μm-2μm of SiO2 needs to be consumed during the etching process, so the thickness range of SiO2 is selected to be 1μm-3μm.

[0039] S200, using the mask layer 200 as a mask, etching the SiC layer 100 with a first etching gas to form a groove 110 with a rounded bottom in the SiC layer 100, the first etching gas includes Si element and halogen element, Figure 3 Step (e). The halogen elements include at least two different elements, and the ratio of Si to the halogen elements is within a range of 1:5 to 1:30. Thus, the ratio of Si to the halogen elements is appropriate, which is beneficial for improving the etching effect of the first etching gas.

[0040] Optionally, the etching gas including the Si element may be a gaseous hydride of Si, or may be other etching gases including the Si element.

[0041] The Si elements dissociated from the first etching gas accumulate on the bottom wall 112 of the groove 110, and the accumulation phenomenon is more obvious at the connection between the bottom wall 112 and the side wall 111. The accumulated Si elements will hinder the etching process, so the etching rate at the bottom wall 112 of the groove 110 and the connection between the bottom wall 112 and the side wall 111 is lower than the etching rate at other positions, and the Si element accumulation phenomenon is more obvious at the connection between the bottom wall 112 and the side wall 111, which will cause a difference in etching rate between the center and the connection of the bottom wall 112 of the groove 110, resulting in a slower etching rate at the connection between the bottom wall 112 and the side wall 111, so that the structure formed at the connection is relatively smooth, and finally a groove 110 with rounded corners is formed at the bottom.

[0042] Optionally, the halogen element can be F element, Cl element or Br element, or other elements, so the first etching gas can be an etching gas containing F element, an etching gas containing Cl element or an etching gas containing Br element, or an etching gas containing other halogen elements, which is mainly used for chemical etching.

[0043] In this embodiment, the SiC layer 100 is etched using the first etching gas. Since the first etching gas includes Si and halogen elements, when the groove 110 is formed in the SiC layer 100, the bottom wall 112 of the groove 110 is etched to a greater extent, so that the bottom wall 112 of the groove 110 has a certain degree of roundness, rather than a straight structure. Therefore, the side wall 111 of the groove 110 is not perpendicular to the bottom wall 112, and the connection between the two is not too sharp. Figure 4 and Figure 5 The trench 110 shown in the effect diagram effectively avoids the problem of electric field concentration, which is beneficial to improving the performance of SiC devices.

[0044] Moreover, there is no oxidizing gas involved in the etching in the first etching gas, that is, there is no need to use oxidation etching. Micromasks and damaged layers are not easily generated during the formation of the groove 110, and no additional process is required to remove the micromasks, which is beneficial to reducing the preparation cost of the device.

[0045] In an optional embodiment, the halogen elements include F and Cl. The F element is used to etch the SiC layer 100 and reduce deposition on the top of the trench 110. The Cl element is used to etch the SiC layer 100, increase the etching selectivity between the SiC layer 100 and the mask layer 200, and make the bottom of the trench 110 have a rounded corner. That is, the etching rate of the SiC layer 100 is faster than the etching rate of the mask layer 200, which is beneficial to the formation of the trench 110 in the SiC layer 100. Optionally, the first etching gas includes a gas capable of generating a high F radical and a high Cl radical. Further optionally, the gas capable of generating a high F radical may be NF3, CF4, CHF3, etc., and the gas capable of generating a high Cl radical may be Cl2, CCl4, etc.

[0046] In this embodiment, the first etching gas containing the F element is conducive to increasing the etching rate, reducing top deposition, and improving the process effect; the first etching gas containing the Cl element is conducive to increasing the etching rate and selectivity, making the connection between the side wall 111 and the bottom wall 112 of the groove 110 smoother, further avoiding the electric field concentration problem, and improving the process effect.

[0047] In an optional embodiment, the first etching gas includes SiCl 4 and SF 6 , both of which mainly play a role in chemical etching, and the flow ratio of SiCl 4 to SF 6 is within the range of 1:4 to 4:1.

[0048] During the etching process, SiCl4 dissociates, generating Si and Cl. The Si element primarily accumulates at the junction between the bottom wall 112 and the sidewall 111, hindering the etching rate at the junction. Furthermore, compared to Cl2, SiCl4 produces a higher concentration of Cl radicals, which further increases the etching rate and selectivity, making the junction more rounded and further avoiding the problem of electric field concentration. Compared to gases such as NF3 and CF4, SF6 produces a higher concentration of fluorine radicals, which further increases the etching rate and reduces top deposition. Furthermore, the flow ratio of SiCl4 and SF6 meets the aforementioned conditions, and the SiCl4 and SF6 ratio is relatively appropriate, which facilitates the first etching gas to form a trench 110 with vertical sidewalls 111 and a relatively smooth bottom wall 112.

[0049] In an optional embodiment, the flow rate of SiCl4 is in the range of 5 sccm-20 sccm, and the flow rate of SF6 is in the range of 5 sccm-20 sccm, so as to vertically form the sidewalls 111 of the trench 110. The flow rates of SiCl4 and SF6 are within the above ranges, so that the flow rates of the different gases of the first etching gas are relatively appropriate, and the combination of the different gases is relatively appropriate, which is conducive to the first etching gas forming the trench 110 with vertical sidewalls 111 and a relatively smooth bottom wall 112.

[0050] Of course, in other embodiments, the flow rates of SiCl 4 and SF 6 may also be selected to be outside the above flow rate ranges.

[0051] In an optional embodiment, mask layer 200 is a SiO2 layer. The Si element is used to increase the etching selectivity between SiC layer 100 and mask layer 200. In other words, SiC layer 100 etches faster, while mask layer 200 etches slower. In this embodiment, mask layer 200 etches slower, which helps to better serve as a mask and also facilitates the first etching gas to accurately etch trench 110 in SiC layer 100.

[0052] Of course, in other embodiments, the mask layer 200 may also be made of materials other than SiO 2 that can function as a mask.

[0053] In an optional embodiment, the first etching gas includes Ar, which primarily performs physical etching. The Ar flow rate range is 200 sccm-500 sccm, and the Ar flow rate is related to the aperture ratio of the mask layer 200. In other words, the Ar flow rate range can be adjusted based on the aperture ratio of the mask layer 200. The aperture ratio of the mask layer 200 indicates the degree of exposure of the SiC layer 100. A higher aperture ratio of the mask layer 200 indicates a larger area of ​​the SiC layer 100 to be etched, and a larger Ar flow rate is required. A lower aperture ratio of the mask layer 200 indicates a smaller area of ​​the SiC layer 100 to be etched, and a smaller Ar flow rate is required.

[0054] Thus, adding Ar as the first etching gas can destroy Si-C bonds, enhance physical etching and help clean up byproducts.

[0055] Of course, in other embodiments, the first etching gas may also be other gases other than Ar for physical etching, and can be used together with a gas including Si and halogen elements as the first etching gas to etch and form the groove 110 with rounded bottom corners.

[0056] In an optional embodiment, the etching conditions of the first etching gas include: an upper electrode RF power range of 1200W-2000W, and a lower electrode RF power range of 400W-600W, so that the sidewalls 111 of the trench 110 are vertical and the bottom has rounded corners. The upper electrode RF power determines the concentration of the plasma during the etching process, and the lower electrode RF power determines the energy of the plasma bombardment. Using the upper electrode RF power and the lower electrode RF power within the above ranges ensures that the plasma concentration and energy are appropriate during the etching process.

[0057] Of course, in other embodiments, the first etching gas may also etch the SiC layer 100 under other etching conditions.

[0058] In an optional embodiment, the etching conditions of the first etching gas also include: an etching pressure range of 40mT-90mT, an etching temperature range of 10℃-40℃, and the etching pressure and etching temperature are both related to the aperture ratio of the mask layer 200, that is, the etching pressure and etching temperature can be adjusted according to the aperture ratio of the mask layer 200.

[0059] The etching pressure and etching temperature determine the etching environment. Using the etching pressure and etching temperature within the above range is conducive to obtaining a groove 110 with rounded corners at the bottom during the etching process, that is, obtaining a groove 110 with a smooth transition connection between the bottom wall 112 and the side wall 111, effectively avoiding the problem of electric field concentration, and is conducive to improving the performance of SiC devices.

[0060] In summary, the SiC layer 100 is placed in the etching chamber of the etcher, and the RF power of the upper electrode of the etcher is set in the range of 1200W-2000W, and the RF power of the lower electrode is set in the range of 400W-600W, then an electron area is formed in the etching chamber, and an electric field is formed in the etching chamber. At the same time, the etching temperature is set in the range of 10℃-40℃, and under the etching pressure of 40mT-90mT, 5sccm-20sccm of SiCl4, 5sccm-20sccm of SF6 and 200sccm-500sccm of Ar are introduced into the etching chamber of the etcher, and the introduction is continued for a period of time. When the first etching gas enters the etching chamber, it is exposed to the electron area to form a plasma. The ionized gas and the gas composed of released functional electrons thus generated form plasma or ions. When the ionized gas atoms are accelerated by the electric field to contact the SiC layer 100, they will release the energy to etch the part of the SiC layer 100 corresponding to the opening 210, thereby forming a groove 110.

[0061] In the solution of the present application, a mask layer 200 with a predetermined pattern is formed on the surface of the SiC layer 100, including:

[0062] S120. Etch the mask layer 200 using a second etching gas so that the mask layer 200 forms a predetermined pattern, that is, the SiC layer 100 has a certain aperture ratio. The mask layer 200 is a SiO2 layer, and the second etching gas includes a fluorocarbon gas, O2, and Ar. Adding O2 to the fluorocarbon gas is beneficial to increasing the concentration of etching free radicals F, thereby increasing the atomic ratio of fluorine to carbon and accelerating the etching rate; while Ar mainly plays a physical etching role, which is beneficial to strengthening physical etching and helping to clean up by-products. Using this embodiment, the etching process is used to accurately set a pattern with a relatively fine shape on the mask layer 200, so that the aperture ratio of the mask layer 200 is within a preset range, and the etching accuracy and consistency are high.

[0063] Optionally, forming a mask layer 200 with a predetermined pattern on the surface of the SiC layer 100 further includes:

[0064] S110: Before etching, a mask layer 200 is first provided on the surface of the SiC layer 100. It should be noted that the mask layer 200 at this time is a mask layer 200 without an opening.

[0065] In a further alternative embodiment, reference Figure 2 and Figure 3 As shown, etching the mask layer 200 using the second etching gas specifically includes:

[0066] S121, coating a photoresist layer 300 on the side of the mask layer 200 facing away from the SiC layer 100, and forming a photoresist pattern on the photoresist layer 300, referring to Figure 3 step (b).

[0067] Specifically, a photoresist layer 300 is applied to the surface of the mask layer 200 facing away from the SiC layer 100, and a photolithographic pattern is formed through photolithography and development. Optionally, the aperture ratio of the photolithographic pattern ranges from 10% to 50%. The aperture ratio determines the size of the exposed area of ​​the mask layer 200. Typically, SiC devices require aperture ratios of 10%, 30%, and 50%. Devices formed under lower aperture ratios have a higher yield but lower production capacity, while devices formed under higher aperture ratios have a lower yield. Therefore, an appropriate aperture ratio can be selected for the photolithographic pattern based on different etching recipes.

[0068] S122, using the photoresist layer 300 as a mask, etching the mask layer 200 with a second etching gas to form a predetermined pattern in the mask layer 200, that is, forming an opening 210 in the mask layer 200, referring to Figure 3 In step (c), the aperture ratio of the mask layer 200 is consistent with the aperture ratio of the photolithographic pattern. In this step, the selection of the second etching gas and the etching conditions are not specifically limited. This is a conventional etching process that can form the opening 210 in the mask layer 200.

[0069] In this way, the photoresist layer 300 serves as a protective layer during the preparation of the mask layer 200 , preventing the photoresist pattern from being transferred to the mask layer 200 , and etching the portion of the mask layer 200 that does not need to be etched, thereby avoiding process failure.

[0070] In an optional embodiment, the etching conditions of the second etching gas include: etching pressure range of 50mT-80mT, etching temperature range of 10°C-40°C, RF power range of the upper electrode of 200W-400W, and RF power range of the lower electrode of 400W-800W.

[0071] The second etching gas adopts the above etching conditions, which can obtain appropriate plasma concentration and energy during the etching process, and is conducive to smoothly etching the mask layer 200 to form the opening 210.

[0072] In an optional embodiment, the fluorocarbon gas includes CF4 and C4F8. Optionally, the flow rate of CF4 is in the range of 5 sccm-10 sccm, the flow rate of C4F8 is in the range of 10 sccm-20 sccm, the flow rate of O2 is in the range of 10 sccm-30 sccm, and the flow rate of Ar is in the range of 300 sccm-500 sccm.

[0073] The flow rates of various gases of the second etching gas are within the above ranges. The flow rates of different gases of the second etching gas are relatively appropriate, and the matching of different gases is relatively appropriate, which is conducive to the second etching gas etching the mask layer 200 to form the opening 210.

[0074] In an optional embodiment, the SiC layer etching method further includes:

[0075] S123, after forming a predetermined pattern on the mask layer 200, the mask layer 200 is stripped. Figure 2 shown.

[0076] After the mask layer 200 is etched to form the opening 210 with the photoresist layer 300 as a protective layer, the photoresist layer 300 is removed to expose the mask layer 200 , so that the trench 110 can be etched into the SiC layer 100 using the first etching gas with the mask layer 200 as a mask.

[0077] In a further embodiment, the mask layer 200 is stripped, specifically comprising:

[0078] The mask layer 200 is subjected to dry stripping and wet stripping using O 2 .

[0079] Specifically, dry stripping, also known as plasma stripping, mainly removes the photoresist layer 300 by reacting oxygen atoms and photoresist in a plasma environment. Since the basic components of the photoresist layer 300 are hydrocarbon organics, under the action of radio frequency or microwaves, oxygen is ionized to form oxygen atoms and chemically reacts with the photoresist to produce carbon monoxide, carbon dioxide and water, thereby removing the photoresist layer 300; wet stripping uses wet chemical reactions to dissolve or decompose the glue, thereby achieving the purpose of removing the photoresist layer 300.

[0080] The combination of dry stripping and wet stripping cleaning is beneficial for quickly removing the photoresist layer 300 , shortening the interval between etching with the first etching gas and etching with the second etching gas, and improving the efficiency of the SiC etching process.

[0081] Of course, in other embodiments, the mask layer 200 may also be removed using only a dry stripping method or only a wet stripping method.

[0082] In summary, the SiC layer etching method of the present application specifically includes:

[0083] A layer of SiO2 is deposited on the surface of the SiC layer 100 as a mask layer 200, and then a photoresist layer 300 is coated on the side of the mask layer 200 facing away from the SiC layer 100, and a photoresist layer 300 is formed into a photolithographic pattern. The SiC layer 100 is further placed in an etcher, and the radio frequency power of the upper electrode of the etcher is set to 200W-400W, the radio frequency power range of the lower electrode is set to 400W-800W, the etching temperature range is 10°C-40°C, and under an etching pressure of 50mT-80mT, 5sccm-10sccm of CF4, 10sccm-20sccm of C4F8, 10sccm-30sccm of O2, and 300sccm-500sccm of Ar are introduced into the etching chamber of the etcher, so that these four gases act on the mask layer 200. Etching is performed to form a predetermined pattern on the mask layer 200; then the photoresist layer 300 is removed, and the SiC layer 100 is placed in the etcher again. The RF power of the upper electrode of the etcher is set in the range of 1200W-2000W, the RF power of the lower electrode is set in the range of 400W-600W, the etching temperature is set in the range of 10°C-40°C, and under an etching pressure of 40mT-90mT, 5sccm-20sccm of SiCl4, 5sccm-20sccm of SF6 and 200sccm-500sccm of Ar are introduced into the etching chamber of the etcher, so that these three gases etch the SiC layer 100 to form a groove 110 with vertical sidewalls 111 and smooth bottom wall 112 in the SiC layer 100, that is, a groove 110 with rounded bottom.

[0084] Based on the SiC layer etching method disclosed in the present application, the present application embodiment further provides a semiconductor process equipment 400, which can be the etching machine mentioned above, such as Figure 6 As shown, the semiconductor process equipment 400 may include a process chamber 40, an inlet assembly 40A, an upper electrode assembly 40B and a lower electrode assembly 40C, a pumping assembly 40D and a controller ( Figure 6 (not shown). The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0085] For example, the controller can be a host computer or a slave computer. Specifically, the controller can control the opening of the valve of the gas inlet assembly 40A to introduce the corresponding process gas into the process chamber 40. The controller can also control the opening and closing of the valve of the gas inlet assembly 40A to control the flow rate of the process gas. The controller can also control the exhaust assembly 40D to exhaust the interior of the process chamber 40, for example, by controlling the valve opening of the exhaust assembly 40D or the speed of the exhaust pump, thereby controlling the pressure inside the process chamber 40 and exhausting reaction byproducts.

[0086] The upper electrode assembly 40B may include an RF coil 41, an upper RF power supply 43, and an upper matcher 45. The controller is further configured to control the upper RF power supply 43 to provide RF power to the RF coil 41 via the upper matcher 45, so that the RF coil 41 excites the process gas inside the process chamber 40 to generate plasma 500.

[0087] The lower electrode assembly 40C may include a wafer carrier 42, a lower RF power supply 44, and a lower matcher 46. The controller is further configured to control the lower RF power supply 44 to provide RF power to the wafer carrier 42 via the lower matcher 46 to provide an RF bias. The wafer carrier 42 may be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum chuck.

[0088] The semiconductor process equipment 400 of the embodiment of the present application may be an inductively coupled plasma (ICP) device or a capacitively coupled plasma (CCP) device. The embodiment of the present application does not limit the type of the semiconductor process equipment 400.

[0089] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A SiC layer etching method, characterized in that: include: forming a mask layer (200) with a predetermined pattern on the surface of the SiC layer (100); Using the mask layer (200) as a mask, etching the SiC layer (100) with a first etching gas to form a groove (110) with a rounded bottom in the SiC layer (100), wherein the first etching gas includes Si element and a halogen element; The halogen elements include at least two different elements, and the ratio of the Si element to the halogen elements is within a range of 1:5 to 1:

30.

2. The SiC layer etching method according to claim 1, wherein: The halogen elements include F and Cl. The F element is used to etch the SiC layer (100) and reduce deposition on the top of the trench (110). The Cl element is used to etch the SiC layer (100), increase the etching selectivity between the SiC layer (100) and the mask layer (200), and make the bottom of the trench (110) have a rounded corner.

3. The SiC layer etching method according to claim 2, characterized in that: The first etching gas includes SiCl 4 and SF 6 , and a flow ratio of the SiCl 4 to the SF 6 is within a range of 1:4 to 4:

1.

4. The SiC layer etching method according to claim 3, characterized in that: The flow rate of the SiCl4 is in the range of 5 sccm-20 sccm, and the flow rate of the SF6 is in the range of 5 sccm-20 sccm, so as to make the sidewall (111) of the groove (110) vertical.

5. The SiC layer etching method according to claim 1, wherein: The mask layer (200) is a SiO2 layer, and the Si element is used to increase the etching selectivity ratio between the SiC layer (100) and the mask layer (200).

6. The SiC layer etching method according to claim 1, characterized in that: The first etching gas also includes Ar, the flow rate of the Ar is in the range of 200 sccm-500 sccm, and the flow rate of the Ar is related to the aperture ratio of the mask layer (200).

7. The SiC layer etching method according to any one of claims 1 to 6, characterized in that: The etching conditions of the first etching gas include: The radio frequency power of the upper electrode is in the range of 1200W-2000W, and the radio frequency power of the lower electrode is in the range of 400W-600W, so that the sidewall (111) of the groove (110) is vertical and the bottom has a rounded corner.

8. The SiC layer etching method according to claim 7, characterized in that: The etching conditions of the first etching gas also include: The etching pressure ranges from 40mT to 90mT, and the etching temperature ranges from 10°C to 40°C. Both the etching pressure and the etching temperature are related to the aperture ratio of the mask layer (200).

9. The SiC layer etching method according to claim 1, characterized in that: The mask layer (200) for forming a predetermined pattern on the surface of the SiC layer (100) comprises: Etching the mask layer (200) using a second etching gas so that the mask layer (200) forms the predetermined pattern; The mask layer (200) is a SiO2 layer, and the second etching gas includes a carbon-fluorine gas, O2 and Ar.

10. A semiconductor process equipment, characterized in that: The invention comprises a process chamber (40), an air inlet assembly (40A), an upper electrode assembly (40B), a lower electrode assembly (40C) and a controller, wherein the controller comprises at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the SiC layer etching method according to any one of claims 1 to 9 is implemented.

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