Packaging method and packaging structure

Abstract

The invention relates to a packaging method and a packaging structure, and the packaging method comprises the steps: providing a hybrid substrate, the hybrid substrate comprises a packaging substrate and a rewiring interposer, the rewiring interposer comprises a first bonding pad and a second bonding pad, the second bonding pad and the first bonding pad are located at the two ends of the rewiring interposer respectively, and the packaging substrate is welded with the second bonding pad; bonding a chip to one side, far away from the packaging substrate, of the redistribution interposer through the first bonding pad; and forming a plastic package layer covering the chip. In the application, the chip side packaging can be used as the final process of packaging, so that the problem of chip waste caused by poor subsequent processes in the traditional technology can be effectively avoided.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a packaging method and a packaging structure. Background Art

[0002] In existing packaging technology, a redistribution layer is typically formed on a first temporary substrate. This layer is then bonded to the chip, and a plastic encapsulation layer is formed to cover the chip. A second temporary substrate is then formed on the plastic encapsulation layer. The first temporary substrate is then removed, using the second temporary substrate as support. The redistribution layer, removed from the first temporary substrate, is then bonded to the packaging substrate.

[0003] This packaging method can lead to waste of known-good chips if a defect occurs in the back-end process. This problem is particularly prominent in high-value packaged products. Summary of the Invention

[0004] Based on this, it is necessary to provide a packaging method and packaging structure to address the problem in the prior art of wasting known good chips due to poor back-end processes.

[0005] A packaging method, comprising:

[0006] Providing a hybrid substrate, the hybrid substrate comprising a packaging substrate and a redistribution interposer, the redistribution interposer comprising a first pad and a second pad, the second pad and the first pad being located at two ends of the redistribution interposer, respectively, the packaging substrate being welded to the second pad;

[0007] Bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad;

[0008] A plastic packaging layer is formed to cover the chip.

[0009] In one embodiment, before bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad, the method includes:

[0010] The first pad is thinned.

[0011] In one embodiment, the first pad includes a seed layer and a functional layer, and thinning the first pad includes:

[0012] At least the seed layer of the first pad is removed.

[0013] In one embodiment, after thinning the first pad, the method further includes:

[0014] The thinned surface of the first pad is chemically treated to form the welding film.

[0015] In one embodiment, the chemical treatment includes electroless nickel palladium immersion gold surface treatment.

[0016] In one embodiment, the hybrid substrate further includes a temporary substrate, the redistribution interposer is formed on the temporary substrate, and the packaging substrate is located on a side of the redistribution layer away from the temporary substrate.

[0017] Before bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad, the method further includes:

[0018] The temporary substrate is removed to expose the first pad.

[0019] In one embodiment, the chip includes solder balls and / or copper pillars.

[0020] Bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad includes:

[0021] The chip is thermally pressed and bonded to the first pad via the solder balls and / or copper pillars.

[0022] In one embodiment, the redistribution interposer further includes a dielectric layer, and the first pad is located in the dielectric layer.

[0023] Bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad includes:

[0024] The hybrid substrate and the chip are hybrid-bonded via the dielectric layer and the first pad.

[0025] In one embodiment, the packaging substrate includes an ABF packaging substrate.

[0026] A packaging structure is prepared according to the above packaging method.

[0027] The aforementioned packaging method utilizes a hybrid substrate comprising a packaging substrate and a redistribution interposer. Therefore, after bonding the chips, there is no need for additional processes such as forming a second temporary substrate, removing the first temporary substrate, and bonding the packaging substrate. This means that chip-side packaging can be performed as the final step in the packaging process, effectively avoiding chip waste caused by defects in the latter stages of traditional techniques. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a flow chart of a packaging method provided in one embodiment;

[0030] Figure 2 is a schematic diagram of a cross-sectional structure of a hybrid substrate provided in one embodiment;

[0031] Figure 3 is a schematic cross-sectional structural diagram of a hybrid substrate provided in another embodiment;

[0032] Figure 4 is a schematic cross-sectional view of a packaging structure provided in one embodiment;

[0033] Figure 5 A schematic cross-sectional view of a packaging structure provided in another embodiment;

[0034] Figure 6 is a schematic cross-sectional structural diagram of a packaging structure provided in yet another embodiment;

[0035] Figure 7 Figures (a) to (d) are schematic diagrams of a bonding process for bonding a chip using a low-pressure thermal compression bonding method in one embodiment;

[0036] Figure 8 Figures (a) to (c) are schematic diagrams of a bonding process for bonding a chip using a high-pressure thermal compression bonding method in one embodiment;

[0037] Figure 9 Figures (a) to (c) are schematic diagrams of a bonding process for bonding a chip using a high-pressure thermal compression bonding method in another embodiment;

[0038] Figure 10 Figures (a) to (e) are schematic diagrams of a bonding process for bonding chips using liquid phase contact thermal compression bonding in one embodiment.

[0039] Description of reference numerals:

[0040] 100-hybrid substrate, 110-packaging substrate, 120-rewiring interposer, 121-first pad, 1211-seed layer, 1212-functional layer, 122-second pad, 123-dielectric layer, 130-first filling layer, 140-temporary substrate, 150-sacrificial layer, 200-chip, 210-solder ball, 220-copper pillar, 230-solder cap, 300-plastic layer, 400-solder film, 500-second filling layer, 5001-filling material, 600-flux, 10-needle head, 20-bonding head. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0043] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0044] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0045] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In one embodiment, see Figure 1 , provides a packaging method, comprising the following steps:

[0047] Step S10, see Figure 2 , providing a hybrid substrate 100, the hybrid substrate 100 includes a package substrate 110 and a redistribution interposer 120, the redistribution interposer 120 includes a first pad 121 and a second pad 122, the second pad 122 and the first pad 121 are respectively located at two ends of the redistribution interposer 120, and the package substrate 110 is welded to the second pad 122;

[0048] Step S30, see Figure 4 , bonding the chip 200 to a side of the redistribution interposer 120 away from the package substrate 110 through the first pad 121 ;

[0049] Step S40, see Figure 4 , forming a plastic encapsulation layer 300 covering the chip 200 .

[0050] In step S10, refer to Figure 2 The hybrid substrate 100 may be a finished product substrate. The package substrate 110 may include but is not limited to an ABF package substrate 110 .

[0051] The redistribution interposer 120 may include multiple routing layers. The line widths and / or line spacings of the multiple routing layers in the redistribution interposer 120 may gradually increase from a side away from the package substrate 110 to a side closer to the package substrate 110. Furthermore, the area of ​​the second pads 122 may be larger than that of the first pads 121.

[0052] For example, a first filling layer 130 may be provided between the redistribution interposer 120 and the package substrate 110 to fill the space therebetween.

[0053] In step S30, refer to Figure 4 , the chip 200 can be bonded to the first pad 121 , thereby bonding the chip 200 to the hybrid substrate 100 .

[0054] In step S40, refer to Figure 4 , a plastic encapsulation layer 300 may be formed by a plastic encapsulation process. The plastic encapsulation layer 300 covers and wraps the chip 200, thereby protecting the chip 200.

[0055] In this embodiment, a hybrid substrate 100 comprising a packaging substrate 110 and a redistribution interposer 120 is used for packaging. Therefore, after bonding the chip 200, no further processes such as forming a second temporary substrate, removing the first temporary substrate, and bonding the packaging substrate 110 are required. That is, chip 200 packaging can be performed as the final step in the packaging process, effectively avoiding chip 200 waste caused by defects in the back-end process in traditional technologies.

[0056] In one embodiment, before step S30, the method further includes:

[0057] Step S22 , thinning the first pad 121 .

[0058] The first pad 121 may be thinned by chemical mechanical polishing and / or etching (dry etching or wet etching).

[0059] Before bonding the chip 200 , during the storage and / or transportation of the hybrid substrate 100 , the surface of the first pad 121 may be oxidized or damaged, thereby affecting the soldering performance of the first pad 121 .

[0060] In this embodiment, before bonding the chip 200 , the first pad 121 is first thinned so as to remove the oxidized or damaged surface layer of the first pad 121 , thereby effectively improving the bonding performance of the first pad 121 .

[0061] In one embodiment, the first pad 121 includes a seed layer 1211 and a functional layer 1212 .

[0062] During the formation of the hybrid substrate 100 , the redistribution interposer 120 may be first formed on the temporary substrate 140 . Then, the redistribution interposer 120 may be formed on a side away from the temporary substrate 140 , and the second pads 122 of the redistribution interposer 120 may be bonded to the package substrate 110 .

[0063] When forming each wiring layer of the redistribution interposer 120, a seed material layer can first be sputtered using physical vapor deposition (PVD) technology. The seed material layer can include materials such as Ti / Cu. A photoresist can then be coated on the seed material layer and exposed using laser direct patterning (LDI) technology. The exposed photoresist is then developed to form a first patterned photoresist. The first patterned photoresist can have a first opening. Then, a metal (such as copper) can be deposited within the first opening of the first patterned photoresist using electrochemical deposition (ECD) to form a functional layer 1212. The first patterned photoresist is then stripped and removed, and the seed material layer is etched based on the functional layer 1212 to form a seed layer 1211. The seed layer 1211 and the functional layer 1212 form a wiring layer.

[0064] The first wiring layer formed on the temporary substrate 140 may include the first pads 121. The wiring layer may include only the first pads 121; or the wiring layer may include both the first pads 121 and the traces.

[0065] Based on this, the first pad 121 may include a seed layer 1211 and a functional layer 1212. Before bonding the chip 200, the temporary substrate 140 is removed, so that the seed layer 1211 is exposed.

[0066] Meanwhile, before bonding the chip 200 , thinning the first pad 121 (step S22 ) includes:

[0067] Step S221 , at least removing the seed layer 1211 of the first pad 121 .

[0068] Here, only the seed layer 1211 may be removed, or part of the functional layer 1212 may be thinned while the seed layer 1211 is removed.

[0069] At this time, see Figure 5 In subsequent steps, the chip 200 can be bonded to the functional layer 1212 of the remaining first pads 121 .

[0070] Removing the seed layer 1211 not only removes the oxidized or damaged surface layer of the first pad 121, but also exposes the functional layer 1212. Due to factors such as the manufacturing process, the surface treatment of the functional layer 1212 is usually more uniform, which can better absorb laser energy and facilitate the welding process. However, the seed layer 1211 may have surface unevenness or defects, which may affect the welding effect.

[0071] In one embodiment, after step S22, the method further includes:

[0072] In step S23 , chemical treatment is performed on the surface of the thinned first pad 121 to form a welding film 400 .

[0073] At this time, see Figure 6 In subsequent steps, the chip 200 can be bonded to the welding film 400.

[0074] When the thinned surface of the first pad 121 is chemically treated, a chemical reaction may occur on the surface of the first pad 121 , thereby forming the welding film 400 .

[0075] The welding film 400 may have better welding performance and reliability than the first pad 121 , thereby facilitating good bonding of the chip 200 to the first pad 121 in subsequent steps.

[0076] As an example, the thinned surface of the first pad 121 may be subjected to a surface treatment of electroless nickel-palladium immersion gold plating to form the soldering film 400 .

[0077] At this point, palladium can be replaced on the surface of the first pad 121 (such as copper) through a chemical reaction, and then a nickel-phosphorus alloy layer can be chemically plated on the basis of the palladium core. A palladium layer is then generated on the nickel layer through oxidation-reduction. Finally, a layer of gold is plated on the surface of the palladium through a replacement reaction (through the tiny gaps in the palladium layer to undergo a replacement reaction with the nickel layer), thereby completing the preparation of the welding film 400.

[0078] In one embodiment, see Figure 2 In addition to the package substrate 110 and the redistribution interposer 120, the hybrid substrate 100 also includes a temporary substrate 140. The redistribution interposer 120 is formed on the temporary substrate 140, and the package substrate 110 is located on a side of the redistribution interposer away from the temporary substrate 140.

[0079] Before step S30, the method further includes:

[0080] In step S21, the temporary substrate 140 is removed to expose the first pad 121.

[0081] At this time, before the hybrid substrate 100 is packaged, the temporary substrate 140 can cover the first pad 121 side of the redistribution interposer 120. Therefore, during the transportation and storage of the hybrid substrate 100 product, the temporary substrate 140 can protect the redistribution interposer 120 from damage such as external friction, thereby providing good protection for the product.

[0082] As an example, the hybrid substrate 100 may further include a sacrificial layer 150. The sacrificial layer 150 is located between the temporary substrate 140 and the redistribution interposer 120. Laser irradiation can be used to destroy the sacrificial layer 150, thereby removing the temporary substrate 140. Subsequently, a cleaning process or the like can be used to remove any remaining sacrificial layer 150 from the surface of the first pads 121.

[0083] Furthermore, after removing the temporary substrate 140, the first pad 121 may be thinned (step S22). While thinning the first pad 121 to remove the oxidized or damaged surface layer of the first pad 121, the sacrificial layer 150 residue on the first pad 121 may also be further removed.

[0084] Of course, in other embodiments, the configuration of the hybrid substrate 100 may be different. For example, the hybrid substrate 100 may only include the package substrate 110 and the redistribution interposer 120. In this case, before step S30, step S22 may still be included to thin the first pad 121 to remove the oxidized or damaged surface layer of the first pad 121.

[0085] In one embodiment, chip 200 includes solder balls 210 and / or copper pillars 220 .

[0086] Step S30 includes:

[0087] In step S31 a , the chip 200 is thermally pressed and bonded to the first pad 121 via the solder balls 210 and / or the copper pillars 220 .

[0088] When the chip 200 includes the copper pillar 220, the copper pillar 220 may have a solder cap 230. Thermocompression bonding may include low-pressure thermocompression bonding, high-pressure thermocompression bonding, or liquid-phase contact thermocompression bonding.

[0089] See also Figure 7In Figures (a) through (d), when using low-pressure thermocompression bonding to bond chip 200 to first pad 121 via solder ball 210 (or copper pillar 220), flux (not shown) can be applied to either solder ball 210 (or solder cap 230) or first pad 121. Alternatively, flux 600 can be applied to both solder ball 210 (or solder cap 230) and first pad 121. Then, chip 200 is picked up and placed onto first pad 121, and heat is applied to melt the solder. During this process, a slight pressure is applied to maintain a certain distance between chip 200 and hybrid substrate 100. Then, a filler material 5001 can be deposited between chip 200 and hybrid substrate 100 using a needle 10. Filler material 5001 then diffuses and solidifies, forming a second filler layer 500 that fills the space between chip 200 and hybrid substrate 100.

[0090] See also Figure 8 or Figure 9 In Figures (a) through (c), when high-pressure thermocompression bonding is used to thermocompressively bond chip 200 to first pad 121 via solder ball 210 (or solder cap 230), filler material 5001 can be spin-coated onto hybrid substrate 100 or chip 200 using dispensing with a needle 10 or vacuum coating. Chip 200 is then picked up and placed onto first pad 121, and heat is applied to melt the solder. During this process, high pressure is applied to bond chip 200 to hybrid substrate 100, and filler material 5001 fills the space between chip 200 and hybrid substrate 100, forming a second filler layer 500.

[0091] See also Figure 10 In Figures (a) through (e), when liquid phase contact thermocompression bonding is used to thermocompressively bond the chip 200 to the first pad 121 via the solder ball 210 (or solder cap 230), flux 600 can be printed or sprayed onto the hybrid substrate 100. The bond head 20 is then heated to a temperature below the melting point of the solder and removed from the carrier. The bond head 20 is then heated again to a temperature above the melting point of the solder. The chip 200 is then aligned with the first pad 121 of the hybrid substrate 100. After visual alignment, the chip 200 is brought into contact with the hybrid substrate 100 at preset bonding parameters and wetted. After a period of bonding, the bond head 20 is removed when the bonding temperature is reached or after the temperature has cooled below the melting point of the solder.

[0092] In one embodiment, see Figure 2 or Figure 3 The redistribution interposer 120 further includes a dielectric layer 123 , and the first pad 121 is located in the dielectric layer 123 .

[0093] During the formation of the redistribution interposer 120 , a plurality of wiring layers may be formed. The first pad 121 may be located in the wiring layer (ie, the first wiring layer) formed first on the temporary substrate 140 .

[0094] Before forming each subsequent wiring layer, an insulating dielectric material layer can be formed by slit coating or other methods. The insulating dielectric material layer can then be etched to form dielectric layer 123. Dielectric layer 123 has through-holes that expose at least a portion of the underlying wiring layer. A subsequent wiring layer can be electrically connected to a previously formed wiring layer via the through-holes in dielectric layer 123.

[0095] Therefore, the first pad 121 may be located in the dielectric layer 123 covering the first wiring layer.

[0096] Step S30 includes:

[0097] In step S31 b , hybrid bonding is performed on the hybrid substrate 100 and the chip 200 through the dielectric layer 123 and the first pad 121 .

[0098] The integration density of the chip 200 can be effectively improved through hybrid bonding.

[0099] For example, before hybrid bonding is performed, both the dielectric layer 123 and the first pad 121 may be thinned by etching or the like, thereby improving a reliable bonding surface for hybrid bonding.

[0100] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0101] In one embodiment, a packaging structure is further provided, which is prepared according to any of the above packaging methods.

[0102] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0103] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A packaging method, characterized in that: include: Providing a hybrid substrate, the hybrid substrate comprising a packaging substrate and a redistribution interposer, the redistribution interposer comprising a first pad and a second pad, the second pad and the first pad being located at two ends of the redistribution interposer, respectively, the packaging substrate being welded to the second pad; Bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad; A plastic packaging layer is formed to cover the chip.

2. The packaging method according to claim 1, wherein: Before bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad, the method includes: The first pad is thinned.

3. The packaging method according to claim 2, wherein: The first pad includes a seed layer and a functional layer, and thinning the first pad includes: At least the seed layer of the first pad is removed.

4. The packaging method according to claim 2, wherein: After thinning the first pad, the method further includes: The thinned surface of the first pad is chemically treated to form the welding film.

5. The packaging method according to claim 4, wherein: The chemical treatment includes chemical nickel-palladium immersion gold surface treatment.

6. The packaging method according to claim 1, wherein: The hybrid substrate further includes a temporary substrate, the redistribution interposer is formed on the temporary substrate, and the packaging substrate is located on a side of the redistribution layer away from the temporary substrate. Before bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad, the method further includes: The temporary substrate is removed to expose the first pad.

7. The packaging method according to claim 1, wherein: The chip includes solder balls and / or copper pillars, Bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad includes: The chip is thermally pressed and bonded to the first pad via the solder balls and / or copper pillars.

8. The packaging method according to claim 1, wherein: The redistribution interposer further includes a dielectric layer, wherein the first pad is located in the dielectric layer. Bonding the chip to a side of the redistribution interposer away from the package substrate through the first pad includes: The hybrid substrate and the chip are hybrid-bonded via the dielectric layer and the first pad.

9. The packaging method according to claim 1, wherein: The packaging substrate includes an ABF packaging substrate.

10. A packaging structure, characterized in that: Prepared by the packaging method according to any one of claims 1 to 9.

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