Electronic device

Abstract

An electronic device is provided. The electronic device includes: an electronic component; a conductive pad disposed on the electronic component and electrically connected to the electronic component; and a redistribution structure disposed on the conductive pad and including a plurality of conductive layers; a polymer layer surrounding the conductive layer; and a bump electrically connected to the conductive pad via the conductive layer. The center of the conductive pad is horizontally offset from the center of the bump. The conductive layer has a first conductive layer having a side surface, the side surface contacting the polymer layer and the side surface having a side edge, the side edge having a roughness of 0.08 [mu] m to 0.8 [mu] m in a cross-sectional view.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to a packaging technology for an electronic device. Background Art

[0002] Fan-out packaging, such as fan-out wafer level package (FOWLP) and fan-out panel level package (FOPLP), can increase the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) within a given area and has been widely used in the production and manufacturing of electronic devices in recent years.

[0003] However, fan-out packaging structures have many heterogeneous material interface integration structures (for example, the interface between the redistribution structure and the conductive pad). The heterogeneous material interfaces are often prone to delamination or peeling problems due to the presence of large stress.

[0004] Therefore, improving the reliability of the packaging structure of electronic devices is still one of the research topics that the industry is currently working on. Summary of the Invention

[0005] Some embodiments of the present disclosure provide an electronic device comprising: an electronic component; a conductive pad disposed on the electronic component and electrically connected to the electronic component; and a redistribution structure disposed on the conductive pad and comprising a plurality of conductive layers; a polymer layer surrounding the conductive layer; and a bump electrically connected to the conductive pad via the conductive layer. The center of the conductive pad is horizontally offset from the center of the bump. The conductive layer comprises a first conductive layer, the first conductive layer having a side surface, the side surface contacting the polymer layer and having a side edge, the side edge having a roughness of 0.08 μm to 0.8 μm in a cross-sectional view. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following will describe various aspects of the present disclosure in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure. It should also be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered to limit its scope. The present disclosure is equally applicable to other embodiments.

[0007] According to some embodiments of the present disclosure, Figures 1 to 5 Schematic diagram showing a cross-section of an electronic device at different manufacturing stages.

[0008] According to some embodiments of the present disclosure, Figure 6 show Figure 5 An enlarged view of a local area of ​​an electronic device.

[0009] According to some embodiments of the present disclosure, Figure 7 as well as Figure 8 Schematic diagram showing a cross-section of an electronic device at different manufacturing stages.

[0010] According to some embodiments of the present disclosure, Figure 9 show Figure 8 An enlarged view of a local area of ​​an electronic device.

[0011] According to some embodiments of the present disclosure, Figures 10 to 12 Schematic diagram showing a cross-section of an electronic device at different manufacturing stages.

[0012] According to some embodiments of the present disclosure, Figure 13 show Figure 12 A partial enlarged view of an electronic device.

[0013] Figure 1-13 The reference numerals in the figures are described as follows:

[0014] 100: Substrate

[0015] 101: Adhesive layer

[0016] 105: Substrate

[0017] 110: Electronic components

[0018] 120: Circuit layer

[0019] 130: Barrier layer

[0020] 140: Passivation layer

[0021] 141: Segment

[0022] 142: Segment

[0023] 150: Conductive pad

[0024] 160: polymer layer

[0025] 170: Opening

[0026] 180: Molding layer

[0027] 190: Photoresist

[0028] 200: Seed layer

[0029] 210: Conductive layer

[0030] 220: Seed layer

[0031] 230: Conductive layer

[0032] 240: Seed layer

[0033] 250: Conductive layer

[0034] 260: Bump

[0035] 300: Redistribution Structure

[0036] 500: Local area

[0037] 800: Local area

[0038] 1200: Local area

[0039] 150S: Surface

[0040] 150T: Surface

[0041] A1: Space

[0042] A2: Space

[0043] C1: Center

[0044] C2: Center

[0045] D1: Distance

[0046] D2: Distance

[0047] E1: Edge

[0048] E2: Surface

[0049] E3: Surface

[0050] E4: surface

[0051] E5: Surface

[0052] L: Reference Line

[0053] Rp1: Peak point

[0054] Rp2: Peak point

[0055] Rp3: Peak point

[0056] Rp4: Peak point

[0057] Rp5: Peak point

[0058] Rv1: trough point

[0059] Rv2: trough point

[0060] Rv3: trough point

[0061] Rv4: trough point

[0062] Rv5: trough point

[0063] T1: thickness

[0064] T2: Thickness

[0065] W1: width

[0066] W2: width DETAILED DESCRIPTION

[0067] The following provides some embodiments or examples of the present disclosure for implementing different components of the provided target object. Specific examples of each component and its configuration are described below to simply and clearly describe the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description refers to a first component formed on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that they are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or configurations discussed.

[0068] In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used to facilitate describing the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative adjectives used herein will be interpreted based on the resulting orientation.

[0069] Furthermore, when a component or film layer is referred to as being "on" or "connected to" another component or film layer, it can be directly on or directly connected to the other component or layer, or there can be intervening components or layers between the two (indirect case). Conversely, when a component is referred to as being "directly on" or "directly connected to" another component or film layer, there are no intervening components or layers between the two. In addition, the terms "electrically connected" or "coupled" include any direct and indirect electrical connection means.

[0070] The use of ordinal numbers such as "first," "second," and "third" in this disclosure to modify components does not, by itself, indicate any prior ordinal number of the component(s), nor does it indicate the order of one component relative to another, or the order of manufacturing methods. These ordinal numbers are used solely to clearly distinguish a component with a certain name from another component with the same name. The claims and the specification may use different terms; for example, a first component in the specification may be a second component in the claims.

[0071] In this disclosure, the terms "about" and "substantially" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The phrase "a range between a first value and a second value" means that the range includes the first value, the second value, and any other values ​​therebetween. The quantities given herein are approximate quantities, that is, even without the specific wording "about" or "substantially," the meaning of "about" or "substantially" may still be implied.

[0072] The following describes some embodiments of the present disclosure. Additional steps or operations may be provided before, during, and / or after the steps or operations described in these embodiments. Some of the steps or operations may be replaced or deleted in different embodiments. In addition, it should be understood that the following embodiments may replace, combine, or reorganize the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features between the embodiments may be arbitrarily reorganized and used in combination as long as they do not violate the spirit of the invention or conflict with each other.

[0073] According to an embodiment of the present disclosure, the electronic device includes a power module, a semiconductor packaging device, a display device, a backlight device, an antenna device, a touch device, a sensing device, a wearable device, a vehicle device, a battery device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. Furthermore, the electronic device may, for example, include liquid crystal, quantum dots (QD), fluorescence, phosphorescence, other suitable materials or a combination of the foregoing. The electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, integrated circuits, etc. The diode may include a light-emitting diode or a photodiode. The light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (QDLED), but is not limited thereto. According to some embodiments, the electronic device may include a panel and / or a backlight module, and the panel may, for example, include a liquid crystal panel or other self-luminous panel, but is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. It should be understood that the electronic device may be any of the foregoing arrangements and combinations, but is not limited thereto. According to some embodiments, the manufacturing method of the provided electronic device may include a wafer-level package (WLP) process or a panel-level package (PLP) process, and may adopt a chip first process or a chip last / RDL first process, which will be further described in detail below. The electronic device referred to in this disclosure may include, but is not limited to, a system on a chip (SoC), a system in a package (SiP), an antenna in a package (AiP), or a combination thereof. In the embodiments of this disclosure, the electronic component is illustrated as a die. Furthermore, the die may be a semiconductor die, and the electronic device may be a semiconductor package.

[0074] refer to Figure 1, the electronic component 110 is arranged on the first substrate 100 by the adhesive layer 101. In some embodiments, the first substrate 100 may include glass, quartz, ceramic, steel plate, silicon wafer, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first substrate 100 may be a glass substrate, such as oxide glass, fluoride glass, oxynitride glass, but the present disclosure is not limited thereto. In other embodiments, the first substrate 100 may be a wafer, but the present disclosure is not limited thereto. In some embodiments, the electronic component 110 may include an integrated circuit die, a surface mount device (SMD), other suitable electronic components, or a combination thereof, but the present disclosure is not limited thereto.

[0075] Continue to refer Figure 1 , the adhesive layer 101 is disposed on the first substrate 100. The adhesive layer 101 can be separated from the overlying structure together with the first substrate 100 in a subsequent step. In some embodiments, the adhesive layer 101 may include a polymer-based material, but the present disclosure is not limited thereto. For example, the adhesive layer 101 may include a thermal release tape (HRT) or a light-to-heat-conversion (LTHC) coating, which loses its adhesiveness when heated. In other embodiments, the adhesive layer 101 may include an ultraviolet (UV) adhesive, which loses its adhesiveness when exposed to ultraviolet light. In yet other embodiments, the adhesive layer 101 may lose its adhesiveness by a laser stripping process. In some embodiments, the adhesive layer 101 may be formed by a coating and curing process, a lamination process, other suitable processes, or a combination of the above.

[0076] Continue to refer Figure 1 Between the electronic component 110 and the adhesive layer 101, a circuit layer 120, a barrier layer 130, a passivation layer 140, a conductive pad 150, a polymer layer 160, and an opening 170 are further included. In some embodiments, the circuit layer 120 may include copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), molybdenum (Mo), aluminum (Al), silver (Ag), gold (Au), other suitable materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the barrier layer 130 may include titanium (Ti), tantalum (Ta), other suitable materials, or combinations thereof, but the present disclosure is not limited thereto.

[0077] In some embodiments, the passivation layer 140 may include an inorganic material. For example, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the passivation layer 140 may be formed by a coating process (e.g., a spin coating process), a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), other suitable methods, or a combination thereof. The passivation layer 140 may reduce the effects of moisture and oxygen on the electronic component 110 from the external environment. In addition, the passivation layer 140 may be patterned by one or more photolithography processes and / or etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying, etc., but the present disclosure is not limited thereto. The etching process may include a dry etching process or a wet etching process, but the present disclosure is not limited thereto.

[0078] In some embodiments, the conductive pad 150 may include a conductive material, such as aluminum (Al) or other suitable conductive materials, but the present disclosure is not limited thereto. In some embodiments, the conductive material may be formed by a physical vapor deposition (PVD) process, an electroplating process, an electroless plating process (also referred to as an electroless plating process), other suitable methods, or a combination thereof. Furthermore, the conductive material may be patterned by one or more photolithography processes and / or etching processes to form the conductive pad 150.

[0079] In some embodiments, the polymer layer 160 may include a polymer dielectric material, such as polybenzodibenzo[pi]n- ... The polymer layer 160 may be formed by a coating process (e.g., a spin coating process), a lamination process, a chemical vapor deposition process, other suitable methods, or a combination thereof, but the present disclosure is not limited thereto.

[0080] refer to Figure 2, forming a molding layer 180 to seal the electronic component 110. In some embodiments, the molding layer 180 may include a molding compound, epoxy, other suitable packaging materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the molding layer 180 may be formed by a compression molding process, a transfer molding process, or other suitable methods. In some embodiments, the molding layer 180 may be molded in a liquid or semi-liquid state and then cured. Subsequently, a planarization process, such as chemical mechanical polishing (CMP), may be performed to make the top surface of the molding layer 180 flush with the top surface of the electronic component 110.

[0081] refer to Figure 3 After forming the mold layer 180, the adhesive layer 101 can be de-adhesive by, for example, a heat treatment, UV treatment, or laser treatment, thereby separating the structure on the adhesive layer 101 from the adhesive layer 101 and the first substrate 100. The structure originally on the adhesive layer 101 is flipped over and placed on the second substrate 105. The material of the second substrate 105 can be similar to that of the first substrate 100 and will not be further described here.

[0082] Continue to refer Figure 3 , a first seed layer 200 is formed on the polymer layer 160, on the mold layer 180, and in the opening 170. In some embodiments, the first seed layer 200 may include titanium (Ti), tantalum (Ta), copper (Cu), other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first seed layer 200 may be formed by an atomic layer deposition process (ALD), a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. The physical vapor deposition process may, for example, include a sputtering process and an evaporation process. Subsequently, a dry film photoresist 190 may be formed on the first seed layer 200.

[0083] refer to Figure 4 , forming a first conductive layer 210 between the dry film photoresist 190. In some embodiments, the first conductive layer 210 may include copper (Cu), nickel (Ni), other suitable conductive materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the first conductive layer 210 may be formed by a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or combinations thereof. After forming the first conductive layer 210, the dry film photoresist 190 is removed.

[0084] refer to Figure 5 The first seed layer 200 may be patterned by one or more photolithography processes and / or etching processes. In addition, the side surface of the first conductive layer 210 may be roughened by an etching process. The etching process may include a dry etching process, a wet etching process, or other suitable etching processes. Figure 13 In other embodiments, when forming the dry film photoresist 190 (such as Figure 3 After forming the first conductive layer 210 (as shown in FIG. Figure 4 As shown in FIG, before the step of forming the first conductive layer 210, the side surface of the dry film photoresist 190 may be roughened by an etching process, so that the sidewall of the first conductive layer 210 formed subsequently may be roughened due to the rough side surface of the dry film photoresist 190.

[0085] refer to Figure 6 , Figure 6 show Figure 5 An enlarged view of a local area 500 of an electronic device. The lower half of the first conductive layer 210 contacting the conductive pad 150 has an arc-shaped edge, which can improve the risk of peeling. In detail, if the lower half of the first conductive layer 210 contacting the conductive pad 150 is at a right angle, the stress will be concentrated at the turning point of the right angle, resulting in an increased risk of peeling. On the contrary, the lower half of the first conductive layer 210 contacting the conductive pad 150 has an arc-shaped edge, and the stress will change and release in a radial manner along the arc-shaped edge, rather than being concentrated in a single direction or a single turning point, thereby improving the risk of peeling and improving the reliability of the electronic device.

[0086] Continue to refer Figure 6 , the passivation layer 140 is disposed between the conductive pad 150 and the polymer layer 160, and the passivation layer 140 has an opening exposing the conductive pad 150. That is, the opening of the passivation layer 140 overlaps the conductive pad 150. Figure 6In the embodiment, the bottom width W2 of the first conductive layer 210 is smaller than the bottom width W1 of the opening, and the ratio of the bottom width W2 to the bottom width W1 is between 0.5 and 0.8 (greater than or equal to 0.5 and less than or equal to 0.8). That is, 0.5≦W2 / W1≦0.8. The ratio of the bottom width W2 to the bottom width W1 being within the above range can improve the risk of peeling while maintaining the desired impedance. In detail, the bottom width W1 of the opening is the width of the conductive pad 150 exposed by the above opening, and the bottom width W2 is the bottom plane width of the first conductive layer 210 closest to the conductive pad 150. Since the material of the polymer layer 160 is more elastic than the passivation layer 140, the conductive pad 150 and the first conductive layer 210, it can have a buffering effect between the components. If the bottom width W2 of the first conductive layer 210 is too large, the space A1 will be compressed too small, and the amount that can be filled with the polymer layer 160 will be reduced, which will reduce the buffering capacity between the components and increase the risk of peeling. If the bottom width W2 of the first conductive layer 210 is too small, the contact area between the first conductive layer 210 and the conductive pad 150 will be too small, resulting in excessive impedance between the first conductive layer 210 and the conductive pad 150. Therefore, setting the ratio of the bottom width W2 to the bottom width W1 between 0.5 and 0.8 can reduce the risk of delamination while maintaining the desired impedance.

[0087] It should be understood that in some embodiments, a scanning electron microscope (SEM), an optical microscope (OM), an α-step thin film thickness profilometer, an ellipsometer, or other suitable methods can be used to measure the width, thickness, or height of each component, as well as the spacing or distance between components. Specifically, in some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structural image containing the component to be measured, and the width, thickness, or height of each component, as well as the spacing or distance between components can be measured.

[0088] Continue to refer Figure 6The passivation layer 140 has a first portion disposed on the conductive pad 150. The first portion has a first segment 141 disposed on the top surface 150T of the conductive pad 150 and a second segment 142 disposed on the side surface 150S of the conductive pad 150. The first portion has a curved edge E1, which can reduce the risk of peeling to improve the reliability of the electronic device. In detail, if the edge E1 of the passivation layer 140 is linear, there will be a turning angle between the hypotenuse and the top surface of the passivation layer 140, and the stress (for example, caused by the difference in thermal expansion and contraction between the passivation layer 140 and the polymer layer 160) will be concentrated at the turning angle, resulting in an increased risk of peeling. On the contrary, if the edge E1 of the passivation layer 140 is curved, the stress will change and be released in a radial manner along the curved edge E1, rather than being concentrated in a single direction or at the turning point. In addition, the curved edge E1 can increase the contact area with the polymer layer 160, thereby improving the adhesion between the passivation layer 140 and the polymer layer 160.

[0089] Continue to refer Figure 6 , the first segment 141 of the passivation layer 140 has a thickness T1 on the top surface of the conductive layer 150 (measured along the normal direction of the top surface of the conductive layer 150), and the second segment 142 of the passivation layer 140 has a thickness T2 on the side surface of the conductive layer 150 (measured along the normal direction of the side surface of the conductive layer 150). Thickness T1 is greater than thickness T2, which can improve the risk of peeling to improve the reliability of the electronic device. In detail, since the material of the polymer layer 160 is more elastic than the passivation layer 140, the conductive pad 150 and the first conductive layer 210, it can have a buffering effect between the components. If the thickness T2 is greater than the thickness T1, the passivation layer 140 compresses the space A2, and the amount of polymer layer 160 that can be filled is reduced, which reduces the buffering capacity between the components and increases the risk of peeling. On the contrary, thickness T1 is greater than thickness T2 to ensure that there is more polymer layer 160 in space A2, thereby having a better ability to buffer stress.

[0090] refer to Figure 7 A polymer layer 160 is formed on the first seed layer 200 and the first conductive layer 210, and a planarization process, such as a chemical mechanical polishing process, is performed to make the top surface of the polymer layer 160 flush with the top surface of the first conductive layer 210. The materials and formation method of the polymer layer 160 can be referred to above and will not be repeated here.

[0091] refer to Figure 8, a second seed layer 220, a second conductive layer 230, a third seed layer 240, and a third conductive layer 250 are formed on the first conductive layer 210. In some embodiments, the materials and formation methods of the second conductive layer 230 and the third conductive layer 250 can be similar to those of the first conductive layer 210 and are not further described here. The materials and formation methods of the second seed layer 220 and the third seed layer 240 can be similar to those of the first seed layer 200 and are not further described here.

[0092] refer to Figure 9 , which shows Figure 8 An enlarged view of a local area 800 of an electronic device. The first seed layer 200 is disposed between the conductive pad 150 and the first conductive layer 210, and the side surface E2 of the first seed layer 200 protrudes from the side surface E3 of the first conductive layer 210 by a first distance D1 greater than zero, which can improve the risk of peeling to improve the reliability of the electronic device. In detail, the adhesion between the first seed layer 200 and the polymer layer 160 is better than the adhesion between the first conductive layer 210 and the polymer layer 160. If the side surface of the first conductive layer 210 extends beyond the side surface of the first seed layer 200, or the side surfaces of the two are flush, a larger portion of the first conductive layer 210 will directly contact the polymer layer 160. Due to the poor adhesion between the two, the risk of peeling increases.

[0093] Continue to refer Figure 9 The second conductive layer 230 is disposed on the first conductive layer 210 and is electrically connected to the first conductive layer 210. The second seed layer 220 is disposed between the first conductive layer 210 and the second conductive layer 230. The side surface E4 of the second seed layer 220 protrudes from the side surface E5 of the second conductive layer 230 by a second distance D2. Because the first conductive layer 210 formed on the first seed layer 200 is thicker than the second conductive layer 230 formed on the second seed layer 220, the distance that the side surface E2 of the first seed layer 200 protrudes from the side surface E3 of the first conductive layer 210 must be greater than the distance that the side surface E4 of the second seed layer 220 protrudes from the side surface E5 of the second conductive layer 230 to ensure stable adhesion. In other words, the first distance D1 is greater than the second distance D2, which can reduce the risk of delamination and improve the reliability of the electronic device.

[0094] refer to Figure 10 , forming a bump 260 on the third conductive layer 250. In some embodiments, the bump 260 may include copper (Cu), tin (Sn), bismuth (Bi), other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the bump 260 may be formed on the third conductive layer 250 by a reflow process, a fusion bonding process, a metal-to-metal bonding process, other suitable methods, or a combination thereof. Figure 10 As shown, the redistribution structure 300 includes a first seed layer 200 and a first conductive layer 210 thereon; a second seed layer 220 and a second conductive layer 230 thereon; a third seed layer 240 and a third conductive layer 250 thereon; a polymer layer 160 surrounding the seed layers 200, 220, 240 and the conductive layers 210, 230, 250; and a bump 260. Figure 10 As shown, among the first conductive layer 210 , the second conductive layer 230 and the third conductive layer 250 , the first conductive layer 210 is closest to the conductive pad 150 , and the center C1 of the conductive pad 150 is horizontally offset from the center C2 of the bump 260 .

[0095] It should be understood that, according to different embodiments, the redistribution structure 300 may include any suitable number of polymer layers, seed layers, and conductive layers. If more polymer layers, seed layers, and conductive layers are to be formed, the above steps and processes may be repeated. The redistribution structure enables the circuits of the electronic device to be redistributed and / or further increases the circuit fan-out area. Alternatively, different electronic components may be electrically connected to each other through the redistribution structure. Alternatively, the redistribution structure may be used to redistribute the size of the contact pads for circuit fan-out or fan-in of the chip. For example, the spacing between two adjacent contact pads of the redistribution structure contacting one end of the chip is smaller than the spacing between two adjacent contact pads of the redistribution structure away from one end of the chip.

[0096] refer to Figure 11 The adhesive layer on the second substrate 105 can be de-adhesive by, for example, a heat process, an ultraviolet light process, or a laser process, so that the electronic component 110 and the structure thereon are separated from the second substrate 105. After separation from the second substrate 105, a singulation process can be performed on the electronic component 110. The resulting structure is as follows: Figure 12 shown.

[0097] refer to Figure 13 , which shows Figure 12An enlarged view of a local area 1200 of an electronic device. In some embodiments, after forming the first conductive layer 210, the side surface (side edge) of the first conductive layer 210 contacting the polymer layer 160 can be roughened by an etching process to form a microstructure, for example, a plurality of recesses, on the side edge of the first conductive layer 210. In some embodiments, the etching process may include a dry etching process, a wet etching process or other suitable etching processes. In some embodiments, the side edge of the first conductive layer 210 has a roughness Rz of 0.08 μm to 0.8 μm, which can improve the risk of peeling to improve the reliability of the electronic device. In detail, if the side surface of the first conductive layer 210 is not roughened, the side surface of the first conductive layer 210 is smoother and the contact area with the polymer layer 160 is smaller, so it is easy to peel off from the polymer layer 160. It should be noted that the roughness Rz described in the embodiment of the present disclosure is calculated by a cross-sectional image obtained by a scanning electron microscope (SEM). In detail, in Figure 13 In this method, five peaks (Rp1, Rp2, Rp3, Rp4, and Rp5) and five valleys (Rv1, Rv2, Rv3, Rv4, and Rv5) are selected from the side edge of the first conductive layer 210. A reference line L is set between the peaks Rp1-Rp5 and the valleys Rv1-Rv5. The value of reference line L is set to 0, with positive values ​​toward the peaks Rp1-Rp5 and negative values ​​toward the valleys Rv1-Rv5. The numerical differences between the peaks Rp1 and Rv1, the peaks Rp2 and Rv2, the peaks Rp3 and Rv3, the peaks Rp4 and Rv4, and the peaks Rp5 and Rv5 are calculated. The average of these five numerical differences is summed to obtain the roughness Rz. Therefore, the roughness Rz can be expressed by the following formula:

[0098]

[0099] It should be understood that for the purpose of clarity, Figure 13 The side surface of the first conductive layer 210 is shown to be roughened. However, the side surfaces of the second conductive layer 230 and the third conductive layer 250 to be formed subsequently may also be roughened.

[0100] In summary, in some embodiments of the present disclosure, by roughening the side surface of the conductive layer so that the side surface of the conductive layer has a roughness Rz between 0.08μm and 0.8μm, the risk of peeling is improved. In other embodiments of the present disclosure, by forming the portion of the conductive layer in contact with the conductive pad into an arc shape and / or forming the edge of the passivation layer into an arc shape, stress concentration in a single direction or a single turning point can be avoided, so that the stress can change and release in a radial manner along the edge of the arc, thereby improving the risk of peeling. In addition, by setting the ratio of the bottom width of the conductive layer to the bottom width of its corresponding opening so that the ratio is between 0.5 and 0.8, the space that can be filled by the polymer layer can be increased without negatively affecting the impedance of the electronic device, thereby improving the buffering capacity and improving the risk of peeling. Furthermore, by forming the thickness of the segment of the passivation layer located on the oblique edge of the conductive pad to be smaller than the thickness of the segment of the passivation layer located on the top surface of the conductive pad, the space that can be filled by the polymer layer can be increased to improve the buffering capacity and thus improve the risk of peeling. In some other embodiments of the present disclosure, by protruding the side surface of the seed layer a certain distance from the side surface of the conductive layer, the area with better adhesion can be increased, thereby reducing the risk of delamination. In addition, the protrusion distance of the seed layer with a thicker conductive layer above it must be greater than the protrusion distance of the seed layer with a thinner conductive layer above it to ensure stable adhesion.

[0101] Although the embodiments of the present disclosure and their benefits have been disclosed as above, it should be understood that those skilled in the art may make changes, substitutions and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. The features between the embodiments may be mixed and matched as they please as long as they do not violate the spirit of the present disclosure or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Those skilled in the art may understand from the disclosure of the present disclosure that the processes, machines, manufactures, material compositions, devices, methods and steps currently or in the future may be developed, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they may be used in accordance with the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be subject to the scope of the appended claims. Any embodiment or claim of the present disclosure is not required to achieve all the purposes, benefits and features disclosed in this disclosure.

Claims

1. An electronic device, characterized in that: include: an electronic component; a conductive pad disposed on the electronic component and electrically connected to the electronic component; as well as a redistribution structure disposed on the conductive pad and comprising a plurality of conductive layers; and a polymer layer surrounding the plurality of conductive layers; and a bump electrically connected to the conducting pad through the plurality of conducting layers, wherein a center of the conducting pad is horizontally offset from a center of the bump; The plurality of conductive layers include a first conductive layer having a side surface, the side surface contacts the polymer layer and has a side edge, and the side edge has a roughness of 0.08 μm to 0.8 μm in a cross-sectional view.

2. The electronic device according to claim 1, wherein Among the plurality of conductive layers, the first conductive layer is closest to the conductive pad, and in the cross-sectional view, a lower half of the first conductive layer has an arc-shaped edge.

3. The electronic device according to claim 1, wherein: The invention further comprises a passivation layer disposed between the conductive pad and the polymer layer, wherein the passivation layer has an opening overlapping the conductive pad, and in the cross-sectional view, a first bottom width of the first conductive layer is smaller than a second bottom width of the opening.

4. The electronic device according to claim 3, wherein: The ratio of the first bottom width to the second bottom width ranges from 0.5 to 0.

8.

5. The electronic device according to claim 3, wherein: The passivation layer has a first portion disposed on the conductive pad. The first portion has a first segment disposed on a top surface of the conductive pad and a second segment disposed on a side surface of the conductive pad.

6. The electronic device according to claim 5, wherein: The thickness of the first segment is greater than the thickness of the second segment.

7. The electronic device according to claim 5, wherein: In the cross-sectional view, the first portion has an arc-shaped edge.

8. The electronic device according to claim 1, wherein: The method further includes a first seed layer disposed between the conducting pad and the first conducting layer, wherein the first seed layer protrudes from the side surface of the first conducting layer by a first distance greater than zero.

9. The electronic device according to claim 8, wherein: The plurality of conductive layers include a second conductive layer disposed on the first conductive layer, wherein the second conductive layer is electrically connected to the first conductive layer.

10. The electronic device according to claim 9, wherein: The invention further comprises a second seed layer disposed between the first conductive layer and the second conductive layer, wherein the second seed layer protrudes from a side surface of the second conductive layer by a second distance, and the first distance is greater than the second distance.

11. The electronic device according to claim 1, wherein: The invention further comprises a molding layer for sealing the electronic component.

12. The electronic device according to claim 1, wherein: The electronic component is a semiconductor die.

13. The electronic device according to claim 1, wherein: The electronic device is a semiconductor package.

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