Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof, in particular to a method for reducing wafer warping. A method of forming a semiconductor device according to an embodiment of the present disclosure includes depositing a compression dielectric layer on an element wafer, the element wafer including a first substrate, an element layer on the first substrate, and a first interconnect structure on the element layer; depositing a first bonding layer on the compression dielectric layer; depositing a second bonding layer on the second substrate; and bonding the second substrate and the element wafer by bonding the first bonding layer and the second bonding layer. The first bonding layer and the second bonding layer comprise dielectric materials, and the heat conduction degree of the dielectric materials is larger than that of silicon oxide.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to reducing wafer warpage. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (e.g., the number of interconnected elements per chip area) has generally increased, while geometry size (e.g., the smallest component (or trace) that can be created using a process) has decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs. However, this downsizing also increases the complexity of fabricating ICs.

[0003] As integrated circuit (IC) device miniaturization continues, routing of IC components can be achieved not only through front-side interconnects but also through back-side interconnects. Forming back-side interconnects can involve bonding the device wafer to a carrier substrate via a bonding layer, as well as flip-chip placement of the device wafer. The bonding layer can affect heat dissipation. Summary of the Invention

[0004] A semiconductor device includes a substrate; a bonding layer on the substrate; a compressive dielectric layer on the bonding layer; a first interconnect structure on the compressive dielectric layer; a device layer on the first interconnect structure; and a second interconnect structure on the device layer. The bonding layer has a kappa (κ) value between 10 and 100.

[0005] A method for forming a semiconductor device includes: depositing a compressive dielectric layer on a device wafer, the device wafer including a first substrate, a device layer on the first substrate, and a first interconnect structure on the device layer; depositing a first bonding layer on the compressive dielectric layer; depositing a second bonding layer on a second substrate; and bonding the second substrate to the device wafer by bonding the first bonding layer and the second bonding layer. The first bonding layer and the second bonding layer include a dielectric material having a thermal conductivity greater than that of silicon oxide (SiO).

[0006] A method for forming a semiconductor device includes: forming a device layer on a first substrate; forming a front-side interconnect structure on the device layer; depositing a compressive dielectric layer on the front-side interconnect structure; depositing a first bonding layer on the compressive dielectric layer; depositing a second bonding layer on a second substrate; bonding the second substrate to the first substrate by bonding the first bonding layer and the second bonding layer; thinning the first substrate; and, after thinning the first substrate, forming a back-side interconnect structure on the device layer. The first bonding layer and the second bonding layer include titanium oxide or aluminum nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following describes the embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are provided for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure.

[0008] Figure 1 FIG1 is a flow chart illustrating a method for forming a device die according to one or more aspects of the present disclosure.

[0009] Figures 2 to 14 According to one or more aspects of the present disclosure, a device wafer and / or a carrier substrate is shown in FIG. Figure 1 Schematic cross-section during the fabrication process of the method.

[0010] The description of the accompanying drawings is as follows:

[0011] 100: Method

[0012] 102: Box

[0013] 104: Box

[0014] 106: Box

[0015] 108: Box

[0016] 110: Box

[0017] 112: Box

[0018] 114: Box

[0019] 116: Box

[0020] 200: Component wafer

[0021] 202: First substrate

[0022] 204: Component layer

[0023] 206: Contact layer

[0024] 208: Front-side interconnection structure

[0025] 210: Etch stop layer

[0026] 212: Compressed film

[0027] 213: Surface reforming dielectric layer

[0028] 214: First bonding layer

[0029] 216: Second bonding layer

[0030] 218: Bonding layer

[0031] 220: Second substrate

[0032] 230: Backside interconnect structure

[0033] 240: Redistribution layer

[0034] 250: Bump components

[0035] 300: Planarization process

[0036] 400: Component Die

[0037] 450: Component Die

[0038] 500: Intermediary layer

[0039] 600: Package substrate

[0040] 1000: Wafer suction cup

[0041] 1200: Probe

[0042] P: Reference plane

[0043] W: Warp DETAILED DESCRIPTION

[0044] The following disclosure provides many different embodiments or examples for implementing different components of the provided services. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, the description of a first component formed on a second component may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present disclosure may repeat reference symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not, in itself, dominate the relationship between the various embodiments and / or configurations discussed.

[0045] Spatially relative terms such as "below," "beneath," "below," "above," "above," and the like may be used herein to describe the relationship of one element or component to another element or component as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. When the device is otherwise oriented (rotated 90 degrees or at other orientations), the spatially relative descriptors used herein should be interpreted in that rotated orientation.

[0046] In addition, when using "about", "approximately", etc. to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range, which is based on the variations inherent in the manufacturing process understood by those with ordinary skill in the art. For example, based on the known manufacturing tolerances for manufacturing parts with the characteristics associated with the numbers, the number or range of numbers covers a reasonable range including the number, such as within ±10% of the number. For example, the manufacturing tolerance associated with deposited material layers is known to those with ordinary skill in the art to be ±15%, and a material layer with a thickness of "about 5 nanometers" may cover a size range of 4.25 nanometers to 5.75 nanometers. For the avoidance of doubt, the X direction, Y direction, and Z direction in the figures of this disclosure are perpendicular to each other. Throughout this disclosure, the same parts may be marked with the same symbols unless there are exceptions.

[0047] For semiconductor devices fabricated on a bulk semiconductor substrate, the bulk semiconductor substrate can act as a heat sink, dissipating heat generated by the semiconductor device and conducting it into the heat sink. In some technologies that thin or substantially remove the semiconductor substrate to implement backside interconnect structures, a carrier substrate is bonded to the frontside interconnect structure via a bonding layer. When the bonding layer includes less than an ideal thermal conductor, heat from the semiconductor device cannot be effectively dissipated. Due to self-heating, the semiconductor device can experience degradation and may even induce substantial warpage.

[0048] The present disclosure provides a method for reducing warpage of a component wafer and improving the heat conduction path to avoid damage to the semiconductor device on the component wafer. In one embodiment, a compressive dielectric layer is deposited on the component wafer to apply compressive stress to the component wafer. The component wafer includes a first substrate, a component layer on the first substrate, and a first interconnect structure on the component layer. A first bonding layer is deposited on the compressive dielectric layer, and a second bonding layer is deposited on the second substrate. The second substrate is bonded to the component wafer by bonding the first bonding layer and the second bonding layer. The first substrate is thinned, and a second interconnect structure is provided on the component layer. The compressive dielectric layer may include silicon nitride (SiN). The first bonding layer and the second bonding layer may include a dielectric material, the thermal conductivity of the dielectric material being greater than the thermal conductivity of silicon oxide (SiO) (for example, approximately 1 W / m·K).

[0049] Various aspects of the present disclosure will now be described in detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 for forming a device die according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the present disclosure to the specific depiction of the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method 100. For the sake of simplicity, not all steps are described in detail. The method 100 will be combined with Figures 2 to 14 As detailed below, Figures 2 to 14 1 is a schematic cross-sectional view of a device wafer and / or a carrier substrate at different manufacturing stages according to an embodiment of the method 100. Throughout this disclosure, identical components may be designated by identical reference numerals unless otherwise specified.

[0050] Reference Figure 1 and Figure 2 , method 100 includes block 102, wherein a component wafer 200 is received. Figure 2In some embodiments, the device wafer 200 includes a first substrate 202, a device layer 204 fabricated on the first substrate 202, a contact layer 206 on the device layer 204, and a front-side interconnect structure 208 on the contact layer 206. In semiconductor technology, the device layer 204 is fabricated before the contact layer 206 and the front-side interconnect structure 208 and is considered a front-end of line (FEOL) structure. The contact layer 206 is fabricated after the device layer 204 and is used to connect the devices in the device layer 204 to the front-side interconnect structure 208. The contact layer 206 may be referred to as a middle-end of line (MEOL) structure. The front-side interconnect structure 208 is fabricated after the device layer 204 and the contact layer 206 and is referred to as a back-end of line (BEOL) structure.

[0051] In some embodiments, the first substrate 202 may be a silicon (Si) substrate. In other embodiments, the first substrate 202 includes: an elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide (GaInAs). arsenicphosphide, GaInAsP); or a combination thereof. In some embodiments, the first substrate 202 includes one or more III-V materials, one or more II-VI materials, or a combination thereof. In some further examples, the first substrate 202 is a semiconductor substrate on an insulator, such as a silicon on insulator (SOI) substrate, a silicon germanium on insulator (SGOI) substrate, or a germanium on insulator (GeOI) substrate. The first substrate 202 may include an N-type doped or P-type doped well region. The N-type doped region includes an N-type dopant, such as phosphorus (P) or arsenic (As). The P-type doped region includes a P-type dopant, such as boron (B). In some examples, the first substrate 202 may have a thickness between approximately 750 μm and 800 μm.

[0052] The device layer 204 may include planar devices or multi-gate devices. A planar device represents a device having a gate structure present on one side of the channel region. As integrated circuit technology evolves to smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). A multi-gate device generally represents a device having a gate structure or portion thereof disposed on more than one side of the channel region. Fin field effect transistors (finFETs) and gate-all-around (GAA) transistors (both also referred to as non-planar transistors) are examples of multi-gate devices that have become popular and reliable choices for high-performance and low-leakage current applications. FinFETs have an upward-pointing channel that is surrounded by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from the substrate). Compared to planar transistors, this configuration provides better channel control and significantly reduces short channel effects (particularly by reducing subthreshold leakage current (e.g., coupling between the source and drain of a FinFET in the off state)). A wrapped gate transistor has a gate structure that extends (partially or completely) around the channel region to provide access to the channel region on two or more sides. Due to this configuration, a wrapped gate transistor may also be referred to as a surrounding gate transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of a wrapped gate transistor may be formed from a nanowire, a nanosheet, other nanostructures, and / or other suitable structures. The shape of these channel regions also gives wrapped gate transistors different names. For example, a wrapped gate transistor with a nanosheet channel region may be referred to as a nanosheet transistor. In the embodiment described, device layer 204 includes multi-gate transistors, such as wrapped gate transistors. Generally, planar transistors tend to have larger feature sizes and generally do not require backside interconnect structures for routing.

[0053] In the illustrated embodiment, the transistors in the device layer 204 have a fully wrapped gate configuration. Each transistor includes a plurality of channel members stacked vertically on the first substrate 202. The plurality of channel members extend between two source / drain components. A gate structure surrounds each channel member. The gate structure is separated from the two source / drain components by a plurality of inner spacer components. The plurality of inner spacer components are vertically staggered with the plurality of channel members. The top of the gate structure is aligned with the top gate spacer. In some embodiments, the plurality of channel members include silicon. The gate structure includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interfacial layer (IL) to interface the channel members with a high-k gate dielectric layer on the interfacial layer. High-k dielectric materials, as described and used herein, include dielectric materials having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide (approximately 3.9). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate (HfSiO), or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k gate dielectric layer may include hafnium oxide (HfO2). Alternatively, the high-k gate dielectric layer may include other high-k dielectric materials such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO x)、tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), strontium titanate (STO), SrTiO3), barium titanate (BTO), BaTiO3), barium zirconate (BZO), BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), The high-k gate dielectric layer may be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0054] The gate electrode layer may include a single layer or alternatively a multilayer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layers), liner layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed using atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes.

[0055] The source / drain features of the transistors in device layer 204 may include silicon doped with an N-type dopant (e.g., phosphorus or arsenic), or silicon germanium doped with a P-type dopant (e.g., boron or boron difluoride (BF2)). The interspacer features may include silicon nitride, silicon oxycarbonitride (SiOCN), silicon oxynitride, or silicon oxycarbide (SiOC). The top gate spacer defines the gate trench during the gate replacement process and may include silicon nitride, silicon oxycarbonitride, silicon oxynitride, or silicon oxycarbide.

[0056] The middle-of-line contact layer 206 may include contacts to the gate structures and source / drain features of the devices in the device layer 204. The contacts to the gate structures (or gate contacts) may include tungsten, ruthenium, copper, or molybdenum (Mo) and couple the gate structures to the front-side interconnect structure 208. The contacts to the source / drain features (or source / drain contacts) may include cobalt, nickel, or copper and couple the source / drain features to the front-side interconnect structure 208. The gate contacts and source / drain contacts in the contact layer 206 extend through at least one etch stop layer (ESL) and at least one interlayer dielectric (ILD) layer. The at least one etch stop layer may include silicon nitride, silicon oxynitride, or aluminum nitride (AlN). The at least one interlayer dielectric layer may include silicon oxide or a dielectric material having a low-k dielectric constant. The gate contact and the source / drain contacts may be separated from at least one etch stop layer and at least one interlayer dielectric layer by a barrier layer. The barrier layer may include titanium nitride or tantalum nitride.

[0057] In some embodiments, the front-side interconnect structure 208 may include 8 to 25 metal layers. Each metal layer includes conductive lines and contact vias embedded in an inter-metal dielectric (IMD) layer. The IMD layer may include materials such as tetraethyl ortho silicate (TEOS) oxide, undoped silicate glass (USG), doped silicon oxide, borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), silicon oxycarbide, and / or other suitable dielectric materials. The conductive lines and contact vias may include copper, titanium nitride, tungsten, or ruthenium. The front-side interconnect structure 208 functions to connect transistors in the device layer 204 via contact features in the contact layer 206. In some embodiments not explicitly shown in the figures, active and passive devices may be included in the front-side interconnect structure 208. Examples of such active and passive devices may include metal-insulator-metal (MIM) capacitors, radio frequency (RF) antennas, deep trench capacitors, memory devices, or transistors.

[0058] In some embodiments, residual stress in the dielectric layer within the device layer 204, contact layer 206, and front-side interconnect structure 208 can cause warpage of the device wafer 200. Generally, the warpage of the device wafer 200 depends on the number of metal layers in the front-side interconnect structure 208. For example, an interconnect structure with 20 metal layers can cause approximately twice as much warpage to the device wafer 200 as an interconnect structure with 10 or fewer metal layers. The warpage W can be measured as the difference between the edge of the device wafer 200 and a reference plane P. In some examples, after forming the front-side interconnect structure 208 and planarizing the top surface of the device wafer 200, the device wafer 200 can include a warpage W between approximately 100 μm and 200 μm.

[0059] Reference Figure 1 and Figure 3 , method 100 includes block 104, in which a compressive film 212 is deposited on the front-side interconnect structure 208. The compressive film 212 comprises a dielectric material and is deposited to apply compressive stress to the device wafer 200 to counteract warpage in the device wafer 200. In some embodiments, the compressive film 212 comprises silicon nitride and is deposited using chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD). The compressive film 212 can apply a compressive stress between approximately 1.75 GPa and 2.4 GPa, which is an order of magnitude greater than the compressive stress of a compressive film formed using silicon oxide. That is, the thickness of the compressive film 212 can be significantly reduced by using the compressive film 212 of the present disclosure. To ensure that the compressive film 212 applies sufficient compressive stress to the device wafer 200 to counterwarp the device wafer 200, the compressive film 212 can have a thickness between approximately 50 nm and 100 nm. This range is not insignificant. When the thickness of the compressive film 212 is less than 50 nm, the compressive film 212 may not be thick enough to fully reverse the warpage of the device wafer 200. When the thickness of the compressive film 212 is greater than 100 nm, the compressive film 212 may cause the device wafer 200 to warp, and the increased thickness may hinder heat dissipation. The thermal conductivity of the compressive film 212 is greater than that of silicon oxide. When the compressive film 212 comprises silicon nitride, it may have a kappa (κ) value (W / m·K) between 2 and 5, while the kappa value of silicon oxide is approximately 1.

[0060] In some embodiments represented in the figures, an etch stop layer 210 may be deposited on the front-side interconnect structure 208 before depositing the compressive film 212. To perform its etch stop function, the etch stop layer 210 is formed from a dielectric material different from the intermetal dielectric layer in the front-side interconnect structure 208 or the compressive film 212. In some embodiments, the etch stop layer 210 comprises silicon carbonitride (SiCN). The etch stop layer 210 may be deposited using chemical vapor deposition or plasma-assisted chemical vapor deposition. In some embodiments, the etch stop layer 210 may serve as an etch stop for forming through-substrate vias (TSVs) when forming TSVs through a carrier wafer (described in more detail below) to electrically connect to the front-side interconnect structure 208.

[0061] Reference Figure 1 、 Figure 4 ,and Figure 5 The method 100 includes block 106, wherein a surface resurfacing process is performed on the device wafer 200. As described above with respect to block 104, the compression film 212 applies a compressive stress to the device wafer 200 to counter-warp the device wafer 200. Although the compression film 212 can solve the problem of warping the device wafer 200, the top surface of the compression film 212 may still have a thickness between about and The average roughness (Ra) between 10 and 20 is not suitable for subsequent bonding process. The surface reforming process in block 106 is intended to reduce the surface roughness. Figure 4 , a surface reforming dielectric layer 213 is deposited on the compression film 212 by chemical vapor deposition. In some embodiments, the surface reforming dielectric layer 213 may include silicon oxide. In one embodiment, depositing the surface reforming dielectric layer 213 may include using tetraethoxysilane, and the surface reforming dielectric layer 213 may be referred to as a tetraethoxysilane oxide layer. In order to remove or reduce the surface reforming dielectric layer 213 at about and The surface roughness of the surface reforming dielectric layer 213 may be between about and The thickness is about 10 times the average roughness of the compression film 212. After the surface reforming dielectric layer 213 is deposited, the surface reforming dielectric layer 213 is planarized 300 to remove about to Materials such as Figure 5 As shown. Figure 5 The entire surface reforming dielectric layer 213 is shown removed, with traces of the surface reforming dielectric layer 213 remaining on the compression film 212 to provide a film having a thickness between about and Surfaces with lower average roughness.

[0062] Reference Figure 1 and Figure 6 , method 100 includes block 108, in which a first bonding layer 214 is deposited on the compressed film 212. As will be described in detail below, the first bonding layer 214 is configured to be bonded to the second bonding layer 216 in a subsequent direct bonding process. Additionally, the first bonding layer 214 and the second bonding layer 216 are located in a thermally conductive path to dissipate heat from the device layer 204. For these reasons, it is desirable to form the first bonding layer 214 from a material that is compatible with the direct bonding process and does not hinder thermal conductivity. In some embodiments, the first bonding layer 214 includes a metal-like material (such as titanium oxide or aluminum nitride) and may have a thickness between approximately 50 nm and 25 μm. In one embodiment, the first bonding layer 214 includes titanium oxide. In some embodiments, the first bonding layer 214 is deposited using atomic layer deposition, chemical vapor deposition, or metal organic chemical vapor deposition (MOCVD). Both titanium oxide and aluminum nitride are compatible with the direct bonding process and have a thermal conductivity (kappa value) greater than that of silicon oxide. In some examples, the first bonding layer 214 may have a kappa value between 10 and 100, while silicon oxide may have a kappa value of approximately 1.

[0063] Reference Figure 1 and Figure 7 Method 100 includes block 110, wherein a second bonding layer 216 is deposited on a second substrate 220. As will be described in detail below, method 100 includes bonding the second substrate 220 to the device wafer 200 to provide mechanical strength while thinning and partially removing the first substrate 202. To achieve this, the second bonding layer 216 is deposited on the second substrate 220 to interface with the first bonding layer 214 during a direct bonding process. In some embodiments, the second substrate 220 comprises: an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium inphosphide, and / or gallium indium arsenic phosphide; or combinations thereof. In one embodiment, the second substrate 220 may comprise silicon. In alternative embodiments, the second substrate 220 may comprise glass. The bonding of the second substrate 220 allows the device wafer 200 to be flipped for subsequent processing, while the second substrate 220 provides mechanical strength to the device wafer 200. For these reasons, the second substrate 220 may also be referred to as a carrier substrate or carrier wafer. In some examples, the second substrate 220 may have a thickness between approximately 750 μm and 800 μm.

[0064] The second bonding layer 216 is configured to be directly bonded to the first bonding layer 214 in subsequent processes. Similar to the first bonding layer 214, the second bonding layer 216 is located in the heat conduction path to dissipate heat from the component layer 204. For these reasons, it is desirable to form the second bonding layer 216 with a material that is compatible with the direct bonding process and does not hinder heat conduction. In some embodiments, the second bonding layer 216 includes a metal-like material (such as titanium oxide or aluminum nitride) and may have a thickness between approximately 50 nm and 25 μm. In one embodiment, the second bonding layer 216 includes titanium oxide. In some embodiments, the second bonding layer 216 is deposited using atomic layer deposition, chemical vapor deposition, or metal organic chemical vapor deposition. Both titanium oxide and aluminum nitride are compatible with the direct bonding process and have a thermal conductivity (kappa value) greater than that of silicon oxide. In some examples, the second bonding layer 216 may have a kappa value between 10 and 100, while the kappa value of silicon oxide is approximately 1.

[0065] Reference Figure 1 、 Figure 8 ,and Figure 9 , the method 100 includes block 112, wherein the device wafer 200 is bonded to the second substrate 220 by bonding the first bonding layer 214 to the second bonding layer 216. To bond the first bonding layer 214 and the second bonding layer 216, the surfaces of the first bonding layer 214 and the second bonding layer 216 are first activated by plasma treatment. In some embodiments, the plasma treatment may include using a plasma of oxygen (O2), nitrogen (N2), or a combination thereof. After the plasma activation, the first bonding layer 214 and the second bonding layer 216 are pressed together, as shown in FIG. Figure 8 As shown. Then, an annealing process is performed to form a covalent bond at the interface between the first bonding layer 214 and the second bonding layer 216. Plasma treatment activation helps to reduce the annealing temperature in the annealing process, thereby reducing thermal damage to the device wafer 200. After the operation of box 112, the first bonding layer 214 and the second bonding layer 216 can be collectively referred to as a bonding layer 218. Figure 9 As shown, the device wafer 200 and the second substrate 220 bonded thereto are flip-chip mounted to facilitate subsequent process steps.

[0066] Reference Figure 1 and Figure 10Method 100 includes block 114, in which a backside interconnect structure 230 is formed. Operations in block 114 may include thinning the first substrate 202, forming backside contacts, and forming the backside interconnect structure 230. Thinning the first substrate 202 may include a mechanical grinding process and a chemical mechanical polishing (CMP) process. During the mechanical grinding process, a substantial amount of substrate material may initially be removed from the first substrate 202. Thereafter, a chemical mechanical polishing process is performed to further thin the first substrate 202 and provide a planar backside surface. Depending on the presence of self-aligned features, backside contact openings may be formed on the backside surface using photolithography techniques or selective etching to expose source features, drain features, or gate structures. A dielectric liner and barrier layer may be deposited over the backside contact openings. Depending on whether the contacts are coupled to source / drain features, a silicide layer may be formed in the contact openings to border the source / drain features. A metal fill layer is then deposited over the contact openings to form the backside contacts. The dielectric liner may include silicon nitride. The barrier layer in the backside contact may include titanium nitride or tantalum nitride. The metal fill layer may include tungsten, cobalt, molybdenum, ruthenium, copper, or aluminum. The silicide component may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0067] Then, a backside interconnect structure 230 is formed to couple to the backside contacts. Figure 10The backside interconnect structure 230 shown may include 3 to 12 metal layers. Each metal layer includes a conductive line embedded in an intermetallic dielectric layer. The backside interconnect structure 230 also includes contact vias that vertically interconnect conductive lines in different metal layers. The intermetallic dielectric layer may include materials such as tetraethoxysilane oxide, undoped silicate glass, or doped silicon oxide, boron-doped phosphosilicate glass, fused silica glass, phosphosilicate glass, boron-doped silicate glass, silicon oxycarbide, and / or other suitable dielectric materials. The conductive lines and contact vias may include aluminum, copper, titanium nitride, tungsten, or ruthenium.

[0068] A redistribution layer (RDL) 240 may be formed on the backside interconnect structure 230. The RDL 240 is an additional metal layer that redirects signals from the contact pads of the backside interconnect structure 230 to other locations for better access. Since the RDL structure is typically located on top of the die and is formed at the end of the back-end process, the RDL structure typically serves as a test pad or probe pad, such as a wafer acceptance test (WAT) pad. By probing the wafer acceptance test pad, process control monitoring data is generated to improve yield and reduce defects. In addition to the wafer acceptance test pad, the RDL 240 also includes contact pads that are configured to couple to bump components.

[0069] Reference Figure 1 and Figures 11 to 14 , method 100 includes block 116, where subsequent processing is performed. Such subsequent processing may include testing (shown in FIG. Figure 11 ), forming a redistribution layer 240 and a bump component 250 (shown in Figure 12 Middle), thin carrier substrate (shown in Figure 13 ), and single crystallization (shown in Figure 14 (in Chinese). Figure 11 , the component wafer 200 is attached to the wafer chuck 1000. In some embodiments, the wafer chuck 1000 is a wafer acceptance test chuck. In order to perform a wafer acceptance test, the probe 1200 can contact the wafer acceptance test pad on the component wafer 200. In some embodiments, the probe 1200 is one of many probes in a probe card. By having physical and electrical contact between the probe 1200 and the wafer acceptance test pad, the electronic test system can perform automated integrated circuit testing. The probe 1200 can also be referred to as an electronic connector or pin. After testing the component wafer 200, a bump component 250 is formed on the component wafer 200, such as Figure 12 shown.

[0070] The redistribution layer 240 includes a passivation layer covering the top redistribution metal layer. To form the bump component 250, an opening is formed in the passivation layer to expose a portion of the top redistribution metal layer. An under bump metallization (UBM) component is formed on the exposed portion of the top redistribution metal layer. Then, the bump component 250 is formed on the UBM component. The redistribution metal layer may include copper. The UBM component may include a barrier layer and a seed layer. The barrier layer may include titanium nitride or tantalum nitride. The seed layer may include copper, silver (Ag), chromium (Cr), tin (Sn), gold (Au), or a combination thereof. After forming the UBM component, the bump component 250 is formed on the UBM component. The bump component 250 may include lead tin, indium antimonide, tin, silver, copper, or a combination thereof.

[0071] After forming the bump features 250, the second substrate 220 is thinned using mechanical grinding, chemical mechanical polishing, or a combination thereof. In some examples, the second substrate 220 may be thinned to between about 40 μm and 760 μm, such as Figure 13 When no TSVs are formed through the second substrate 220, the second substrate 220 may only be slightly thinned to provide mechanical support and act as a heat sink. When TSVs are formed through the second substrate 220 for packaging or die stacking, the second substrate 220 may be thinned to a thickness between 40 μm and 60 μm.

[0072] After thinning the second substrate 220, the device wafer 200 may undergo a single crystallization process, wherein the device die 400 may be single crystallized. In some embodiments, single crystallizing the device die may include a laser dicing process. The device die 400 is shown in FIG. Figure 14 In. The component die 400 includes a plurality of bump components 250 to interface with the package structure or the package substrate. The backside interconnect structure 230 is disposed on the bump component 250. The component layer 204 is disposed on the backside interconnect structure 230. The transistors in the component layer 204 are electrically coupled to the front side interconnect structure 208 by means of the contact layer 206. Both the front side interconnect structure 208 and the backside interconnect structure 230 provide signal routing for the transistors in the component layer 204. An etch stop layer 210 is deposited on the front side interconnect structure 208. A compression film 212 is disposed on the etch stop layer 210. A bonding layer 218 is disposed on the compression film 212. The second substrate 220 is disposed on the bonding layer 218 to provide mechanical strength to the component die 400. The component die 400 can be adhered to the package structure or the package substrate by means of the bump component 250. In Figure 14In some embodiments, device die 400 and another device die 450 are attached to an interposer 500, which is attached to a package substrate 600. In the embodiment shown, bump features 250 are surrounded by underfill, while device die 400, device die 450, and interposer 500 are surrounded by molding material.

[0073] In one exemplary aspect, the present disclosure is directed to a semiconductor device comprising: a substrate; a bonding layer on the substrate; a compressive dielectric layer on the bonding layer; a first interconnect structure on the compressive dielectric layer; a component layer on the first interconnect structure; and a second interconnect structure on the component layer. The bonding layer has a kappa value between 10 and 100.

[0074] In some embodiments, the bonding layer comprises titanium oxide or aluminum nitride. In some embodiments, the compressive dielectric layer comprises silicon nitride. In some embodiments, the semiconductor device further comprises an etch stop layer between the compressive dielectric layer and the first interconnect structure, wherein the etch stop layer comprises silicon carbonitride. In some embodiments, the bonding layer comprises a thickness between 50 nm and 25 μm. In some embodiments, the compressive dielectric layer comprises a thickness between 50 nm and 100 nm.

[0075] In another exemplary aspect, the present disclosure provides a method for forming a semiconductor device. The method includes depositing a compressive dielectric layer on a device wafer, the device wafer comprising a first substrate, a device layer on the first substrate, and a first interconnect structure on the device layer; depositing a first bonding layer on the compressive dielectric layer; depositing a second bonding layer on a second substrate; and bonding the second substrate to the device wafer by bonding the first bonding layer and the second bonding layer. The first bonding layer and the second bonding layer comprise a dielectric material having a thermal conductivity greater than that of silicon oxide.

[0076] In some embodiments, the first bonding layer and the second bonding layer include titanium oxide or aluminum nitride. In some embodiments, the compressive dielectric layer includes silicon nitride. In some embodiments, each of the first bonding layer and the second bonding layer includes a thickness between 50 nm and 25 μm. In some embodiments, the compressive dielectric layer includes a thickness between 50 nm and 100 nm. In some embodiments, the compressive dielectric layer applies compressive stress to the device wafer. In some embodiments, the device layer includes a plurality of multi-gate transistors. In some embodiments, the method for forming a semiconductor device further includes depositing an etch stop layer on the device wafer before depositing the compressive dielectric layer on the device wafer, wherein after depositing the compressive dielectric layer, the etch stop layer is sandwiched between the compressive dielectric layer and the device wafer. In some embodiments, the etch stop layer includes silicon carbonitride. In some embodiments, the method for forming a semiconductor device further includes: thinning the first substrate after bonding the second substrate to the device wafer; and forming a second interconnect structure on the device layer.

[0077] In another exemplary aspect, the present disclosure provides a method for forming a semiconductor device. The method includes forming a device layer on a first substrate; forming a front-side interconnect structure on the device layer; depositing a compressive dielectric layer on the front-side interconnect structure; depositing a first bonding layer on the compressive dielectric layer; depositing a second bonding layer on a second substrate; bonding the second substrate to the first substrate by bonding the first bonding layer and the second bonding layer; thinning the first substrate; and, after thinning the first substrate, forming a back-side interconnect structure on the device layer. The first bonding layer and the second bonding layer include titanium oxide or aluminum nitride.

[0078] In some embodiments, the compressive dielectric layer comprises silicon nitride. In some embodiments, the compressive dielectric layer has a thickness greater than a thickness of the first bonding layer or a thickness of the second bonding layer. In some embodiments, the method of forming a semiconductor device further comprises depositing an etch stop layer on the front-side interconnect structure before depositing the compressive dielectric layer on the front-side interconnect structure, wherein the etch stop layer comprises silicon carbonitride.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a substrate; a bonding layer on the substrate; a compressive dielectric layer on the bonding layer; a first interconnect structure on the compressive dielectric layer; a device layer on the first interconnect structure; and a second interconnect structure on the device layer, The kappa value of the bonding layer is between 10 and 100. 2 . The semiconductor device as claimed in claim 1 , wherein the bonding layer comprises titanium oxide or aluminum nitride. The semiconductor device of claim 1 , wherein the compressive dielectric layer comprises silicon nitride.

4. The semiconductor device according to claim 1 , further comprising: an etch stop layer located between the compressive dielectric layer and the first interconnect structure, The etching stop layer includes silicon carbonitride.

5. A method for forming a semiconductor device, comprising: Depositing a compressive dielectric layer on a device wafer, the device wafer comprising a first substrate, a device layer on the first substrate, and a first interconnect structure on the device layer; depositing a first bonding layer on the compressive dielectric layer; depositing a second bonding layer on a second substrate; as well as The second substrate and the device wafer are bonded by bonding the first bonding layer and the second bonding layer. The first bonding layer and the second bonding layer include a dielectric material, and the thermal conductivity of the dielectric material is greater than that of silicon oxide. The method for forming a semiconductor device as claimed in claim 5 , wherein the compressive dielectric layer applies compressive stress to the device wafer. 7 . The method for forming a semiconductor device according to claim 5 , wherein the device layer comprises a plurality of multi-gate transistors.

8. The method for forming a semiconductor device according to claim 5, further comprising: After bonding the second substrate and the device wafer, thinning the first substrate; as well as A second interconnect structure is formed on the device layer.

9. A method for forming a semiconductor device, comprising: forming a device layer on a first substrate; forming a front-side interconnect structure on the device layer; depositing a compressive dielectric layer on the front-side interconnect structure; depositing a first bonding layer on the compressive dielectric layer; depositing a second bonding layer on a second substrate; bonding the second substrate and the first substrate by bonding the first bonding layer and the second bonding layer; thinning the first substrate; as well as After thinning the first substrate, forming a backside interconnection structure on the device layer, The first bonding layer and the second bonding layer include titanium oxide or aluminum nitride. 10 . The method for forming a semiconductor device as claimed in claim 9 , wherein a thickness of the compressive dielectric layer is greater than a thickness of the first bonding layer or a thickness of the second bonding layer.

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