Improved IGBT module structure and packaging method

Abstract

The invention provides an improved IGBT module structure and a packaging method, and belongs to the technical field, the improved IGBT module structure comprises a DBC substrate, the upper surface of the DBC substrate is provided with an IGBT chip, the IGBT chip is arranged in an inverted manner, the back surface of the IGBT chip is thinned in a laser lift-off and mechanical polishing manner, a micro-column array is arranged between the IGBT chip and the DBC substrate, the back surface of the IGBT chip is provided with copper column bumps, and the copper column bumps are arranged on the lower surface of the DBC substrate. The upper surfaces of the copper pillar bumps are provided with the encapsulation layers, and the bottom of the DBC substrate is provided with the phase change heat dissipation layer, thereby solving the problems that a conventional IGBT module is poor in heat dissipation performance and electrical performance, and is poor in interconnection reliability.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an improved IGBT module structure and packaging method. Background Art

[0002] In the field of IGBT module packaging, which belongs to the microelectronics industry, IGBT is a device made of MOSFET and bipolar transistor. Its input pole is MOSFET and its output pole is PNP transistor. It combines the advantages of these two devices. It has the advantages of low driving power and fast switching speed of MOSFET devices, and the advantages of low saturation voltage and large capacity of bipolar devices. Its frequency characteristics are between MOSFET and power transistor, and it can work normally in the frequency range of tens of KHZ.

[0003] However, existing IGBT modules have the following problems:

[0004] Heat dissipation performance bottleneck: The heat dissipation design of traditional IGBT modules cannot meet the requirements of efficient dissipation of the large amount of heat generated by the chip under high power density, which can easily cause chip overheating and affect performance and life.

[0005] Insufficient electrical performance optimization: The electrical performance of conventional packaging is limited and cannot adapt well to complex working conditions such as high voltage, high current and high frequency.

[0006] Poor interconnection reliability: Traditional interconnection methods have current crowding effects and large contact resistance, which affects power transmission efficiency and device reliability. Summary of the Invention

[0007] The embodiments of the present invention provide an improved IGBT module structure and packaging method, which solve the problems of poor heat dissipation and electrical performance and poor interconnection reliability of traditional IGBT modules.

[0008] In view of the above problems, the technical solution proposed by the present invention is:

[0009] The present invention provides an improved IGBT module structure method, including a DBC substrate, an IGBT chip is arranged on the upper surface of the DBC substrate, the IGBT chip is flip-chip arranged, the back side of the IGBT chip is thinned by laser stripping and mechanical polishing, a micro-pillar array is arranged between the IGBT chip and the DBC substrate, copper pillar bumps are arranged on the back side of the IGBT chip, a potting layer is arranged on the upper surface of the copper pillar bumps, and a phase change heat dissipation layer is arranged on the bottom of the DBC substrate.

[0010] As a preferred technical solution of the present invention, the encapsulation layer is made of silicon carbide nanowire-enhanced silicone gel material, which is obtained by plasma activation of the surface of the silicon carbide nanowires, vacuum mixing with the silicone prepolymer in proportion, and then curing in stages after encapsulation.

[0011] As a preferred technical solution of the present invention, the copper pillar bumps are provided on the surface of the IGBT chip by electroplating, bonded by ultrasonic-assisted hot pressing, and filled with a dielectric with a low dielectric constant.

[0012] As a preferred technical solution of the present invention, honeycomb grooves are etched on the top surface of the copper pillar bumps, and liquid metal is filled in the grooves to form a lateral flow-uniform layer.

[0013] 5. An improved IGBT module structure according to claim 4, characterized in that the DBC substrate has a three-layer structure, comprising, from top to bottom, an alumina ceramic, a corrugated copper layer, and a liquid-cooled copper substrate, the layers being connected by vacuum brazing, microchannels being etched on the surface of the liquid-cooled copper substrate, and a gradient dielectric constant layer being provided on the surface of the DBC substrate.

[0014] As a preferred technical solution of the present invention, the phase change heat dissipation layer is one of graphene aerogel and paraffin composite phase change material.

[0015] As a preferred technical solution of the present invention, the micropillar array is flexibly connected at the top and rigidly connected at the bottom. The bottom of the micropillar array is a copper / diamond composite, the middle is a spiral carbon nanotube bundle, and the outer side of the carbon nanotube bundle is wrapped with silicone material.

[0016] On the other hand, an improved packaging method of an IGBT module structure includes the following steps:

[0017] S1, using hydrofluoric acid gas to clean the IGBT chip, magnetron sputtering to deposit a stack of titanium, nickel, and silver on the bottom surface of the flip-chip IGBT as an electrode contact layer, and then performing atomic layer deposition to grow an insulating layer on the sidewalls of the IGBT chip;

[0018] S2, using SU-8 thick resist to form cylindrical openings, electroplating the copper pillar bumps with a copper sulfate-based solution, using femtosecond laser two-photon polymerization on the copper pillar bumps, etching a honeycomb structure on the top of the copper pillar, and filling the honeycomb grooves with liquid metal. The filling vacuum is (0.001 Pa), the temperature is controlled within the range of (45-55 ° C), and ultrasonic-assisted hot compression bonding is used for flip-chip bonding;

[0019] S3, using laser engraving to form a corrugated structure on the surface of the copper foil, 3D printing a copper substrate in a laser powder bed melting process, electrostatically spraying a SiO2 / PVDF nanocomposite slurry on the surface of the DBC substrate, and then integrating the IGBT chip and the DBC substrate by vacuum brazing;

[0020] S4, using argon to plasma activate the silicon carbide nanowires to enhance the interface bonding with the silicone, vacuum mixing the silicon carbide nanowires with the silicone prepolymer, and finally vacuum potting and curing in stages to form a three-dimensional thermal conductive network;

[0021] S5. Before brazing the IGBT chip and the DBC substrate, insert a micropillar array between them and perform ultrasonic thermocompression bonding at a frequency of 50 kHz and an amplitude of 5 μm. Finally, vacuum hot-press encapsulation is performed using a carbon fiber reinforced epoxy resin frame and the edges are coated with silicone rubber for sealing.

[0022] S6, use the power device analyzer to perform performance testing.

[0023] As a preferred technical solution of the present invention, the micro-pillar array fabrication process of step S5 is as follows:

[0024] S51, vertical alignment of carbon nanopillars induced by electric field, and copper filling at the bottom of the micropillars using pulse electroplating;

[0025] S52, a mechanical twisting process is used to twist the micropillars to form a spiral structure, and the silicone material is wrapped on the outer surface of the micropillars using vacuum impregnation, followed by gradient curing;

[0026] S53, chemical bonding is performed at the bottom of the carbon nanocolumn, Si-OC covalent bonds are formed through APTES silane coupling agent, and carbon quantum dots are added to the top organic silicon material prepolymer to enhance the interface bonding strength.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) The present invention adopts a three-layer structure of a DBC substrate and connects it through vacuum brazing, which has good electrical insulation, thermal conductivity and mechanical properties. A phase change heat dissipation layer is introduced at the bottom of the DBC substrate to improve thermal conductivity and shape stability, achieve efficient thermal management, and effectively solve the problem of low heat dissipation efficiency and difficulty in adapting to different working conditions of traditional heat dissipation structures.

[0029] (2) The present invention sets a gradient dielectric constant layer on the surface of the DBC substrate, sprays the nano-composite medium layer by layer, and realizes a dielectric constant gradient distribution by controlling the polyvinylidene fluoride content, thereby improving the electrical performance and insulation reliability of the module and solving the problems of poor dielectric performance and easy electric field concentration in the traditional homogeneous dielectric layer.

[0030] (3) The present invention sets copper pillar bumps on the surface of the IGBT chip by electroplating, etches honeycomb grooves on the top surface of the copper pillar bumps, and fills them with liquid metal to form a lateral flow-equalizing layer. By utilizing the characteristics of the honeycomb structure and liquid metal, the contact area is increased and the contact resistance is reduced, while avoiding the current crowding effect and the introduction of parasitic capacitance, thereby optimizing the electrical interconnection performance and improving the power transmission efficiency and signal integrity.

[0031] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a structural diagram of an improved IGBT module structure disclosed in the present invention;

[0033] Figure 2 This is a partial structural diagram of a DBC substrate of an improved IGBT module structure disclosed in the present invention;

[0034] Figure 3 This is a flow chart of a packaging method for an improved IGBT module structure disclosed in the present invention;

[0035] Explanation of the accompanying reference numerals: 10, DBC substrate; 101, alumina ceramic; 102, corrugated copper layer; 103, liquid-cooled copper substrate; 20, IGBT chip; 30, micropillar array; 40, potting layer; 50, copper pillar bump; 60, phase change heat dissipation layer; 70, alumina insulating layer. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0037] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0041] Example 1

[0042] Refer to the attached Figure 1-2 As shown, the present invention provides a technical solution: an improved IGBT module structure, including a DBC substrate 10, an IGBT chip 20 is arranged on the upper surface of the DBC substrate 10, and the IGBT chip 20 is flip-chip arranged. The back of the flip-chip IGBT chip 20 is laser stripped and mechanically polished to be thinned to 60-70μm, thereby reducing the chip weight and lowering the thermal resistance. The side wall is plasma-deposited with an aluminum oxide insulating layer 70. The side wall uses a plasma-deposited aluminum oxide insulating layer 70 to ensure the insulation performance between the chip and the DBC substrate 10, which helps to improve the power density and reliability of the module and provides a basis for highly integrated packaging. A micro-pillar array 30 is arranged between the IGBT chip 20 and the DBC substrate 10, a copper pillar bump 50 is arranged on the back of the IGBT chip 20, and a potting layer 40 is arranged on the upper surface of the copper pillar bump 50. A phase change heat dissipation layer 60 is arranged on the bottom of the DBC substrate 10.

[0043] The embodiment of the present invention is also implemented through the following technical solutions.

[0044] In an embodiment of the present invention, the encapsulation layer 40 is made of a silicon carbide nanowire-enhanced silicone gel material. The surface of the silicon carbide nanowires is plasma activated, vacuum-mixed with a silicone prepolymer at a ratio of 10-15wt%, and then cured in stages after encapsulation, at 80°C / 2h-120°C / 1h-160°C / 6h. The encapsulation layer 40 forms a three-dimensional thermal conductive network, improves thermal conductivity and mechanical strength, enhances chip protection and heat dissipation, and overcomes the defects of insufficient performance of traditional encapsulation materials.

[0045] In the embodiment of the present invention, the copper pillar bumps 50 are disposed on the surface of the IGBT chip 20 by electroplating, bonded by ultrasonic-assisted hot pressing, and filled with a dielectric with a low dielectric constant.

[0046] In an embodiment of the present invention, a honeycomb groove is etched on the top surface (non-functional area) of the copper pillar bump 50, and liquid metal is filled in the groove to form a lateral flow-distributing layer, thereby forming a liquid metal interconnection as a whole. After the liquid metal fills the groove, the contact area between the copper pillar and the adjacent conductive layer is significantly increased, and the contact resistance is reduced. The honeycomb structure limits the flow of liquid metal through capillary action, thereby avoiding the current crowding effect of traditional planar interconnection. The groove is only provided in the power electrode area to shield the gate signal area to prevent the liquid metal from introducing parasitic capacitance. An Al2O3 / Si3N4 composite dielectric layer (thickness 1μm, breakdown field strength>20MV / cm) is deposited on the side wall of the groove to ensure insulation between adjacent copper pillars (spacing ≥100μm).

[0047] In an embodiment of the present invention, the DBC substrate 10 has a three-layer structure, which includes, from top to bottom, an alumina ceramic 101, a corrugated copper layer 102, and a liquid-cooled copper substrate 103. The layers are connected by vacuum brazing. Microchannels are etched on the surface of the liquid-cooled copper substrate 103. When the coolant flows in the microchannels, it can fully exchange heat with the substrate surface and quickly take away the heat generated by the substrate and the chip. The alumina ceramic layer 101 has a high thermal conductivity and can quickly conduct the heat generated by the chip to the corrugated copper layer 102, and then further conduct the heat generated by the chip to the corrugated copper layer 102. The heat generated by the chip is transferred to the liquid-cooled copper substrate 103 in sequence through the micropillar array 30 and the DBC substrate 10 (alumina ceramic layer, corrugated copper layer) to the liquid-cooled copper substrate 103, and is finally carried away by the coolant. A gradient dielectric constant layer is set on the surface of the DBC substrate 10, and a nano-composite medium (silicon dioxide / PVDF mixed material, particle size 50nm) is sprayed layer by layer. The dielectric constant gradient distribution is achieved by controlling the PVDF content (0-40% with an increment of 5% per layer). As the PVDF content increases, the dielectric constant of the composite material gradually decreases.

[0048] Among them, the process steps of the gradient dielectric constant layer are:

[0049] Silica nanoparticles and polyvinylidene fluoride powder were dispersed in N-methylpyrrolidone solvent at preset ratios (0%, 10%, 20%, 30%, and 40%) and ultrasonically treated (500 W for 30 minutes) to form a homogeneous slurry. The rheometer was used to adjust the slurry to 200-500 cps (suitable for spray coating).

[0050] Using a precision electrostatic spraying system (nozzle diameter 0.3mm, spraying distance 50mm), spraying from low polyvinylidene fluoride content (0%) to high content (40%) layer by layer, each layer thickness 10μm, the specific number of layers is set according to demand, after each layer is sprayed, pre-baked at 80℃ for 5min to volatilize the solvent and initially solidify;

[0051] Hot pressing is performed at a temperature of 180°C and a pressure of 5 MPa for 30 minutes. The polyvinylidene fluoride melts and flows to fill the gaps between the silica particles, forming a dense composite layer. The interlayer interface is bound by molecular chains and hydrogen bonds to avoid delamination (interlayer bonding strength > 20 MPa).

[0052] Post-processing and performance verification: diamond slurry polishing to a surface roughness Ra < 0.1μm, an impedance analyzer (1kHz-1MHz) is used to verify the dielectric constant gradient (measured error <±5%), and the breakdown field strength test (transient method) is >150kV / mm (conventional homogeneous layer is about 100kV / mm).

[0053] In an embodiment of the present invention, the phase change heat dissipation layer 60 is one of graphene aerogel or paraffin composite phase change material. If the module operating temperature is high and long-term stable heat dissipation is required, graphene aerogel is selected. By processing a microneedle array (diameter 50μm, height 200μm, spacing 100μm) on the bottom surface of the DBC substrate 10, the bonding is enhanced by mechanical interlocking, the graphene aerogel is prefabricated into a thin sheet matching the bottom of the DBC, and nano-silver glue is sprayed on the surface of the graphene. The graphene aerogel and the DBC substrate 10 are hot-pressed and bonded at a temperature of 300°C, a pressure of 10MPa, and a time of 10min to sinter the nano-silver particles to form an interface heat conduction path. The thermal conductivity (e.g., 5-10W / m·K) and porosity of the graphene aerogel are (such as 80%-90%). If cost needs to be considered, paraffin composite phase change material is selected, and a honeycomb packaging cavity is designed at the bottom of the DBC substrate 10. The inner wall is nickel-plated (thickness 5μm) to prevent paraffin corrosion. The composition is paraffin + expanded graphite (mass ratio 8:2) + carbon nanotubes (1wt%) to improve thermal conductivity and shape stability. The paraffin is heated to 80°C (liquid) using vacuum melt infusion and injected into the honeycomb cavity under a vacuum degree of 0.01Pa. The filling rate is >99%, and the top is covered with copper foil (thickness 0.1mm). The edge is sealed by laser welding (power 200W, scanning speed 10mm / s), and a heat pipe array (diameter 3mm, spacing 10mm) is set between the DBC substrate 10 and the phase change material layer to accelerate the introduction of heat into the phase change material layer.

[0054] In an embodiment of the present invention, the micropillar array 30 is flexibly connected at the top and rigidly connected at the bottom. The bottom of the micropillar array 30 is a copper / diamond composite, and the middle is a spiral carbon nanotube bundle with a length of 100-200 μm and a spiral pitch of 50 μm. The outer side of the carbon nanotube bundle is wrapped with an organic silicon material, which is polydimethylsiloxane.

[0055] The structural design of the micropillar array combines the advantages of different materials, realizes a multi-modulus gradient design, and has good thermal conductivity, electrical conductivity, mechanical support and self-repairing properties. The structure and performance of the micropillar array are precisely controlled, providing an excellent connection effect between the chip and the DBC substrate 10. Its spiral carbon nanotube bundle and other structures have good conductivity, can provide more transmission paths for current, reduce contact resistance, improve current transmission efficiency, reduce power loss, and improve the overall electrical performance of the module.

[0056] The liquid metal honeycomb interconnect layer and the copper pillar bump 50 core conductive area are not set because the fluidity of the liquid metal may interfere with the positioning of the microcapsules, and the honeycomb structure itself has high reliability. Microcapsules are not set here to avoid microcapsules occupying the conductive area and ensure current transmission efficiency.

[0057] Considering that key components of electronic equipment and power systems need to operate stably for a long time, the self-repair function can extend the service life of components by timely repairing damage caused by thermomechanical fatigue and interface failure, so that the equipment can operate normally within the designed life cycle, or even exceed the expected life cycle, thereby improving the return on investment of the equipment. To this end, self-repairing microcapsules can be evenly mixed in the micropillar array 30. The microcapsules are set according to the size of the setting area and integrated into the micropillars. The groove width of the micropillars is 30μm, and the diameter of the self-repairing microcapsules is 29.1-29.8μm, covering the entire module surface. The microcapsules are locally densified at the junction of the chip and the DBC substrate 10 (concentration 30%) to specifically repair thermomechanical fatigue cracks. The microcapsules are triggered when the local stress is greater than 10MPa (such as when the crack extends to the microcapsule), and the epoxy resin reacts with moisture to solidify after release;

[0058] Among them, the preparation of microcapsules: bisphenol A epoxy resin (EPON 828) and carbon nanotubes are ultrasonically dispersed in acetone (power 500W, 30min) to form a homogeneous slurry (carbon nanotube content 3wt%), a latent curing agent (microencapsulated acid anhydride, particle size 1μm, content 5wt%) is added, and stirred and mixed. Toluene diisocyanate and polyether polyol (molecular weight 2000) are mixed in a 1:1 molar ratio, epoxy resin core material emulsion, polyvinyl alcohol (PVA, concentration 5%) solution is added as an emulsifier, the oil-water ratio is 1:3, the stirring rate is 1500rpm, the temperature is 60°C, the reaction is carried out for 4h, centrifugal separation (8000rpm, 10min), deionized water washing, vacuum drying at 40°C, and titanium dioxide (thickness 50nm) is vapor-deposited on the surface of the capsule to improve temperature resistance.

[0059] Example 2

[0060] Refer to the attached Figure 3 As shown, an embodiment of the present invention further provides an improved packaging method for an IGBT module structure, comprising the following steps:

[0061] S1, using hydrofluoric acid gas to clean the IGBT chip 20 (HF concentration 5%, time 3 minutes), magnetron sputtering deposits a stack of titanium, nickel, and silver on the bottom surface of the flip-chip IGBT as an electrode contact layer, and then atomic layer deposition grows a 10nm insulating layer on the sidewalls of the IGBT chip 20;

[0062] S2, using SU-8 thick resist (thickness 150 μm, exposure dose 300 mJ / cm 2 ), forming a cylindrical opening, using a copper sulfate base solution (Cu 2+ 40g / L, H2SO4 100g / L) for electroplating copper pillar bumps 50, current density 4A / dm 2The copper pillar bump 50 has a diameter of 80μm, a height of 150μm, an aspect ratio of 3:1, and a pitch of 200μm. Femtosecond laser two-photon polymerization (wavelength 515nm, pulse energy 50μJ) is used on the copper pillar bump 50 to etch a honeycomb structure (groove width 30μm, depth 50μm) on the top of the copper pillar, and liquid metal is filled in the honeycomb groove. Ultrasonic assisted hot compression bonding (temperature 250℃, pressure 20MPa, ultrasonic power 800W, time 0.5s) is used to flip the chip. Machine vision is used for positioning (±3μm), and eutectic solder Sn-Bi (melting point 138℃) assists in interface connection.

[0063] The detailed steps for creating a honeycomb structure on a copper pillar are as follows: spin-coating photoresist (SU-8, 60 μm thick) on the top of the copper pillar, defining a honeycomb pattern (50 μm side length) by UV lithography, and using a femtosecond laser whose wavelength needs to match the absorption characteristics of the copper pillar material (wavelength 515 nm, pulse energy 50 μJ, pulse frequency 50 kHz, energy density 5 J / cm 2 ) The surface of the copper pillars was ablated layer by layer to form honeycomb grooves with a depth of 50 μm and a sidewall tilt angle of 70° (to reduce reflection loss). Plasma cleaning (O2 / Ar mixed gas, power 300W) removed residues and improved liquid metal wettability (contact angle <10°);

[0064] The steps of filling and encapsulating the liquid metal in the honeycomb grooves are as follows: vacuum injection is performed in a vacuum chamber (0.001 Pa) to heat the liquid metal to 50°C (viscosity is reduced to 0.0015 Pa·s), and the grooves are precisely filled with a micro nozzle (filling rate >99%). Nitrogen is immediately introduced after filling, and a BN protective layer (thickness 2nm, thermal stability >300°C) is grown on the liquid metal surface by atomic layer deposition (ALD). The copper pillars filled with liquid metal are bonded to the DBC substrate 10 by ultrasonic assisted hot pressing (pressure 20MPa, temperature 180°C, ultrasonic power 500W) to form a low-resistance interconnection, referring to the IPC-7095 standard;

[0065] When etching copper pillar bumps, thermal damage to the copper pillars must be avoided. This can be reduced by adjusting pulse frequency, pulse width, and laser power. For example, lowering the laser pulse frequency can reduce the energy input to the copper pillars per unit time, thereby reducing the temperature rise rate of the copper pillars. For example, reducing the pulse frequency from the typical 100kHz to 50kHz or lower allows more time for the copper pillars to dissipate heat between pulses, reducing heat accumulation.

[0066] S3, using laser engraving (fiber laser, wavelength 1064nm, power 300W), a corrugated structure (Ra = 10μm, surface area increased by 40%) was formed on the surface of a 0.6mm thick copper foil, and a copper substrate (powder particle size 15-45μm, laser power 300W, scanning speed 800mm / s) was 3D printed using laser powder bed fusion (L-PBF). The microchannel width was 0.3mm, the depth was 1.2mm, and the flow channel density was 20 / cm. SiO2 / PVDF nanocomposite slurry was electrostatically sprayed on the surface of the DBC substrate 10, and then the IGBT chip 20 and the DBC substrate 10 were integrated by vacuum brazing, wherein the brazing material was AgCu28 (melting point 780℃), the brazing temperature was 800℃, and the heat preservation time was 15min. Alumina ceramic 101 was used as the middle insulating layer, and the upper and lower copper layers were welded by brazing;

[0067] S4, using argon to plasma activate the silicon carbide nanowires (power 300W, 5min) to enhance the interfacial bonding with silicone, the silicon carbide nanowires and silicone prepolymer (viscosity 5000cps) were vacuum mixed (vacuum degree ≤ 0.1Pa), and finally vacuum potted (vacuum degree 10-3Pa), and cured in stages (80℃ / 2h→120℃ / 1h→160℃ / 4h), forming a three-dimensional thermal conductive network with a thermal conductivity of 1.2W / mK and a 50% increase in mechanical strength;

[0068] S5. Before soldering the IGBT chip 20 to the DBC substrate 10, insert the micropillar array 30 between them and perform ultrasonic thermocompression bonding (pressure 15 MPa, temperature 180°C, ultrasonic power 500 W). A liquid metal honeycomb structure is used as the conductive medium. Finally, vacuum hot-press packaging (tensile strength 800 MPa) is performed using a carbon fiber reinforced epoxy resin frame at a packaging temperature of 150°C, a pressure of 10 MPa, and a time of 1 hour. The edges are then coated with a silicone rubber seal (thickness 0.5 mm).

[0069] The fabrication process of the micropillar array 30 is as follows:

[0070] S51, substrate temperature 600 ° C, C2H2 flow rate 50sccm, plasma power 300W, through the electric field induced carbon nano-micro column vertical orientation, using pulse plating (peak current density 50A / dm 2 , duty cycle 10%), the bottom of the micropillars was filled with copper, and the plating solution contained 2 wt % nanodiamond particles;

[0071] S52, the micropillars were twisted to form a spiral structure using a mechanical twisting process (rotation speed 500 rpm, tension 0.1 N), and the silicone material was wrapped on the outer surface of the micropillars using vacuum impregnation (vacuum degree 0.1 Pa), followed by gradient curing (60°C → 100°C → 150°C for 1 h each);

[0072] S53, using APTES silane coupling agent to form Si-OC covalent bonds between the copper / diamond composite and the silicone coating, can significantly enhance the bonding between the two. Adding 0.5wt% carbon quantum dots to the silicone prepolymer on top enhances the interfacial bonding strength.

[0073] S6, performance test was performed using Keysight B1505A power device analyzer.

[0074] Aging Screening: Temperature Cycling: 1000 times (JESD22-A104), power cycle (AQG324 standard);

[0075] Failure analysis: X-ray inspection (bonding void rate <1%), infrared thermal imaging (hot spot temperature difference <5°C).

[0076] It should be noted that the size and thickness of the above materials need to be adjusted according to actual needs, and since the materials change, the corresponding process parameters such as temperature and time also need to be adaptively adjusted.

[0077] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0078] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0079] In the foregoing detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that embodiments of the claimed subject matter require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the invention comprises less than all the features of any individual disclosed embodiment. The appended claims are therefore hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0080] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments herein may be implemented as electronic hardware, computer software, or a combination thereof. In order to clearly illustrate the interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps described above are generally described around their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. A skilled person may implement the described functions in an adaptable manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of this disclosure.

[0081] The steps of the methods or algorithms described in conjunction with the embodiments herein may be directly embodied as hardware, software modules executed by a processor, or a combination thereof. The software module may be located in a RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and storage medium may be located in an ASIC. The ASIC may be located in a user terminal. Of course, the processor and storage medium may also be present in a user terminal as discrete components.

[0082] For software implementation, the techniques described in this application can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described in this application. These software codes can be stored in a memory unit and executed by a processor. The memory unit can be implemented within the processor or external to the processor. In the latter case, it is communicatively coupled to the processor via various means, which are well known in the art.

[0083] The foregoing description includes examples of one or more embodiments. Of course, it is not possible to describe all possible combinations of components or methods for the purposes of describing the above embodiments, but one of ordinary skill in the art will recognize that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to encompass all such changes, modifications and variations that fall within the scope of the appended claims. Furthermore, to the extent the term "comprising" is used in the specification or claims, the term is intended to be encompassed in a manner similar to the term "including," as explained in terms of "including," used as a transitional word in the claims. Furthermore, any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or."

Claims

1. An improved IGBT module structure, characterized in that: The invention comprises a DBC substrate (10), an IGBT chip (20) is arranged on the upper surface of the DBC substrate (10), the IGBT chip (20) is flip-chip arranged, the back surface of the IGBT chip (20) is thinned by laser stripping and mechanical polishing, a micro-pillar array (30) is arranged between the IGBT chip (20) and the DBC substrate (10), a copper pillar bump (50) is arranged on the back surface of the IGBT chip (20), a potting layer (40) is arranged on the upper surface of the copper pillar bump (50), and a phase change heat dissipation layer (60) is arranged on the bottom of the DBC substrate (10).

2. The improved IGBT module structure according to claim 1, characterized in that: The encapsulation layer (40) is made of silicon carbide nanowire-enhanced organic silicon gel material, which is prepared by subjecting the surface of the silicon carbide nanowires to plasma activation treatment, vacuum mixing with organic silicon prepolymer in proportion, and then encapsulating and curing in stages.

3. The improved IGBT module structure according to claim 2, characterized in that: The copper pillar bumps (50) are arranged on the surface of the IGBT chip (20) by electroplating, bonded by ultrasonic-assisted hot pressing, and filled with a dielectric medium with a low dielectric constant.

4. The improved IGBT module structure according to claim 3, characterized in that: Honeycomb grooves are etched on the top surface of the copper column bump (50), and liquid metal is filled in the grooves to form a lateral uniform flow layer.

5. The improved IGBT module structure according to claim 4, characterized in that: The DBC substrate (10) has a three-layer structure, comprising, from top to bottom, an alumina ceramic (101), a corrugated copper layer (102), and a liquid-cooled copper substrate (103), wherein the layers are connected by vacuum brazing, microchannels are etched on the surface of the liquid-cooled copper substrate (103), and a gradient dielectric constant layer is provided on the surface of the DBC substrate (10).

6. The improved IGBT module structure according to claim 5, characterized in that: The phase-change heat dissipation layer (60) is one of graphene aerogel and paraffin composite phase-change material.

7. The improved IGBT module structure according to claim 6, characterized in that: The micro-pillar array (30) is flexibly connected at the top and rigidly connected at the bottom. The bottom of the micro-pillar array (30) is a copper / diamond composite, the middle is a spiral carbon nanotube bundle, and the outer side of the carbon nanotube bundle is wrapped with organic silicon material.

8. A packaging method for an improved IGBT module structure, applied to an improved IGBT module structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1, using hydrofluoric acid gas to clean the IGBT chip (20), magnetron sputtering to deposit a stack of titanium, nickel and silver on the bottom surface of the flip-chip IGBT as an electrode contact layer, and then performing atomic layer deposition on the sidewall of the IGBT chip (20) to generate an insulating layer; S2, using SU-8 thick resin to form a cylindrical opening by photolithography, using copper sulfate base liquid to electroplate the copper pillar bump (50), using femtosecond laser two-photon polymerization on the copper pillar bump (50), etching a honeycomb structure on the top of the copper pillar, filling the honeycomb groove with liquid metal, and using ultrasound-assisted hot pressing to bond the flip chip; S3, using laser engraving to form a corrugated structure on the surface, melting a 3D-printed copper substrate in a laser powder bed, electrostatically spraying a SiO2 / PVDF nanocomposite slurry on the surface of the DBC substrate (10), and then integrating the IGBT chip (20) and the DBC substrate (10) by vacuum brazing; S4, using argon to plasma activate the silicon carbide nanowires to enhance the interface bonding with the silicone, vacuum mixing the silicon carbide nanowires with the silicone prepolymer, and finally vacuum potting and curing in stages to form a three-dimensional thermal conductive network; S5, before soldering the IGBT chip (20) and the DBC substrate (10), inserting a micro-pillar array (30) between them, ultrasonic hot pressing bonding, and finally, using a carbon fiber reinforced epoxy resin frame for vacuum hot pressing packaging, and coating the edges with silicone rubber for sealing; S6, use the power device analyzer to perform performance testing.

9. The packaging method of an improved IGBT module structure according to claim 8, characterized in that: The process flow of manufacturing the micro-pillar array (30) in step S5 is as follows: S51, vertical alignment of carbon nanopillars induced by electric field, and copper filling at the bottom of the micropillars using pulse electroplating; S52, a mechanical twisting process is used to twist the micropillars to form a spiral structure, and the silicone material is wrapped on the outer surface of the micropillars using vacuum impregnation, followed by gradient curing; S53, chemical bonding is performed at the bottom of the carbon nanocolumn, Si-OC covalent bonds are formed through APTES silane coupling agent, and carbon quantum dots are added to the top organic silicon material prepolymer to enhance the interface bonding strength.

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