An improved IGBT module structure and packaging method

Abstract

This invention provides an improved IGBT module structure and packaging method, belonging to the technical field. It includes a DBC substrate, with an IGBT chip disposed on the upper surface of the DBC substrate. The IGBT chip is flip-chip mounted, and the back side of the IGBT chip is thinned by laser lift-off and mechanical polishing. A micropillar array is disposed between the IGBT chip and the DBC substrate. Copper pillar bumps are disposed on the back side of the IGBT chip, and a potting layer is disposed on the upper surface of the copper pillar bumps. A phase-change heat dissipation layer is disposed on the bottom of the DBC substrate. This invention solves the problems of poor heat dissipation and electrical performance, and poor interconnect reliability of traditional IGBT modules.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and more specifically, relates to an improved IGBT module structure and packaging method. Background Technology

[0002] In the field of IGBT module packaging, which belongs to the microelectronics industry, IGBT is a device composed of MOSFET and bipolar transistor. Its input electrode is MOSFET and its output electrode is PNP transistor. It combines the advantages of these two devices, having the advantages of low drive power and fast switching speed of MOSFET devices, and the advantages of low saturation voltage and large capacitance of bipolar devices. Its frequency characteristics are between those of MOSFET and power transistor, and it can operate normally in the frequency range of tens of kHz.

[0003] However, existing IGBT modules have the following problems:

[0004] Heat dissipation bottleneck: The heat dissipation design of traditional IGBT modules is difficult to meet the efficient dissipation of the large amount of heat generated by the chip under high power density, which can easily lead to chip overheating and affect performance and lifespan.

[0005] Insufficient electrical performance optimization: Conventional packaging offers limited improvement in electrical performance and cannot adequately adapt to complex operating conditions such as high voltage, high current, and high frequency.

[0006] Poor interconnect reliability: Traditional interconnection methods suffer from current congestion and high contact resistance, which affects power transmission efficiency and device reliability. Summary of the Invention

[0007] This invention provides an improved IGBT module structure and packaging method, which solves the problems of poor heat dissipation and electrical performance, and poor interconnection reliability of traditional IGBT modules.

[0008] In view of the above problems, the technical solution proposed by the present invention is as follows:

[0009] This invention provides an improved IGBT module structure, including a DBC substrate. An IGBT chip is disposed on the upper surface of the DBC substrate. The IGBT chip is flip-chip disposed. The back side of the IGBT chip is thinned by laser lift-off and mechanical polishing. A micropillar array is disposed between the IGBT chip and the DBC substrate. Copper pillar bumps are disposed on the back side of the IGBT chip. An encapsulation layer is disposed on the upper surface of the copper pillar bumps. A phase change heat dissipation layer is disposed on the bottom of the DBC substrate.

[0010] As a preferred embodiment of the present invention, the potting layer is a silicon carbide nanowire-reinforced organosilicon gel material. The silicon carbide nanowires are plasma activated, mixed with organosilicon prepolymer in a vacuum according to a certain ratio, and then potted and cured in stages.

[0011] As a preferred embodiment of the present invention, the copper pillar bumps are set on the surface of the IGBT chip by electroplating, bonded by ultrasonic-assisted hot pressing, and filled with a low dielectric constant medium.

[0012] As a preferred embodiment of the present invention, the top surface of the copper pillar protrusion is etched with honeycomb-shaped grooves, and liquid metal is filled in the grooves to form a transverse uniform flow layer.

[0013] As a preferred embodiment of the present invention, the DBC substrate has a three-layer structure, comprising, from top to bottom, an alumina ceramic, a corrugated copper layer, and a liquid-cooled copper substrate. The layers are connected by vacuum brazing. Microchannels are etched on the surface of the liquid-cooled copper substrate, and a gradient dielectric constant layer is disposed on the surface of the DBC substrate.

[0014] As a preferred embodiment of the present invention, the phase change heat dissipation layer is one of graphene aerogel or paraffin composite phase change material.

[0015] As a preferred embodiment of the present invention, the micropillar array is configured with a flexible top connection and a rigid bottom connection. The bottom of the micropillar array is a copper / diamond composite, the middle part is a spiral carbon nanotube bundle, and the outer side of the carbon nanotube bundle is wrapped with an organosilicon material.

[0016] On the other hand, an improved packaging method for an IGBT module structure includes the following steps:

[0017] S1, the IGBT chip is cleaned with hydrofluoric acid gas, and a stack of titanium, nickel and silver is deposited by magnetron sputtering on the bottom surface of the IGBT in the flip state as an electrode contact layer. Then, an insulating layer is grown by atomic layer deposition on the sidewall of the IGBT chip.

[0018] S2, a cylindrical opening is formed using photoresist, copper pillar bumps are electroplated using copper sulfate-based solution, femtosecond laser two-photon polymerization is used on the copper pillar bumps, a honeycomb structure is etched on the top of the copper pillar, and liquid metal is filled in the honeycomb trenches with a vacuum degree of 0.001 Pa and a temperature control range of 45-55℃. Ultrasonic-assisted thermocompression bonding of flip chips is used.

[0019] S3, using laser engraving to form a corrugated structure on the surface of copper foil, 3D printing a copper substrate by laser powder bed melting, using SiO2 / PVDF nanocomposite slurry to electrostatically spray on the surface of the DBC substrate, and then integrating the IGBT chip and the DBC substrate by vacuum brazing.

[0020] S4. Argon gas is used to plasma activate silicon carbide nanowires to enhance the interfacial bonding with organosilicon. Silicon carbide nanowires and organosilicon prepolymer are vacuum mixed and then vacuum-encapsulated for staged curing to form a three-dimensional thermally conductive network.

[0021] S5. Before the IGBT chip is brazed to the DBC substrate, a micropillar array is inserted between them, and ultrasonic hot-press bonding is performed at a frequency of 50kHz and an amplitude of 5μm. Finally, a carbon fiber reinforced epoxy resin frame is used for vacuum hot-press encapsulation, and the edges are coated with silicone rubber for sealing.

[0022] S6 uses a power device analyzer to perform performance testing.

[0023] As a preferred embodiment of the present invention, the fabrication process of the micropillar array in step S5 is as follows:

[0024] S51, carbon nanopillars are oriented vertically by an electric field, and copper is filled at the bottom of the micropillars by pulse electroplating;

[0025] S52 uses a mechanical stranding process to twist the micropillars to form a spiral structure, uses vacuum impregnation to wrap the outer surface of the micropillars with organosilicon material, and then performs gradient curing.

[0026] S53 involves chemical bonding at the bottom of carbon nanopillars, forming Si-OC covalent bonds through APTES silane coupling agent, and adding carbon quantum dots to the top organosilicon prepolymer to enhance interfacial bonding.

[0027] Compared with the prior art, the beneficial effects of the present invention are:

[0028] (1) The present invention uses a three-layer structure of DBC substrate and connects them by vacuum brazing. It has good electrical insulation, thermal conductivity and mechanical properties. A phase change heat dissipation layer is introduced at the bottom of the DBC substrate to improve thermal conductivity and shape stability, achieve efficient thermal management and effectively solve the problems of low heat dissipation efficiency and difficulty in adapting to different working conditions of traditional heat dissipation structures.

[0029] (2) This invention improves the electrical performance and insulation reliability of the module by setting a gradient dielectric constant layer on the surface of the DBC substrate, spraying nanocomposite dielectric layer by layer, and controlling the polyvinylidene fluoride content to achieve a gradient distribution of dielectric constant. This solves the problems of poor dielectric performance and easy electric field concentration in traditional homogeneous dielectric layers.

[0030] (3) The present invention sets copper pillar bumps on the surface of IGBT chip by electroplating, and etches honeycomb-shaped grooves on the top surface of the copper pillar bumps, and fills them with liquid metal to form a transverse current equalization layer. By utilizing the characteristics of honeycomb structure and liquid metal, the contact area is increased and the contact resistance is reduced. At the same time, the current crowding effect and parasitic capacitance are avoided, the electrical interconnection performance is optimized, and the power transmission efficiency and signal integrity are improved.

[0031] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of an improved IGBT module structure disclosed in this invention;

[0033] Figure 2 This is a partial structural schematic diagram of a DBC substrate for an improved IGBT module structure disclosed in this invention;

[0034] Figure 3 This is a flowchart illustrating an improved IGBT module packaging method disclosed in this invention.

[0035] Explanation of reference numerals in the attached figures: 10, DBC substrate; 101, alumina ceramic; 102, corrugated copper layer; 103, liquid-cooled copper substrate; 20, IGBT chip; 30, micropillar array; 40, potting layer; 50, copper pillar bump; 60, phase change heat dissipation layer; 70, alumina insulating layer. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0038] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0039] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] Example 1

[0042] See attached document Figure 1-2 As shown, the present invention provides a technical solution: an improved IGBT module structure, including a DBC substrate 10, an IGBT chip 20 disposed on the upper surface of the DBC substrate 10, the IGBT chip 20 being flip-chip disposed, the back side of the flip-chip IGBT chip 20 being thinned to 60-70μm by laser peeling and mechanical polishing to reduce chip weight and thermal resistance, its sidewalls being protected by plasma-deposited alumina insulating layer 70, the sidewalls using plasma-deposited alumina insulating layer 70 to ensure the insulation performance between the chip and the DBC substrate 10, which helps to improve the power density and reliability of the module, and provides a basis for highly integrated packaging. A micropillar array 30 is disposed between the IGBT chip 20 and the DBC substrate 10, copper pillar bumps 50 are disposed on the back side of the IGBT chip 20, a potting layer 40 is disposed on the upper surface of the copper pillar bumps 50, and a phase change heat dissipation layer 60 is disposed on the bottom of the DBC substrate 10.

[0043] The embodiments of the present invention are also implemented through the following technical solutions.

[0044] In an embodiment of the present invention, the potting layer 40 is a silicon carbide nanowire-reinforced organosilicon gel material. The silicon carbide nanowires are plasma activated and then vacuum-mixed with organosilicon prepolymer at a ratio of 10-15 wt%. After potting, the mixture is cured in stages at 80°C / 2h-120°C / 1h-160°C / 6h. The potting layer 40 forms a three-dimensional thermally conductive network, which improves thermal conductivity and mechanical strength, enhances chip protection and heat dissipation, and overcomes the shortcomings of traditional potting materials.

[0045] In an embodiment of the present invention, copper pillar bumps 50 are set on the surface of IGBT chip 20 by electroplating, bonded by ultrasonic-assisted hot pressing, and filled with a low dielectric constant medium.

[0046] In an embodiment of the present invention, honeycomb trenches are etched on the top surface (non-functional area) of the copper pillar bump 50. Liquid metal is filled in the trenches to form a lateral flow equalization layer, forming a liquid metal interconnect. After the liquid metal fills the trenches, the contact area between the copper pillars and the adjacent conductive layers is significantly increased, and the contact resistance is reduced. The honeycomb structure restricts the flow of liquid metal through capillary action, avoiding the current congestion effect of traditional planar interconnects. The trenches are only set in the power electrode area, shielding the gate signal area and preventing the liquid metal from introducing parasitic capacitance. An Al2O3 / Si3N4 composite dielectric layer (thickness 1μm, breakdown field strength >20MV / cm) is deposited on the trench sidewalls to ensure insulation between adjacent copper pillars (spacing ≥100μm).

[0047] In an embodiment of the present invention, the DBC substrate 10 has a three-layer structure, comprising, from top to bottom, an alumina ceramic layer 101, a corrugated copper layer 102, and a liquid-cooled copper substrate 103. The layers are connected by vacuum brazing. Microchannels are etched on the surface of the liquid-cooled copper substrate 103. When the coolant flows within the microchannels, it can fully exchange heat with the substrate surface, quickly removing the heat generated by the substrate and chip. The alumina ceramic layer 101 has high thermal conductivity, enabling it to rapidly conduct the heat generated by the chip to the corrugated copper layer 102, and then further... The heat generated by the chip is transferred sequentially through the micropillar array 30 and the DBC substrate 10 (alumina ceramic layer and corrugated copper layer) to the liquid-cooled copper substrate 103, and is finally carried away by the coolant. A gradient dielectric constant layer is set on the surface of the DBC substrate 10, and a nanocomposite medium (silica / PVDF mixed material with a particle size of 50nm) is sprayed layer by layer. The gradient dielectric constant distribution is achieved by controlling the PVDF content (0-40% increasing by 5% per layer). As the PVDF content increases, the dielectric constant of the composite material gradually decreases.

[0048] The process steps for the gradient dielectric constant layer are as follows:

[0049] Silica nanoparticles and polyvinylidene fluoride powder were dispersed in N-methylpyrrolidone solvent at a preset ratio (0%, 10%, 20%, 30%, 40%) and ultrasonically treated (500W, 30min) to form a homogeneous slurry. The slurry was then adjusted to 200-500cps using a rheometer (suitable for spraying processes).

[0050] A precision electrostatic spraying system (nozzle diameter 0.3mm, spraying distance 50mm) is used to spray layers from low polyvinylidene fluoride content (0%) to high content (40%), with each layer being 10μm thick. The specific number of layers is set according to the requirements. After each layer is sprayed, it is pre-baked at 80℃ for 5 minutes to evaporate the solvent and pre-cur it.

[0051] Hot pressing is performed at 180℃, 5MPa, and 30min. Polyvinylidene fluoride melts and flows to fill the gaps between silica particles, forming a dense composite layer. The interlayer interface is bonded by molecular chain entanglement and hydrogen bonding to avoid delamination (interlayer bonding strength >20MPa).

[0052] Post-processing and performance verification: Polish with diamond polishing slurry until surface roughness Ra < 0.1 μm. Use an impedance analyzer (1 kHz - 1 MHz) to verify the dielectric constant gradient (measured error < ± 5%). Breakdown field strength test (transient method): > 150 kV / mm (approximately 100 kV / mm for traditional homogeneous layers).

[0053] In embodiments of the present invention, the phase change heat dissipation layer 60 is one of graphene aerogel or paraffin composite phase change material. If the module operates at a high temperature and requires long-term stable heat dissipation, graphene aerogel is selected. A microneedle array (50 μm diameter, 200 μm height, 100 μm spacing) is fabricated on the bottom surface of the DBC substrate 10. Through mechanical interlocking to enhance bonding, the graphene aerogel is pre-formed into a thin sheet matching the bottom of the DBC. Nano-silver paste is sprayed onto the surface of the graphene. The graphene aerogel and the DBC substrate 10 are then hot-pressed together at 300°C, 10 MPa, and 10 min to sinter the nano-silver particles, forming an interfacial thermal conductivity pathway. The thermal conductivity of the graphene aerogel (e.g., 5-10) is achieved. For the W / m·K) and porosity (e.g., 80%-90%), if cost is a consideration, paraffin composite phase change material is selected. A honeycomb encapsulation cavity is designed at the bottom of the DBC substrate 10, with the inner wall plated with nickel (5μm thick) to prevent paraffin corrosion. The composition is paraffin + expanded graphite (mass ratio 8:2) + carbon nanotubes (1wt%), which improves thermal conductivity and shape stability. The paraffin is heated to 80℃ (liquid state) using vacuum melting infusion and injected into the honeycomb cavity under a vacuum of 0.01Pa, with a filling rate >99%. The top is covered with copper foil (0.1mm thick), and the edges are sealed by laser welding (power 200W, scanning speed 10mm / s). A heat pipe array (3mm diameter, 10mm spacing) is set between the DBC substrate 10 and the phase change material layer to accelerate heat transfer to the phase change material layer.

[0054] In an embodiment of the present invention, the micropillar array 30 is configured with a flexible top connection and a rigid bottom connection. The bottom of the micropillar array 30 is a copper / diamond composite, and the middle part is a helical carbon nanotube bundle with a length of 100-200 μm and a helical pitch of 50 μm. The outer side of the carbon nanotube bundle is wrapped with an organosilicon material, namely polydimethylsiloxane.

[0055] The micropillar array's structural design combines the advantages of different materials, achieving a multimodal gradient design. It possesses excellent thermal conductivity, electrical conductivity, mechanical support, and self-healing properties. Precise control of the micropillar array's structure and performance provides excellent connection between the chip and the DBC substrate 10. Its spiral carbon nanotube bundles and other structures have good electrical conductivity, providing more transmission paths for current, reducing contact resistance, improving current transmission efficiency, reducing power loss, and enhancing the overall electrical performance of the module.

[0056] The liquid metal honeycomb interconnect layer and the copper pillar bump 50 core conductive area are not set because the fluidity of the liquid metal may interfere with the positioning of the microcapsules, and the honeycomb structure itself has high reliability. Therefore, the microcapsules are not set here to avoid the microcapsules occupying the conductive area and to ensure current transmission efficiency.

[0057] Considering that critical components of electronic devices and power systems need to operate stably for extended periods, self-healing functions can extend the service life of components by promptly repairing damage caused by thermomechanical fatigue and interface failures. This allows the equipment to operate normally within its designed lifespan, or even beyond its expected lifespan, thereby improving the return on investment. To this end, self-healing microcapsules can be uniformly mixed into the micropillar array 30. The microcapsules are set according to the size of the set area and integrated into the micropillars. The groove width of the micropillars is 30μm, and the diameter of the self-healing microcapsules is 29.1-29.8μm, covering the entire module surface. Microcapsules (concentration 30%) are locally denser at the junction of the chip and the DBC substrate 10 to specifically repair thermomechanical fatigue cracks. The microcapsules are triggered when the local stress is >10MPa (such as when the crack extends to the microcapsule), and the epoxy resin is released and then reacts with moisture to cure.

[0058] The microcapsule preparation involved ultrasonically dispersing bisphenol A type epoxy resin (EPON 828) and carbon nanotubes in acetone (500W, 30min) to form a homogeneous slurry (3wt% carbon nanotube content). A latent curing agent (microencapsulated acid anhydride, 1μm particle size, 5wt% content) was added and stirred. Toluene diisocyanate and polyether polyol (molecular weight 2000) were mixed at a 1:1 molar ratio. An epoxy resin core emulsion was added, and polyvinyl alcohol (PVA, 5% concentration) solution was used as an emulsifier. The oil-to-water ratio was 1:3. The stirring speed was 1500rpm, the temperature was 60℃, and the reaction was carried out for 4h. The mixture was then centrifuged (8000rpm, 10min), washed with deionized water, and vacuum dried at 40℃. Titanium dioxide (50nm thickness) was vapor-deposited on the surface of the capsules to improve their temperature resistance.

[0059] Example 2

[0060] See attached document Figure 3 As shown in the figure, an improved packaging method for an IGBT module structure is provided in another embodiment of the present invention, which includes the following steps:

[0061] S1, IGBT chip 20 is cleaned with hydrofluoric acid gas (HF concentration 5%, time 3min), and a stack of titanium, nickel and silver is deposited by magnetron sputtering on the bottom surface of the flip-chip IGBT as an electrode contact layer. Then, an atomic layer deposition is performed on the sidewall of IGBT chip 20 to grow a 10nm insulating layer.

[0062] S2, using photoresist (150μm thickness, 300mJ / cm² exposure dose), a cylindrical opening is formed. Copper pillar bumps 50 are electroplated using copper sulfate-based solution (Cu²⁺ 40g / L, H₂SO₄ 100g / L), with a current density of 4A / dm². The copper pillar bumps 50 have a diameter of 80μm, a height of 150μm, an aspect ratio of 3:1, and a spacing of 200μm. Femtosecond laser two-photon polymerization (wavelength 515nm, pulse energy 50μJ) is used on the copper pillar bumps 50 to etch a honeycomb structure (groove width 30μm, depth 50μm) on the top of the copper pillars. Liquid metal is then filled into the honeycomb trenches. Ultrasonic-assisted thermocompression bonding (temperature 250℃, pressure 20MPa, ultrasonic power 800W, time 0.5s) is used to flip-chip the chip. Machine vision is used for positioning (±3μm). Eutectic solder Sn-Bi (melting point 138℃) is used to assist in interface connection.

[0063] The detailed steps for processing the honeycomb structure on the copper pillars are as follows: spin-coating photoresist (SU-8, 60μm thickness) on the top of the copper pillars; defining the honeycomb pattern (50μm side length) using ultraviolet lithography; using a femtosecond laser, the wavelength of which needs to match the absorption characteristics of the copper pillar material (wavelength 515nm, pulse energy 50μJ, pulse frequency 50kHz, energy density 5J / cm²) to ablate the surface of the copper pillar layer by layer, forming honeycomb trenches with a depth of 50μm and a sidewall inclination angle of 70° (to reduce reflection loss); and plasma cleaning (O2 / Ar mixed gas, power 300W) to remove residues and improve the wettability of the liquid metal (contact angle <10°).

[0064] The steps for filling and encapsulating liquid metal in the honeycomb trenches are as follows: Vacuum injection: The liquid metal is heated to 50°C in a vacuum chamber (0.001Pa) (viscosity decreases to 0.0015Pa·s), and the trenches are precisely filled through a micro-nozzle (fill rate >99%). Nitrogen gas is immediately introduced after filling, and a BN protective layer (thickness 2nm, thermal stability >300°C) is grown on the surface of the liquid metal by atomic layer deposition (ALD). The copper pillars filled with liquid metal are bonded to the DBC substrate 10 by ultrasonic-assisted thermo-press bonding (pressure 20MPa, temperature 180°C, ultrasonic power 500W) to form a low-resistance interconnect, referring to the IPC-7095 standard.

[0065] When etching bumps on copper pillars, it is necessary to avoid thermal damage to the copper pillars. This can be achieved by adjusting the pulse frequency, pulse width, and laser power. For example, reducing the laser pulse frequency decreases the energy input to the copper pillar per unit time, thereby slowing down the rate of temperature rise. For instance, reducing the pulse frequency from the common 100kHz to 50kHz or lower allows the copper pillar more time to dissipate heat between pulses, reducing heat accumulation.

[0066] S3, using laser engraving (fiber laser, wavelength 1064nm, power 300W), a corrugated structure (Ra=10μm, surface area increased by 40%) is formed on the surface of a 0.6mm thick copper foil. A copper substrate is 3D printed using laser powder bed fusion (L-PBF) (powder particle size 15-45μm, laser power 300W, scanning speed 800mm / s). The microchannel width is 0.3mm, the depth is 1.2mm, and the channel density is 20 channels / cm. A SiO2 / PVDF nanocomposite slurry is electrostatically sprayed onto the surface of the DBC substrate 10. Then, the IGBT chip 20 and the DBC substrate 10 are integrated by vacuum brazing. The brazing filler metal is AgCu28 (melting point 780℃), the brazing temperature is 800℃, and the holding time is 15min. Alumina ceramic 101 serves as the intermediate insulating layer, and the upper and lower copper layers are welded together using the brazing filler metal.

[0067] S4. Silicon carbide nanowires were plasma-activated using argon gas (300W, 5min) to enhance interfacial bonding with organosilicon. The silicon carbide nanowires and organosilicon prepolymer (viscosity 5000cps) were then vacuum-mixed (vacuum degree ≤0.1Pa), followed by vacuum encapsulation (vacuum degree 10⁻³ Pa) and staged curing (80℃ / 2h → 120℃ / 1h → 160℃ / 4h) to form a three-dimensional thermally conductive network with a thermal conductivity of 1.2W / mK and a 50% increase in mechanical strength.

[0068] S5. Before brazing the IGBT chip 20 to the DBC substrate 10, insert a micropillar array 30 between them and perform ultrasonic hot-press bonding (pressure 15MPa, temperature 180℃, ultrasonic power 500W). Use a liquid metal honeycomb structure as a conductive medium. Finally, use a carbon fiber reinforced epoxy resin frame for vacuum hot-press encapsulation (tensile strength 800MPa), encapsulation temperature 150℃, pressure 10MPa, time 1h, and seal the edges with silicone rubber (thickness 0.5mm).

[0069] The fabrication process of the micropillar array 30 is as follows:

[0070] S51, substrate temperature 600℃, C2H2 flow rate 50sccm, plasma power 300W, carbon nanopillars were oriented vertically by electric field, and copper was filled at the bottom of the micropillars by pulse electroplating (peak current density 50A / dm², duty cycle 10%). The plating solution contained 2wt% nanodiamond particles.

[0071] S52 uses a mechanical twisting process (500 rpm, 0.1 N tension) to twist the micropillars into a spiral structure, then uses vacuum impregnation (0.1 Pa vacuum) to wrap the outer surface of the micropillars with silicone material, and then performs gradient curing (60℃→100℃→150℃ for 1 h each).

[0072] S53, through the APTES silane coupling agent, forms Si-OC covalent bonds between the copper / diamond composite and the organosilicon coating layer, which can significantly enhance the bonding force between the two, and the addition of 0.5wt% carbon quantum dots to the organosilicon material prepolymer on the top improves the interfacial bonding force.

[0073] S6. Performance testing was performed using a Keysight B1505A power device analyzer.

[0074] Aging screening: Temperature cycling: -55℃↔175℃, 1000 cycles (JESD22-A104), power cycling (AQG324 standard);

[0075] Failure analysis: X-ray inspection (bonding void rate <1%), infrared thermal imaging (hot spot temperature difference <5℃).

[0076] It should be noted that the dimensions and thickness of the above materials need to be adjusted according to actual needs, and due to the change in materials, the corresponding process temperature, time and other parameters also need to be adjusted accordingly.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

[0078] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0079] In the detailed description above, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features in a single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, with each claim representing a separate preferred embodiment of the invention.

[0080] Those skilled in the art will also understand that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments herein can be implemented as electronic hardware, computer software, or a combination thereof. To clearly illustrate the interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps described above are generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in alternative ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0081] The steps of the methods or algorithms described in conjunction with the embodiments herein can be directly embodied in hardware, software modules executed by a processor, or a combination thereof. The software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a user terminal. Alternatively, the processor and storage medium can exist as discrete components in the user terminal.

[0082] For software implementation, the techniques described in this application can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described in this application. This software code can be stored in memory units and executed by a processor. The memory units can be implemented within the processor or outside the processor; in the latter case, they are communicatively coupled to the processor via various means, as is well known in the art.

[0083] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

Claims

1. An improved IGBT module structure, characterized by, The application relates to a DBC substrate (10) which is a three-layer structure and sequentially comprises, from top to bottom, an alumina ceramic (101), a corrugated copper layer (102) and a liquid-cooled copper substrate (103) which are connected through vacuum brazing, the surface of the liquid-cooled copper substrate (103) is etched with micro-channels, the surface of the DBC substrate (10) is provided with a gradient dielectric constant layer, the upper surface of the DBC substrate (10) is provided with an IGBT chip (20), the IGBT chip (20) is provided in a flip-chip mode, the back surface of the IGBT chip (20) is thinned through laser stripping and mechanical polishing, a micro-pillar array (30) is arranged between the IGBT chip (20) and the DBC substrate (10), the back surface of the IGBT chip (20) is provided with a copper pillar bump (50), the top surface of the copper pillar bump (50) is etched with a honeycomb-shaped groove, liquid metal is filled in the groove to form a horizontal current distribution layer, the copper pillar bump (50) is arranged on the surface of the IGBT chip (20) through electroplating, ultrasonic-assisted hot pressing is adopted for bonding, and a low-dielectric-constant medium is filled, the upper surface of the copper pillar bump (50) is provided with a potting layer (40), and the bottom of the DBC substrate (10) is provided with a phase-change heat dissipation layer (60).

2. The improved IGBT module structure according to claim 1, wherein, The potting layer (40) is a silicon carbide nanowire reinforced silicone gel material, the surface of the silicon carbide nanowire is subjected to plasma activation treatment, the silicone prepolymer is mixed with the silicon carbide nanowire in a certain proportion in a vacuum, and then the mixture is filled and solidified in stages.

3. The improved IGBT module structure according to claim 2, wherein, The phase-change heat dissipation layer (60) is one of a graphene aerogel or a paraffin composite phase-change material.

4. The improved IGBT module structure according to claim 3, wherein, The micro-pillar array (30) is provided in a top flexible connection and bottom rigid connection mode, the bottom of the micro-pillar array (30) is a copper / diamond composite, the middle part is a spiral carbon nanotube bundle, and the outer side of the carbon nanotube bundle is wrapped with a silicone material.

5. A method for encapsulating the improved IGBT module structure according to any one of claims 1 to 4, characterized in that The application comprises the following steps: S1, the IGBT chip (20) is cleaned by using hydrofluoric acid gas, a titanium, nickel and silver stack is deposited on the bottom surface of the IGBT in a flip-chip state through magnetron sputtering as an electrode contact layer, and an insulating layer is formed on the sidewall of the IGBT chip (20) through atomic layer deposition; S2, a cylindrical opening is formed by using photoresist, the copper pillar bump (50) is electroplated by using a copper sulfate-based solution, a honeycomb structure is etched on the top of the copper pillar by using femtosecond laser two-photon polymerization, liquid metal is filled in the honeycomb groove, and ultrasonic-assisted hot pressing is used for bonding the flip-chip; S3, a corrugated structure is formed on the surface by using laser engraving, a copper substrate is 3D printed by using a laser powder bed fusion method, a SiO2 / PVDF nanocomposite slurry is used for electrostatic spraying on the surface of the DBC substrate (10), and then the IGBT chip (20) and the DBC substrate (10) are integrated through vacuum brazing; S4, using argon plasma activation of silicon carbide nanowires, enhance the interface with the organic silicon, silicon carbide nanowires and organic silicon prepolymer for vacuum mixing, finally vacuum filling, curing in stages, form a three-dimensional heat conduction network; S5, before the IGBT chip (20) and the DBC substrate (10) are brazed, a micro column array (30) is inserted between them, ultrasonic hot pressing is bonded, finally, a carbon fiber reinforced epoxy resin frame is used for vacuum hot pressing packaging, and the edge is coated with silicone rubber seal; S6, using power device analyzer, performance test.

6. The improved encapsulation method of IGBT module structure according to claim 5, wherein, The micro column array (30) of step S5 has the following process flow: S51, carbon nanometer micro column vertical orientation by electric field induction, using pulse plating to fill copper at the bottom of the micro column; S52, using mechanical twisting process to twist the micro column to form a spiral structure, using vacuum impregnation to wrap the organic silicon material on the outer surface of the micro column, and then gradient curing; S53, chemical bonding at the bottom of the carbon nanometer micro column, forming Si-O-C covalent bond through APTES silane coupling agent, and adding carbon quantum dots to the top organic silicon material prepolymer to improve the interface bonding force.

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