TFHE scheme processing system and method based on in-memory computing platform

Abstract

The invention discloses a TFHE scheme processing system and method based on an in-memory computing platform. When receiving a tlwe ciphertext and a private key of the TFHE scheme, the host side generates a KSK and a BK according to the private key, performs data splitting on the tlwe ciphertext, the KSK and the BK, and sends the split data to an MRAM in the DPU side; and the DPU end returns the split data in the MRAM to the WRAM through the DMA interface, carries out bootstrap operation on the split data through the TASKLET micro-thread, returns a bootstrap operation result to the MRAM and transmits the bootstrap operation result in the MRAM to the DIMM module, and the host end retrieves the bootstrap operation result in the DIMM module and integrates the bootstrap operation result in the DIMM module. According to the invention, a cooperative processing mechanism of the host end, the DIMM module and the DPU end is adopted, deep fusion of calculation and storage is realized, and the processing efficiency of a TFHE scheme is improved.

Description

Technical Field

[0001] The present invention relates to the field of fully homomorphic encryption technology, and in particular to a TFHE scheme processing system and method based on an in-memory computing platform. Background Art

[0002] Fully homomorphic encryption, a core technology supporting privacy-preserving computing, enables direct computation on encrypted data without decrypting the ciphertext of the Torus Fully Homomorphic Encryption (TFHE) scheme. This provides a revolutionary data security solution for highly sensitive scenarios such as healthcare and finance in cloud computing environments. However, this technology faces severe performance bottlenecks in practical applications: the encryption process causes exponential data expansion (the ciphertext size can be up to 5,000 times that of the original data), and the core computational steps involve complex operations such as high-dimensional polynomial rotations and modular multiplication and accumulation, causing traditional computing architectures to hit a "memory wall" problem.

[0003] Existing hardware acceleration solutions exhibit significant limitations: GPUs, while offering the advantage of parallel processing, are constrained by video memory capacity and energy consumption. Application-specific integrated circuits (ASICs) can improve computational density but lack adaptability to algorithm iterations. Field-Programmable Gate Arrays (FPGAs), while reconfigurable, can alleviate some bottlenecks but struggle to overcome off-chip memory bandwidth limitations. These solutions are unable to effectively address the dual storage and computational pressures unique to fully homomorphic encryption. Therefore, effectively addressing these dual pressures, and thereby improving the processing efficiency of TFHE solutions, is an urgent issue that needs to be addressed.

[0004] The above content is only used to assist in understanding the technical solution of the present invention and does not constitute an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of the present invention is to provide a TFHE scheme processing system and method based on an in-memory computing platform, aiming to effectively address the dual pressures of storage and computing unique to fully homomorphic encryption, thereby improving the processing efficiency of the TFHE scheme.

[0006] To achieve the above objectives, the present invention provides a TFHE solution processing system based on an in-memory computing platform. The TFHE solution processing system includes a host side, a DIMM module, and a DPU side built into the in-memory computing platform: The host side is used to, when receiving the tlwe ciphertext and private key of the TFHE scheme transmitted by the user, generate KSK and BK respectively according to the private key through the ikskgen function and the bknttgen function, split the tlwe ciphertext, the KSK and the BK, and send the split data to the MRAM in the DPU side; The DPU is configured to transmit the split data in the MRAM back to the WRAM through the DMA interface, perform a bootstrap operation on the split data through the TASKLET microthread, transmit the bootstrap operation result back to the MRAM, and transmit the bootstrap operation result in the MRAM to the DIMM module; The host end is further used to retrieve the bootstrap operation results in the DIMM module and integrate the bootstrap operation results.

[0007] Optionally, after sending the split data to the DPU, the method further includes: If the DPU side turns on the asynchronous mode, the DPU side and the CPU side are controlled to execute tasks simultaneously.

[0008] Optionally, after sending the split data to the DPU, the method further includes: If the DPU side turns on the asynchronous mode, the DPU side and the CPU side are controlled to execute tasks simultaneously.

[0009] Optionally, the host side includes a host CPU and a DIMM module, and the DPU side includes multiple DPUs; The host CPU is configured to split the tlwe ciphertext and the BK, store the split data in a DIMM module, and send the split data in the DIMM module to the MRAM in each DPU; The DPU is configured to transfer the split data in the MRAM back to the WRAM through the DMA interface, perform blind rotation on the split data through the TASKLET microthread, transfer the rotation result back to the corresponding MRAM, and transmit the rotation result in the MRAM to the DIMM module; The host CPU is further configured to retrieve the rotation results in the DIMM module, combine the rotation results, evenly split the combined trlwe ciphertext, store the evenly split trlwe ciphertext in the DIMM module, and send the evenly split trlwe ciphertext in the DIMM module to the MRAM in each DPU; The DPU is further configured to transmit the evenly divided trlwe ciphertext in the MRAM back to the WRAM through the DMA interface, extract samples of the evenly divided trlwe ciphertext through the TASKLET microthread, transmit the sample extraction results back to the corresponding MRAM, and transmit the sample extraction results in the MRAM to the DIMM module; The host CPU is further configured to retrieve the sample extraction results in the DIMM module, combine the sample extraction results, evenly split the combined sample ciphertext and the KSK, store the evenly split ciphertext samples and the evenly split KSK in the DIMM module, and send the evenly split ciphertext samples and the evenly split KSK in the DIMM module to the MRAM in each DPU; The DPU is further configured to transmit the evenly split ciphertext samples and the evenly split KSK in the MRAM back to the WRAM through the DMA interface, and perform key switching on the evenly split ciphertext samples and the evenly split KSK through the TASKLET microthread.

[0010] Optionally, after performing key switching on the evenly divided ciphertext samples and the evenly divided KSK, the method further includes: The key switching result is transmitted back to the corresponding MRAM, and the key switching result is transmitted to the DIMM module, so that the host CPU retrieves the key switching result in the DIMM module and overlays and integrates the key switching result.

[0011] Optionally, the splitting of the tlwe ciphertext and the BK, storing the split data in a DIMM module, and sending the split data in the DIMM module to the MRAM in each DPU respectively include: The tlwe ciphertext and the BK are equally divided, and the equally divided tlwe ciphertext and BK are stored in a DIMM module; The first half of the tlwe ciphertext in the DIMM module is evenly split based on the number of DPUs; Call the dpu_prepare_xfer interface and the dpu_push_xfer interface to transmit the first half of the tlwe ciphertext evenly divided in the DIMM module to each DPU in parallel, and call the dpu_broadcast_to interface to broadcast the first half of the BK and blind rotation offset parameters evenly divided in the DIMM module to the MRAM in each DPU; After the transmission is completed, the second half of the tlwe ciphertext in the DIMM module is evenly split based on the number of DPUs; The dpu_prepare_xfer interface and the dpu_push_xfer interface are called to transmit the second half of the tlwe ciphertext evenly split in the DIMM module to each DPU in parallel, and the dpu_broadcast_to interface is called to broadcast the second half of the BK and blind rotation offset parameters evenly divided in the DIMM module to the MRAM in each DPU.

[0012] Optionally, performing blind rotation on the split data by using a TASKLET microthread includes: The control selector function of NTT acceleration and polynomial multiplication in the TFHE homomorphic encryption library is called to perform blind rotation on the split data through the TASKLET microthread.

[0013] Optionally, evenly splitting the combined trlwe ciphertext, storing the evenly split trlwe ciphertext in the DIMM module, and sending the evenly split trlwe ciphertext in the DIMM module to the MRAM in each DPU respectively include: Evenly split the trlwe ciphertext based on the number of DPUs, and store the evenly split trlwe ciphertext in the DIMM module; The dpu_prepare_xfer interface and the dpu_push_xfer interface are called to respectively transmit the evenly divided trlwe ciphertext in the DIMM module to the MRAM in each DPU in parallel.

[0014] Optionally, the evenly splitting the combined sample ciphertext and the KSK respectively, storing the evenly split ciphertext samples and the evenly split KSK in the DIMM module, and sending the evenly split ciphertext samples and the evenly split KSK in the DIMM module to the MRAM in each DPU respectively, includes: Performing equal division on the sample ciphertext and the KSK based on the number of DPUs, and storing the equal-divided ciphertext samples and the equal-divided KSK in the DIMM module; The dpu_prepare_xfer interface and the dpu_push_xfer interface are called to respectively transmit the evenly divided ciphertext samples and evenly divided KSK in the DIMM module in parallel to the MRAM in each DPU.

[0015] In addition, to achieve the above objectives, the present invention also proposes a TFHE solution processing method based on an in-memory computing platform, the method comprising: When the host receives the tlwe ciphertext and private key of the TFHE scheme transmitted by the user, it generates KSK and BK according to the private key through the ikskgen function and the bknttgen function respectively, splits the tlwe ciphertext, the KSK and the BK, and sends the split data to the MRAM in the DPU end; The DPU returns the split data in the MRAM to the WRAM through the DMA interface, performs a bootstrap operation on the split data through the TASKLET microthread, returns the bootstrap operation result to the MRAM, and transmits the bootstrap operation result in the MRAM to the DIMM module; The host side retrieves the bootstrap operation results in the DIMM module and integrates the bootstrap operation results.

[0016] When the host side of the present invention receives the tlwe ciphertext and private key of the TFHE scheme transmitted by the user, it generates KSK and BK respectively based on the private key through the ikskgen function and the bknttgen function, and performs data splitting on the tlwe ciphertext, KSK and BK, and sends the split data to the MRAM in the DPU side. The DPU side transmits the split data in the MRAM back to the WRAM through the DMA interface, performs a bootstrap operation on the split data through the TASKLET microthread, transmits the bootstrap operation result back to the MRAM, and transmits the bootstrap operation result in the MRAM to the DIMM module. The host side integrates the bootstrap operation result retrieved from the DIMM module. The present invention adopts a collaborative processing mechanism between the host side, the DIMM module and the DPU side, mapping the blind rotation, sample extraction and key switching in the bootstrap process to the in-memory computing unit, realizing the deep integration of computing and storage, and improving the processing efficiency of the TFHE scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a structural block diagram of a first embodiment of a TFHE solution processing system based on an in-memory computing platform according to the present invention; Figure 2 This is a schematic diagram of the DPU processing flow of the first embodiment of the TFHE solution processing system based on the in-memory computing platform of the present invention; Figure 3 FIG. 4 is a flow chart of a first embodiment of a TFHE solution processing method based on an in-memory computing platform according to the present invention.

[0018] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0019] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] The embodiment of the present invention provides a TFHE solution processing system based on an in-memory computing platform, referring to Figure 1 , Figure 1 FIG. 4 is a structural block diagram of a first embodiment of a TFHE solution processing system based on an in-memory computing platform according to the present invention.

[0021] In this embodiment, the TFHE solution processing system includes a host side 1001 and a DPU side 1002 built into an in-memory computing platform (UPMEMPIM). The host side includes a host central processing unit (CPU) and a standard memory (DIMM) module; the DPU side includes multiple DRAM processing units (DPUs), each of which has a built-in working random access memory (WRAM) and main random access memory (MRAM).

[0022] It should also be noted that the host CPU only processes the data and needs to store the processed data in the DIMM module.

[0023] The host side 1001 is configured to, upon receiving the TLWE ciphertext and private key of the TFHE scheme transmitted by the user, generate a KSK and a BK according to the private key using the ikskgen function and the bknttgen function, respectively, and perform data splitting on the TLWE ciphertext (ciphertext in the TLWE format), the KSK, and the BK, and send the split data to the MRAM in the DPU side 1002; The DPU end 1002 is used to return the split data in the MRAM to the WRAM through the DMA interface, perform a bootstrap operation on the split data through the TASKLET microthread, return the bootstrap operation result to the MRAM, and transmit the bootstrap operation result in the MRAM to the DIMM module in the host end; The host end 1001 is further configured to retrieve the bootstrap operation results in the DIMM module and integrate the bootstrap operation results.

[0024] Furthermore, if the DPU side turns on the asynchronous mode, the DPU side and the CPU side are controlled to execute tasks simultaneously; if the DPU side turns on the synchronous mode, after the DPU side finishes executing the task, the CPU side is controlled to execute the task.

[0025] In practice, the DPU executes tasks in two ways: synchronous mode and asynchronous mode. This mode can be selected using the DPU_SYNCHRONOUS (synchronous) or DPU_ASYNCHRONOUS (asynchronous) startup options. In synchronous mode, the DPU and host CPU cannot operate simultaneously. While the DPU is executing a task, the host CPU will be suspended, waiting for the DPU to complete the task. In asynchronous mode, the DPU and host CPU can execute tasks concurrently. While the DPU is operating, the host CPU can perform other tasks, such as preprocessing data for the next stage or post-processing the results returned by the DPU. In asynchronous mode, the host needs to use dpu_sync to synchronize the DPU after starting it. dpu_sync waits for the completed operation on the started DPU.

[0026] It should be understood that the bootstrapping operation includes blind rotation, sample extraction, and key switching.

[0027] In the specific implementation, during the bootstrapping process, the blind rotation operation requires splitting the tlwe ciphertext and the bootstrapping key (BK); the sample extraction operation requires evenly splitting the trlwe ciphertext according to the number of allocated DPUs; and the key switching operation requires evenly splitting the sample ciphertext and the key switching key (KSK) according to the number of allocated DPUs.

[0028] When ciphertext and key are divided into blocks, ensure that the divided ciphertext or key is padded with 8 bytes to avoid additional overhead caused by address misalignment in DPU DMA transmission.

[0029] In this embodiment, the tlwe ciphertext and private key of the TFHE scheme transmitted by the user are stored in the DIMM module. The host CPU calls the private key in the DIMM module and generates KSK and BK respectively through the ikskgen function and the bknttgen function, and stores KSK and BK in the DIMM module. The host CPU calls the tlwe ciphertext and BK in the DIMM module, splits the tlwe ciphertext and BK respectively, and stores the split data in the DIMM module in sequence. The split data in the DIMM module is sent to the MRAM in each DPU respectively; the DPU transmits the split data in the MRAM back to the WRAM through the DMA interface. The TASKLET microthread performs blind rotation on the split data in the WRAM, and transmits the rotation result back to the MRAM corresponding to the DPU, and transmits the rotation result in the MRAM to the DIMM module, so that the host CPU can retrieve the rotation result in the DIMM module, and splice the rotation result to obtain the spliced ​​trlwe ciphertext, and transmit the spliced ​​trlwe ciphertext to the DIMM module; the host CPU evenly splits the spliced ​​trlwe ciphertext in the DIMM module, and sends the evenly split trlwe ciphertext to the MRAM in each DPU in sequence; the DPU returns the evenly split trlwe ciphertext in the MRAM through the DMA interface The trlwe ciphertext (i.e., the ciphertext in the trlwe format) evenly divided in the WRAM is sampled and transmitted to the MRAM corresponding to the DPU through the TASKLET microthread, and the sample extraction result is transmitted back to the MRAM corresponding to the DPU, and the sample extraction result in the MRAM is transmitted to the DIMM module, so that the host CPU calls the sample extraction result in the DIMM module, and splices the sample extraction result to obtain the spliced ​​sample ciphertext, and stores the spliced ​​sample ciphertext in the DIMM module; the host CPU calls the spliced ​​sample ciphertext and KSK in the DIMM module, and splits the spliced ​​sample ciphertext and KSK evenly, and stores the average split ciphertext sample The evenly divided ciphertext samples and the evenly divided KSK are stored in the DIMM module, and the evenly divided ciphertext samples and the evenly divided KSK in the DIMM module are sent to the MRAM in each DPU in sequence; the DPU transmits the evenly divided ciphertext samples and the evenly divided KSK in the MRAM back to the WRAM through the DMA interface, performs key switching on the evenly divided ciphertext samples and the evenly divided KSK in the WRAM through the TASKLET microthread, transmits the key switching result back to the MRAM corresponding to the DPU, and transmits the key switching result to the DIMM module, so that the host CPU calls the key switching result in the DIMM module and overlays and integrates the key switching results.

[0030] Furthermore, the tlwe ciphertext and BK are split and processed, and the split data are stored in the DIMM module. The split data in the DIMM module are sent to the MRAM in each DPU respectively. The processing method is as follows: the tlwe ciphertext and BK are equally divided and stored in the DIMM module; the first half of the tlwe ciphertext in the DIMM module is evenly split based on the number of DPUs; the dpu_prepare_xfer interface and the dpu_push_xfer interface are called to sequentially transmit the first half of the tlwe ciphertext evenly split in the DIMM module to the MRAM in each DPU in parallel (for example, the first half of the tlwe ciphertext evenly split is A, B, and C in order, and there are DPU-1, DPU-2, and DPU-3, then A is sent to DPU-1. The dpu_broadcast_to interface is called to broadcast the first half BK and blind rotation offset parameters equally divided in the DIMM module to the MRAM in each DPU. After the transmission is completed, the second half of the tlwe ciphertext equally divided in the DIMM module is evenly split based on the number of DPUs. The dpu_prepare_xfer interface and the dpu_push_xfer interface are called in sequence to transmit the second half of the tlwe ciphertext equally divided in the DIMM module in parallel to the MRAM in each DPU. The dpu_broadcast_to interface is called to broadcast the second half BK and blind rotation offset parameters equally divided in the DIMM module to the MRAM in each DPU.

[0031] It should also be noted that the host side pre-calculates the offset parameters required for the NTT operation during the blind rotation process.

[0032] The host side calls the TwistGen and TableGen functions in the cuhe library to calculate and generate the rotation factor array ntttable used in the NTT operation during blind rotation, and the Twiddle factor lookup table ntttwist used in the subsequent butterfly operation, where the rotation factor array ntttable and the Twiddle factor lookup table ntttwist are offset parameters.

[0033] Furthermore, the combined trlwe ciphertext is evenly divided, and the evenly divided trlwe ciphertext is stored in the DIMM module, and the evenly divided trlwe ciphertext in the DIMM module is sent to the MRAM in each DPU respectively. The processing method is as follows: the trlwe ciphertext is evenly divided based on the number of DPUs, and the evenly divided trlwe ciphertext is stored in the DIMM module; the dpu_prepare_xfer interface and the dpu_push_xfer interface are called in sequence to transmit the evenly divided trlwe ciphertext in the DIMM module in parallel to the MRAM in each DPU respectively.

[0034] Furthermore, the combined sample ciphertext and KSK are evenly divided, and the evenly divided ciphertext samples and the evenly divided KSK are stored in the DIMM module, and the evenly divided ciphertext samples and the evenly divided KSK in the DIMM module are sent to the MRAM in each DPU. The processing method is as follows: the sample ciphertext and the KSK are evenly divided based on the number of DPUs, and the evenly divided ciphertext samples and the evenly divided KSK are stored in the DIMM module; the dpu_prepare_xfer interface and the dpu_push_xfer interface are called in sequence to transmit the evenly divided ciphertext samples and the evenly divided KSK in the DIMM module in parallel to the MRAM in each DPU.

[0035] Use the dpu_broadcast_to interface to distribute shared parameters (such as encryption initialization vectors), and achieve multi-DPU synchronous injection through the symbolic address resolution engine to eliminate redundant transmission.

[0036] The dpu_prepare_xfer and dpu_push_xfer interfaces are combined to implement fine-grained transmission of sharded ciphertext / keys. Each DPU only needs to register a single continuous buffer and access all sharded data through offset calculation.

[0037] In this embodiment, reference Figure 2 , Figure 2FIG. 1 is a schematic diagram of the DPU processing flow of the first embodiment of the TFHE solution processing system based on the in-memory computing platform of the present invention. After the DPU receives the required data from the host, it enters the DPU for processing. The process of each DPU processing subtask (that is, the assigned data) is the same. That is, the data initially transmitted to the DPU by the host CPU through the DIMM module will be stored in the DPU's MRAM. Before the DPU operates on this data, it needs to explicitly call the mram_read() function (that is, the DMA interface) to transfer the data to the DPU's WRAM, and then perform specific data processing (that is, blind rotation or sample extraction or key switching). During the data processing process, the data in the WRAM will be further divided and the DPU's TASKLET micro-threads will be enabled to perform multi-threaded concurrent processing of tasks to achieve acceleration. The intermediate results of these subtasks will be temporarily stored in the WRAM. After the subtask processing is completed, the mram_write() function needs to be explicitly called to return the final result to the MRAM, and then the host is notified of the completion. The host CPU calls the dpu_prepare_xfer interface and the dpu_push_xfer interface to transfer the results of each DPU calculation back to the host memory (that is, the DIMM module).

[0038] Furthermore, the specific steps of performing blind rotation, sample extraction and key switching on the DPU are as follows: Blind rotation: Before the DPU can execute the blind rotation subtasks in parallel, it must first implement a lightweight math library that can be directly called on the DPU. This involves refactoring the code for the INtorus torus operation library and the number theoretic transform (NTT) from the existing TFHE homomorphic encryption library (TFHEpp) into C code that can be executed on the DPU. Each DPU then uses the tlwe ciphertext and BK key data received from the host as function parameters to call a math library function (the control selector function for NTT acceleration and polynomial multiplication, namely CMUXNTTwithPolynomialMulByXaiMinusOne) to complete the operation. The host only passes the tlwe ciphertext and the first half of the BK key to a group of DPUs. After the preceding DPU cluster completes the operation, the data is retrieved by the host CPU, which then passes the second half of the tlwe ciphertext and BK key to the subsequent DPU cluster for further calculation. The host CPU then sequentially combines the rotation results (res), generating the trlwe ciphertext.

[0039] The INTorus torus operation library includes: 1. Modular multiplication optimization: For 64-bit modular multiplication operations, a bit decomposition strategy is used to replace the traditional multiplier. The operand is split into high and low 32 bits, and the four partial products are calculated and the results are reassembled by shifting and masking. For example, This is achieved by following these steps: uint64_t a_high = a>>32, a_low = a&0xFFFFFFFF; uint64_t b_high = b>>32, b_low = b&0xFFFFFFFF; uint64_t res = (a_low b_low) + ((a_high b_low + a_low b_high)<<32) + (a_high b_high<<64); res = (res&P) | (res>>61); / / Fast modular reduction This solution avoids the use of 128-bit intermediate variables and saves 30% of computing cycles.

[0040] 2. Fast exponentiation: By pre-calculating the power table of 2 (such as ) Accelerate the calculation of polynomial coefficients in blind rotation. Combined with the sliding window method to reduce the number of multiplications, for example , decompose the exponential into blocks of window size 4.

[0041] Number Theoretic Transform (NTT) optimization: 1. Butterfly vectorization: Leveraging the DPU's SIMD instruction set to process multiple polynomial coefficients in parallel. For example, the butterfly operation of Radix-2 NTT is expanded into four parallel operations, and register cascading reduces memory accesses, increasing NTT speed by 2.1 times.

[0042] 2. Pre-calculate the twiddle factor: Store the twiddle factor required by NTT in WRAM in advance to avoid repeated calculation during runtime.

[0043] Input: bootstrapping key , TRLWE ciphertext form accumulator ACC Output: TRLWE ciphertext ACC / / The host sets the number of DPU sets according to the security level

[0044] / / … / / Host and DPU communicate / / … / / DPU_1

[0045]

[0046]

[0047]

[0048] / / … / / Host and DPU communicate / / … / / DPU_i ...

[0049]

[0050]

[0051]

[0052]

[0053] Sample extraction: After receiving the data from the host CPU (i.e., the evenly split trlwe ciphertext), the DPU begins to execute the assignment operation of the ciphertext trlwe to the result ciphertext res in parallel during sample extraction, and finally returns res to the corresponding MRAM.

[0054] Input: TRLWE ciphertext accumulator trlwe[] Output: TLWE ciphertext form is tlwe[] / / Set the DPU set and allocate a certain number of DPUs / / …the host communicates with the DPU to transmit data... / /

[0055]

[0056]

[0057]

[0058]

[0059] / / ...the host communicates with the DPU to receive data... for each tlwe

[0060]

[0061]

[0062] Key switching: The DPU receives the blocked sample ciphertext and KSK data. The key switching process modifies the value of the result ciphertext res based on the values ​​of the sample ciphertext and KSK data. Each DPU modifies the value of res in parallel based on the sample ciphertext and KSK fragments, and then transmits the key switching result back to the corresponding MRAM.

[0063] It should also be noted that the TFHE key switching operation is different from the blind rotation operation. Each The computations are independent of each other and lack data dependencies. Based on this, the first-layer accumulation is expanded, and the originally sequential accumulation operations in the algorithm can be reconstructed into spatially parallel multidimensional computational tasks. By distributing the key switching key to each DPU in a group, each DPU only needs to handle a portion of the computation involved in the key switching operation. This sharding strategy enables each computing unit to independently perform polynomial multiplication and addition operations within its assigned interval, and the computational processes between units are completely decoupled, ensuring that the runtime remains constant and does not increase linearly with the number of ciphertext blocks that need to be calculated.

[0064] The key switching operation is implemented on the DPU. First, the system sets up a DPU set and allocates a certain number of DPUs. Then, the key switching key is divided and transmitted to each DPU. On the DPU, the key is calculated based on the received key. Part of the calculation after expansion After the host collects the calculation results of all DPUs, they are accumulated and summed (i.e., superimposed and integrated) on the host side.

[0065] Input: Ciphertext sample , keyswitch key

[0066] Output: After key space transformation

[0067] / / Set the DPU set and allocate a certain number of DPUs / / one Allocate and offload to a DPU

[0068]

[0069]

[0070]

[0071] for i to n

[0072]

[0073]

[0074] In this embodiment, when the host receives the tlwe ciphertext and private key of the TFHE scheme transmitted by the user, it generates KSK and BK respectively based on the private key through the ikskgen function and the bknttgen function, and splits the tlwe ciphertext, KSK, and BK into data, and sends the split data to the MRAM in the DPU. The DPU transmits the split data in the MRAM back to the WRAM via the DMA interface, performs a bootstrapping operation on the split data through the TASKLET microthread, returns the bootstrapping operation result to the MRAM, and transmits the bootstrapping operation result in the MRAM to the DIMM module in the host. The host integrates the bootstrapping operation result in the DIMM module. This embodiment adopts a collaborative processing mechanism between the host and DPU, mapping the blind rotation, sample extraction, and key switching in the bootstrapping process to the in-memory computing unit, achieving a deep integration of computing and storage, and improving the processing efficiency of the TFHE scheme.

[0075] Reference Figure 3 , Figure 3 FIG. 4 is a flow chart of a first embodiment of a TFHE solution processing method based on an in-memory computing platform according to the present invention.

[0076] like Figure 3 As shown, the TFHE solution processing system includes a host side and a DPU side. The TFHE solution processing method based on the in-memory computing platform proposed in the embodiment of the present invention includes: Step S10: When the host receives the tlwe ciphertext and private key of the TFHE scheme transmitted by the user, it generates KSK and BK according to the private key through the ikskgen function and the bknttgen function respectively, splits the tlwe ciphertext, the KSK and the BK, and sends the split data to the MRAM in the DPU; Step S20: The DPU returns the split data in the MRAM to the WRAM through the DMA interface, performs a bootstrap operation on the split data through the TASKLET microthread, returns the bootstrap operation result to the MRAM, and transmits the bootstrap operation result in the MRAM to the DIMM module; Step S30: the host side retrieves the bootstrap operation results in the DIMM module and integrates the bootstrap operation results.

[0077] Other embodiments or specific implementations of the TFHE solution processing method based on the in-memory computing platform of the present invention can refer to the above-mentioned method embodiments and will not be repeated here.

[0078] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0079] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0080] Through the description of the above embodiments, those skilled in the art will clearly understand that the above-mentioned embodiments and methods can be implemented by means of software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is a more preferred embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory / random access memory, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0081] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A TFHE solution processing system based on an in-memory computing platform, characterized in that: The TFHE solution processing system includes a host side and a DPU side built into the in-memory computing platform; The host side is used to, when receiving the tlwe ciphertext and private key of the TFHE scheme transmitted by the user, generate KSK and BK respectively according to the private key through the ikskgen function and the bknttgen function, split the tlwe ciphertext, the KSK and the BK, and send the split data to the MRAM in the DPU side; The DPU side is used to return the split data in the MRAM to the WRAM through the DMA interface, perform a bootstrap operation on the split data through the TASKLET microthread, return the bootstrap operation result to the MRAM, and transmit the bootstrap operation result in the MRAM to the DIMM module in the host side; The host end is further used to retrieve the bootstrap operation results in the DIMM module and integrate the bootstrap operation results.

2. The system according to claim 1, wherein After sending the split data to the DPU, the method includes: If the DPU side turns on the asynchronous mode, the DPU side and the CPU side are controlled to execute tasks simultaneously.

3. The system according to claim 1, wherein After sending the split data to the DPU, the method further includes: If the DPU side turns on the synchronization mode, after the DPU side finishes executing the task, it controls the CPU side to execute the task.

4. The system according to claim 1, wherein: The host side includes a host CPU and a DIMM module, and the DPU side includes multiple DPUs; The host CPU is configured to split the tlwe ciphertext and the BK, store the split data in a DIMM module, and send the split data in the DIMM module to the MRAM in each DPU; The DPU is configured to transfer the split data in the MRAM back to the WRAM through the DMA interface, perform blind rotation on the split data through the TASKLET microthread, transfer the rotation result back to the corresponding MRAM, and transmit the rotation result in the MRAM to the DIMM module; The host CPU is further configured to retrieve the rotation results in the DIMM module, combine the rotation results, evenly split the combined trlwe ciphertext, store the evenly split trlwe ciphertext in the DIMM module, and send the evenly split trlwe ciphertext in the DIMM module to the MRAM in each DPU; The DPU is further configured to transmit the evenly divided trlwe ciphertext in the MRAM back to the WRAM through the DMA interface, extract samples of the evenly divided trlwe ciphertext through the TASKLET microthread, transmit the sample extraction results back to the corresponding MRAM, and transmit the sample extraction results in the MRAM to the DIMM module; The host CPU is further configured to retrieve the sample extraction results in the DIMM module, combine the sample extraction results, evenly split the combined sample ciphertext and the KSK, store the evenly split ciphertext samples and the evenly split KSK in the DIMM module, and send the evenly split ciphertext samples and the evenly split KSK in the DIMM module to the MRAM in each DPU; The DPU is further configured to transmit the evenly split ciphertext samples and the evenly split KSK in the MRAM back to the WRAM through the DMA interface, and perform key switching on the evenly split ciphertext samples and the evenly split KSK through the TASKLET microthread.

5. The system according to claim 4, wherein: After the key switching is performed on the evenly divided ciphertext samples and the evenly divided KSK, the method includes: The key switching result is transmitted back to the corresponding MRAM, and the key switching result is transmitted to the DIMM module, so that the host CPU retrieves the key switching result in the DIMM module and overlays and integrates the key switching result.

6. The system according to claim 4, wherein: The splitting of the tlwe ciphertext and the BK, storing the split data in the DIMM module, and sending the split data in the DIMM module to the MRAM in each DPU respectively include: The tlwe ciphertext and the BK are equally divided, and the equally divided tlwe ciphertext and BK are stored in a DIMM module; The first half of the tlwe ciphertext in the DIMM module is evenly split based on the number of DPUs; Call the dpu_prepare_xfer interface and the dpu_push_xfer interface to transmit the first half of the tlwe ciphertext evenly divided in the DIMM module to the MRAM in each DPU in parallel, and call the dpu_broadcast_to interface to broadcast the first half of the BK and blind rotation offset parameters evenly divided in the DIMM module to the MRAM in each DPU; After the transmission is completed, the second half of the tlwe ciphertext in the DIMM module is evenly split based on the number of DPUs; The dpu_prepare_xfer interface and the dpu_push_xfer interface are called to respectively transmit the second half of the tlwe ciphertext evenly split in the DIMM module to the MRAM in each DPU in parallel, and the dpu_broadcast_to interface is called to broadcast the second half of the BK and blind rotation offset parameters evenly divided in the DIMM module to the MRAM in each DPU.

7. The system according to claim 6, wherein: The blind rotation of the split data by the TASKLET micro-thread includes: The control selector function of NTT acceleration and polynomial multiplication in the TFHE homomorphic encryption library is called to perform blind rotation on the split data through the TASKLET microthread.

8. The system according to claim 4, wherein: The evenly splitting the combined trlwe ciphertext, storing the evenly split trlwe ciphertext in the DIMM module, and sending the evenly split trlwe ciphertext in the DIMM module to the MRAM in each DPU respectively include: Evenly split the trlwe ciphertext based on the number of DPUs, and store the evenly split trlwe ciphertext in the DIMM module; The dpu_prepare_xfer interface and the dpu_push_xfer interface are called to respectively transmit the evenly divided trlwe ciphertext in the DIMM module to the MRAM in each DPU in parallel.

9. The system according to claim 4, wherein: The evenly splitting the combined sample ciphertext and the KSK respectively, storing the evenly split ciphertext samples and the evenly split KSK in the DIMM module, and sending the evenly split ciphertext samples and the evenly split KSK in the DIMM module to the MRAM in each DPU respectively, includes: Performing equal division on the sample ciphertext and the KSK based on the number of DPUs, and storing the equal-divided ciphertext samples and the equal-divided KSK in the DIMM module; The dpu_prepare_xfer interface and the dpu_push_xfer interface are called to respectively transmit the evenly divided ciphertext samples and evenly divided KSK in the DIMM module in parallel to the MRAM in each DPU.

10. A TFHE solution processing method based on an in-memory computing platform, characterized in that: The method comprises: When the host receives the tlwe ciphertext and private key of the TFHE scheme transmitted by the user, it generates KSK and BK according to the private key through the ikskgen function and the bknttgen function respectively, splits the tlwe ciphertext, the KSK and the BK, and sends the split data to the MRAM in the DPU end; The DPU returns the split data in the MRAM to the WRAM through the DMA interface, performs a bootstrap operation on the split data through the TASKLET microthread, returns the bootstrap operation result to the MRAM, and transmits the bootstrap operation result in the MRAM to the DIMM module; The host side retrieves the bootstrap operation results in the DIMM module and integrates the bootstrap operation results.

Images