Addition circuit, operation circuit, circuit for performing hash algorithm and related device

Abstract

The present disclosure relates to an addition circuit, an operation circuit, a circuit for performing a hash algorithm, and related devices. An addition circuit has a first input representing a first number, a second input representing a second number, and an output representing a sum of the first number and the second number. Each input is divided into a first part and a second part in correspondence with each other in order from a low bit to a high bit. The addition circuit includes a first register module for storing the second part of the first input, a second register module for storing the second part of the second input, a first adder for summing the first part of the first input and the first part of the second input to generate a first sum and a first carry, a third register module for storing the first carry, and a second adder for summing the second part of the first input, the second part of the second input, and the first carry to generate a second sum.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to an addition circuit, an operation circuit, a circuit for performing a hash algorithm, a computing chip, and a computing device. BACKGROUND

[0002] A hash algorithm is an algorithm that takes variable-length data as input and produces a fixed-length hash value as output, and its essence is to refine information. Since 1993, the U.S. Institute of Standards and Technology has designed and published multiple versions of the Secure Hash Algorithm (SHA), and SHA-256 is one of the secure hash algorithms with a hash length of 256 bits. SUMMARY

[0003] According to a first aspect of the present disclosure, an addition circuit is provided for calculating a sum of a first number and a second number. The addition circuit has a first input representing the first number and a second input representing the second number and has an output representing the sum of the first number and the second number, each of the first input and the second input is divided into a first part and a second part corresponding to each other, the first part and the second part represent partial bits of the input in turn from low to high. The addition circuit comprises: a first register module configured to store the second part of the first input; a second register module configured to store the second part of the second input; a first adder configured to sum the first part of the first input and the first part of the second input, thereby generating a first sum and a first carry; a third register module coupled to the first adder and configured to store the first carry; and a second adder coupled to the first register module, the second register module, and the third register module and configured to sum the second part of the first input, the second part of the second input, and the first carry, thereby generating a second sum, wherein the first sum and the second sum represent partial bits of the output in turn from low to high.

[0004] In some embodiments, the first part and the second part of each of the first input and the second input have the same number of bits.

[0005] In some embodiments, the number of bits of the first part of each of the first input and the second input is greater than the number of bits of the second part of the input.

[0006] In some embodiments, the number of bits of the first part of each of the first input and the second input is less than the number of bits of the second part of the input.

[0007] In some embodiments, the adder circuit further comprises a fourth register module coupled to the first adder and configured to store the first summand.

[0008] According to a second aspect of the present disclosure, there is provided an arithmetic circuit. The arithmetic circuit comprises a summation module comprising the adder circuit according to any embodiment of the first aspect of the present disclosure; and a first arithmetic module coupled to the summation module to provide the first input and the second input of the adder circuit.

[0009] In some embodiments, the adder circuit further comprises a fourth register module coupled to the first adder and configured to store the first summand, and the arithmetic circuit comprises a plurality of arithmetic stages, each of the plurality of arithmetic stages comprising a respective register module, and the plurality of arithmetic stages comprises a first arithmetic stage and a second arithmetic stage immediately following the first arithmetic stage, the second arithmetic stage further comprising the first to fourth register modules of the adder circuit, the first arithmetic module being arranged between the first arithmetic stage and the second arithmetic stage and coupled to the first respective register module of the first arithmetic stage, the first arithmetic module being configured to perform an arithmetic operation on data from the first respective register module to produce the first input and the second input of the adder circuit, and the first adder of the adder circuit being arranged between the first arithmetic stage and the second arithmetic stage.

[0010] In some embodiments, the plurality of arithmetic stages further comprises a third arithmetic stage immediately following the second arithmetic stage, a third respective register module of the third arithmetic stage being coupled to the summation module to receive an output of the adder circuit, and a second adder of the adder circuit being arranged between the second arithmetic stage and the third arithmetic stage.

[0011] In some embodiments, the arithmetic circuit further comprises a second arithmetic module arranged between the second arithmetic stage and the third arithmetic stage and coupled to the second respective register module of the second arithmetic stage, the second arithmetic module being configured to perform an arithmetic operation on data from the second respective register module.

[0012] In some embodiments, the summation module is a first summation module, the adder circuit is a first adder circuit, and the arithmetic circuit further comprises: a second summation module comprising a second adder circuit according to any embodiment of the first aspect of the present disclosure and further comprising a fourth register module coupled to the first adder and configured to store a first sum, wherein the third arithmetic stage further comprises the first to fourth register modules of the second adder circuit, the second arithmetic module is coupled to the second summation module to provide a first input and a second input of the second adder circuit, and is configured to operate on data from the second respective register modules to produce the first input and the second input of the second adder circuit, and the first adder of the second adder circuit is arranged between the second arithmetic stage and the third arithmetic stage.

[0013] According to a third aspect of this disclosure, a circuit for performing a hash algorithm is provided. The circuit includes: an input unit configured to receive data; and an arithmetic unit configured to calculate a hash value based on the received data, and includes a plurality of arithmetic stages arranged in a pipelined structure, wherein: the plurality of arithmetic stages include a first arithmetic stage and a second arithmetic stage immediately following the first arithmetic stage; each of the first and second arithmetic stages includes a 0th to a 15th extended register module respectively configured to store 0th to 15th extended data of that arithmetic stage; the 15th extended register module includes a first sum register submodule, a first carry register submodule, a second sum register submodule, and a second carry register submodule; the circuit further includes a first extended data arithmetic module arranged between the first and second arithmetic stages; the first extended data arithmetic module includes a first submodule and a second submodule; the first submodule is configured to perform a hash operation based on the 0th extended data of the first arithmetic stage and based on the 1st and 9th extended data of the first arithmetic stage. An initial sum and an initial carry are calculated from at least two of the 14th extended data, each of the initial sum and the initial carry being divided into a first part and a second part corresponding to each other, the first part and the second part representing the portion bits of each from the least significant bit to the most significant bit, wherein the second part of the initial sum is stored in the first sum register submodule of the 15th extended register module of the second arithmetic level, and the second part of the initial carry is stored in the first carry register submodule of the 15th extended register module of the second arithmetic level, and the second submodule includes a first adder configured to sum the first part of the initial sum and the first part of the initial carry to produce a first sum and a first carry, the first sum being stored in the second sum register submodule of the 15th extended register module of the second arithmetic level, and the first carry being stored in the second carry register submodule of the 15th extended register module of the second arithmetic level.

[0014] In some embodiments, the plurality of operation levels further include a third operation level immediately following the second operation level, the third operation level including a 14th extended register module configured to store 14th extended data of the operation level, and wherein the circuit further includes a second extended data operation module disposed between the second operation level and the third operation level, the second extended data operation module including a third submodule, and wherein the third submodule includes a second adder configured to sum a second portion of the initial sum, a second portion of the initial carry, and the first carry to generate a second sum, the second sum being stored in the 14th extended register module of the third operation level.

[0015] In some embodiments, the first sum is shifted from the second sum register submodule of the 15th extended register module of the second operation level to the 14th extended register module of the third operation level.

[0016] According to a fourth aspect of this disclosure, a computing chip is provided, including circuitry according to any embodiment of any of the first to third aspects of this disclosure.

[0017] According to a fifth aspect of this disclosure, a computing device is provided, including the computing chip described in a fourth aspect of this disclosure.

[0018] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0020] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0021] Figure 1 These are schematic block diagrams showing operational circuits in some examples;

[0022] Figure 2 This is a schematic block diagram illustrating an adder circuit according to some embodiments of the present disclosure;

[0023] Figure 3 This is a schematic block diagram illustrating an adder circuit according to some embodiments of the present disclosure;

[0024] Figure 4 This is a schematic block diagram illustrating an adder circuit according to some embodiments of the present disclosure;

[0025] Figure 5 This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0026] Figure 6 This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0027] Figure 7 This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0028] Figure 8 This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0029] Figure 9This is a schematic diagram illustrating an exemplary pipeline structure for executing the SHA-256 algorithm;

[0030] Figure 10 It is shown Figure 9 A schematic diagram of the first example of the extended register module of the arithmetic stage and the extended data operation module between adjacent arithmetic stages in the pipeline structure;

[0031] Figure 11 It is shown Figure 9 A schematic diagram of a second example of the extended register module of the arithmetic stage and the extended data operation module between adjacent arithmetic stages in the pipeline structure;

[0032] Figure 12 It is shown Figure 9 A schematic diagram of the third example of the extended register module of the arithmetic stage and the extended data operation module between adjacent arithmetic stages in the pipeline structure;

[0033] Figure 13 This is a schematic block diagram illustrating a circuit for performing a hash algorithm according to some embodiments of the present disclosure;

[0034] Figure 14 This is a schematic block diagram illustrating a circuit for performing a hash algorithm according to some embodiments of the present disclosure;

[0035] Figure 15 It is shown Figure 14 A schematic diagram of a first example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown;

[0036] Figure 16A and Figure 16B It is shown Figure 14 A schematic diagram of a second example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown;

[0037] Figure 17A and Figure 17B It is shown Figure 14 The diagram shows a third example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown.

[0038] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0039] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0040] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0041] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they are merely illustrative of exemplary ways that can be used to implement the invention, and not exhaustive.

[0042] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0043] Figure 1 These are schematic diagrams of the operational circuit 10 in some examples. For example... Figure 1 As shown, the arithmetic circuit 10 includes a summing module 12. The summing module 12 is configured to sum a first number a and a second number b, thereby producing a sum s and a carry c. The arithmetic circuit 10 also includes an arithmetic module 11, which is coupled before the summing module 12 and configured to perform the operation to produce the first number a and the second number b. For example, the summing module 12 can be implemented as an adder (ADD), while the arithmetic module 11 can be implemented as a combinational logic circuit. Generally, an ADD can have two inputs and one output, thus reducing one operand; however, an ADD has more stages, more glitches, a larger area, and higher power consumption. Especially when the input of the ADD comes from a combinational logic circuit, the adder has high power consumption due to high glitches.

[0044] To this end, this disclosure provides an adder circuit that can have reduced or even eliminated glitches, thereby achieving lower power consumption. Circuits according to various embodiments of this disclosure are described in detail below with reference to the accompanying drawings. It should be understood that actual circuits may include other additional components, but to avoid obscuring the essential points of this disclosure, these additional components are not discussed herein and are not shown in the drawings.

[0045] Figure 2This is a schematic diagram of an adder circuit 100 according to some embodiments of the present disclosure. For example, the adder circuit 100 is configured to calculate the sum of a first number a and a second number b. The adder circuit 100 may have a first input representing the first number a and a second input representing the second number b, and an output representing the sum s of the first number a and the second number b. Each of the first input a and the second input b is correspondingly divided to include a first portion and a second portion, the first portion and the second portion representing the portion bits of the input from the least significant bit to the most significant bit. For example, the first input a includes a first portion a1 and a second portion a2, and the second input b includes a first portion b1 and a second portion b2.

[0046] like Figure 2 As shown, the adder circuit 100 includes a first register module 102, a second register module 104, a third register module 106, a first adder 122, and a second adder 124. The first register module 102 is configured to store the second portion a2 of the first input a. The second register module 104 is configured to store the second portion b2 of the second input b. The first adder 122 is configured to sum the first portion a1 of the first input a and the first portion b1 of the second input b, thereby generating a first sum s1 and a first carry c1. The third register module 106 is coupled to the first adder 122 and is configured to store the first carry c1. The second adder 124 is coupled to the first register module 102, the second register module 104, and the third register module 106 and is configured to sum the second portion a2 of the first input a, the second portion b2 of the second input b, and the first carry c1, thereby generating a second sum s2. The first sum s1 and the second sum s2 represent the portions of the output s from the least significant bit to the most significant bit.

[0047] In some examples, such as reference Figure 3 The adder circuit 100 also includes a fourth register module 108, which is coupled to the first adder 122 and configured to store the first sum s1.

[0048] Each of the first through fourth register modules 102-108 can, for example, be implemented as a combination of single-bit registers. The number of single-bit registers included in each register module can depend on the number of bits that the register module is to store. In some examples, the first and second portions of each of the first input a and the second input b have the same number of bits. This can, in some cases, make the adder circuit 100 suitable for use in pipelined structures (e.g., as discussed later). Figure 15 to Figure 17BThe described method has a smaller computational latency. In some examples, the number of bits in the first part of each of the first inputs a and the second input b is greater than the number of bits in the second part of that input. This can, for example, reduce the number of single-bit registers required. In some examples, the number of bits in the first part of each of the first inputs a and the second input b is less than the number of bits in the second part of that input.

[0049] Therefore, with Figure 1 In contrast, adder circuit 100 breaks down a large-scale adder into two smaller-scale adders. The input to the second adder 124 comes from a register, thus enabling glitch reduction or even elimination (e.g., by fine-tuning the register clock or register drive). The second adder 124 has a generous setup time of up to a full cycle and very small glitch, resulting in reduced power consumption. Furthermore, the total area of ​​the first adder 122 and the second adder 124 can be smaller than [previous value missing]. Figure 1 The area of ​​the adder in the summing module 12 is reduced, thus enabling lower power consumption. Generally, the area of ​​a 32-bit adder may be equivalent to the area of ​​three 16-bit adders.

[0050] When each input consists of a first part and a second part (i.e., a = [a2, a1] and b = [b2, b1]), the output consists of a first sum and a second sum (i.e., s = [s2, s1]). In this case, the second carry c2 output from the second adder 124 can be discarded. It is understood that in some other examples, the individual inputs can also be divided into three or more parts corresponding to each other. In these examples, the adder circuit 100 can be modified accordingly based on the teachings of this disclosure. For example, refer to... Figure 4 , and Figure 2 In contrast, each input is divided into three parts. The first, second, and third parts of each input represent the parts of the input from the least significant bit to the most significant bit, i.e., a = [a3, a2, a1] and b = [b3, b2, b1]. For example... Figure 4As shown, the adder circuit 100' further includes a fourth register module 110, a fifth register module 112, a sixth register module 114, and a third adder 126 compared to the adder circuit 100. The fourth register module 110 is configured to store the third portion a3 of the first input a. The fifth register module 112 is configured to store the third portion b3 of the second input b. The second adder 124 sums the second portion a2 of the first input a, the second portion b2 of the second input b, and the first carry c1 to generate a second sum s2 and a second carry c2. The sixth register module 114 is coupled to the second adder 124 and configured to store the second carry c2. The third adder 126 is coupled to the fourth register module 110, the fifth register module 112, and the sixth register module 114 and is configured to sum the third portion a3 of the first input a, the third portion b3 of the second input b, and the second carry c2 to generate a third sum s3. The first sum s1, the second sum s2, and the third sum s3 represent the parts of the output s from the least significant bit to the most significant bit, i.e., s = [s3, s2, s1]. In this case, the third carry c3 output from the third adder 126 can be discarded.

[0051] Figure 5 An operational circuit 200 according to some embodiments of the present disclosure is shown. For example... Figure 5 As shown, the arithmetic circuit 200 includes a summing module 220 and a first arithmetic module 210 coupled to the summing module 220. The summing module 220 may include the addition circuit 100 (including 100') described in any of the foregoing embodiments. The first arithmetic module 210 may provide a first input and a second input to the addition circuit 100.

[0052] Figure 6 to Figure 8 They are shown respectively Figure 5 Several non-limiting example configurations of the operational circuit 200 are shown. Figure 6 to Figure 8 In the example shown, the addition circuit included in the summation module 220 is depicted as follows: Figure 3 The adder circuit 100 is shown, but this is for illustrative purposes only and is not intended to be limiting.

[0053] In some examples, the arithmetic circuit 200 includes multiple arithmetic stages. For example, these arithmetic stages can be arranged in a pipelined structure. Each arithmetic stage can include a corresponding register module.

[0054] like Figure 6As shown, the multiple operation stages of the arithmetic circuit 200 include a first operation stage 230a and a second operation stage 230b immediately following the first operation stage 230a. The first operation stage 230a includes a first corresponding register module 232a. The second operation stage 230b includes a second corresponding register module 232b, and also includes first to fourth register modules 102-108 of the adder circuit of the summation module 220. A first operation module 210 is arranged between the first operation stage 230a and the second operation stage 230b and coupled to the first corresponding register module 232a of the first operation stage 230a. For example, the first operation module 210 can be configured to perform operations on data from the first corresponding register module 232a to generate a first input and a second input of the adder circuit of the summation module 220. In addition, the first adder 122 of the adder circuit of the summation module 220 can also be arranged between the first operation stage 230a and the second operation stage 230b.

[0055] like Figure 7 As shown, in some examples, the multiple operational stages of the arithmetic circuit 200 also include a third operational stage 230c immediately following the second operational stage 230b. The third operational stage 230c includes a third corresponding register module 232c. The third corresponding register module 232c of the third operational stage 230c can be coupled to the summing module 220 to receive the output of its adder circuit. For example, the second adder 124 of the adder circuit of the summing module 220 can be arranged between the second operational stage 230b and the third operational stage 230c.

[0056] like Figure 8 As shown, in some examples, the arithmetic circuit 200 further includes a second arithmetic module 240 disposed between the second arithmetic stage 230b and the third arithmetic stage 230c. The second arithmetic module 240 may be coupled to a second corresponding register module 232b of the second arithmetic stage 230b and configured to perform operations on data from the second corresponding register module 232b. For example, the second arithmetic module 240 may have the same configuration as the first arithmetic module 210.

[0057] In some examples, the arithmetic circuit 200 may also include another summing module 220', which may have the same configuration as the summing module 220. In such an example, the third arithmetic stage 230c may further include first to fourth register modules 102-108 of the summing module 220'. The second arithmetic module 240 may be coupled to the summing module 220' to provide the first and second inputs of its adder circuit. The second arithmetic module 240 may be configured to perform operations on data from the second corresponding register module 232b to produce the first and second inputs of the adder circuit of the summing module 220'. The first adder 122 of the adder circuit of the summing module 220' may also be arranged between the second arithmetic stage 230b and the third arithmetic stage 230c.

[0058] Although not shown, the first operational stage 230a may also include the first to fourth register modules of the adder circuit of another summing module, and the second adder of the adder circuit of this other summing module may also be arranged between the first operational stage 230a and the second operational stage 230b. That is, the internal configuration of each operational stage of the operational circuit 200 and the configuration between adjacent operational stages may be the same.

[0059] To present the inventive concept of this disclosure more clearly and intuitively, the SHA-256 algorithm will be briefly introduced below, and its use as a representative example of a hash algorithm will be used to describe the circuitry for executing the hash algorithm according to embodiments of this disclosure. Those skilled in the art will understand that the circuitry for executing the hash algorithm according to embodiments of this disclosure is applicable to any hash algorithm and can even be further applied to any other suitable circuitry, and is not limited to implementing the SHA-2 series algorithms such as the SHA-256 algorithm.

[0060] Figure 9 A schematic diagram of an exemplary pipeline structure for performing the SHA-256 algorithm is shown. The input to SHA-256 is a maximum length less than 2. 64 The input data is processed in 512-bit blocks, and the output is a 256-bit data digest, i.e., a hash value. To implement the SHA-256 algorithm, 64 rounds of repeated computation are required for each 512-bit data block. Therefore, a pipelined architecture with 64 computation stages can be used to process 64 sets of data in parallel. Figure 9 As shown, the pipeline architecture includes operation stages 0 to 63. Each operation stage includes eight 32-bit compressed register modules A to H for storing intermediate values ​​and sixteen 32-bit extended register modules R0 to R1 for storing extended data. 15The 0th operation stage receives the input data block, divides it into eight 32-bit data segments, stores them in compression register modules A through H, processes them, and then provides the results to the 1st operation stage. Afterward, each operation stage processes the results received from the previous stage and provides its own result to the next stage. Finally, after 64 operation stages, this pipeline structure outputs the hash result of the input data having undergone one SHA-256 algorithm operation.

[0061] The internal logic of a round of operations performed by SHA-256 at each operational level is discussed in detail below. The t-th round of operations performed at the t-th operational level is defined by the following formula (t is an integer and satisfies 0 ≤ t ≤ 63):

[0062] T1 = H + Σ1(E) + Ch(E, F, G) + K t + W t ;

[0063] T2 = Σ0(A) + Maj(A, B, C);

[0064] H = G;

[0065] G = F;

[0066] F = E;

[0067] E = D + T1;

[0068] D = C;

[0069] C = B;

[0070] B = A;

[0071] A = T1 + T2; (Equation 1)

[0072] in:

[0073] Ch(x, y, z)=(x AND y) ⊕ ((NOT x) AND z)

[0074] Maj(x, y, z)= (x AND y) ⊕ (x AND z) ⊕ (y AND z)

[0075] Σ0(x)=ROTR 2 (x) ⊕ ROTR 13 (x) ⊕ ROTR 22 (x)

[0076] Σ1(x)=ROTR 6(x) ⊕ ROTR 11 (x) ⊕ ROTR 25 (x)

[0077] Among them, ROTR n (x) represents a circular right shift of n bits on a 32-bit variable x; W t For a 32-bit word, derived from the current 256-bit input data block; K t A 32-bit additional constant; + indicates modulo 2. 32 Add; AND is a 32-bit bitwise AND operation; NOT is the negation operation; ⊕ is the XOR operation.

[0078] Next, we will describe the 32-bit word W. t How was it derived from a 512-bit data block? t It can be obtained using the following formula:

[0079] For 0 ≤ t ≤ 15: W t Taken directly from the input data block;

[0080] For 16 ≤ t ≤ 63:

[0081] W t =σ1(W t-2 ) + W t-7 + σ0(W t-15 ) + W t-16 (Equation 2)

[0082] in:

[0083] σ0(x) = ROTR 7 (x) ⊕ ROTR 18 (x) ⊕ SHR 3 (x)

[0084] σ1(x) = ROTR 17 (x) ⊕ ROTR 19 (x) ⊕ SHR 10 (x)

[0085] Among them, ROTR n (x) represents a circular right shift of n bits on a 32-bit variable x; SHR n (x) represents shifting the 32-bit variable x to the right by n bits, filling the left side with 0s; ⊕ is the XOR operation; + is the modulo 2 operation. 32 add.

[0086] Note that the formulas for the functions Σ0(x), Σ1(x), σ0(x), and σ1(x) above are given as examples of SHA-256 for processing 32-bit data. Those skilled in the art know that in other SHA algorithms (such as SHA-512) and even other hash algorithms, these functions can be adapted to other corresponding forms to process data of other sizes (such as 64-bit data).

[0087] The following is combined Figure 10 to Figure 12 describe Figure 9 This section provides several non-restricted example configurations of the extended register modules in the arithmetic stages and the extended data operation modules between adjacent arithmetic stages within the pipelined architecture. It is understood that... Figure 10 to Figure 12 Some extended register modules and extended data operation modules are depicted in gray for illustrative purposes only and are not intended to be restrictive.

[0088] Figure 10 It is shown Figure 9 A schematic diagram of the first example of the extended register module of the operation stage and the extended data operation module between adjacent operation stages in the pipeline structure.

[0089] refer to Figure 10 It requires the use of extended register modules R0, R1, R9, and R1 for each arithmetic stage. 14 The extended data in the calculation is used to calculate the extended register module R to be stored in the next operation stage. 15 Extended data in, and additional extended register modules R1 to R 15 The extended data in the register can be directly shifted to the corresponding extended register module R0 to R1 in the next operation stage. 14 In the middle. Specifically, the extended register module R of the (t+1)th operation level. 15 Extended data W15 in t+1 The 0th extended data W0 in the extended register module R0 of the t-th operation stage is processed by two 32-bit full adders FAA1 and FAA2 and one 32-bit adder ADD. t The first extended data W1 in the extended register module R1 of the t-th operation level t The σ0(W1) obtained after the σ0 operation is performed by the σ0 operator t The 9th extended data W9 in the extended register module R9 of the t-th operation level. t The extended register module R at the t-th operation level 14 Extended data W14 in t The σ1(W14) obtained after σ1 operation by the σ1 operator t The result is obtained by adding them together, i.e., W15. t+1 =W0 t +σ0(W1t )+W9 t +σ1(W14 t As can be seen, from the extended register modules R0, R1, R9, and R at the t-th operation level... 14 The 0th extended data W0 t Extended Data W1 t Extended Data W9, No. 9 t Extended Data 14 W14 t The calculations need to be stored in the extended register module R of the next operation stage. 15 Extended data W15 in t+1 The computational logic stages required are as high as four, which leads to significant computational latency, limits the computational speed of the pipeline structure, and makes it difficult to achieve a low power consumption-to-computing power ratio.

[0090] In this regard, the inventors of this application noted that there is a direct connection between the extended register module R0 of the (t+1)th operation level and the extended register module R1 of the tth operation level; that is, the extended data stored in the extended register module R1 of the tth operation level is directly shifted to the extended register module R0 of the (t+1)th operation level. Therefore, the inventors of this application conceived of using this direct connection between the extended register modules R0 and R1 to transfer the extended register module R0 used for calculating the (t+2)th operation level... 15 During the process of storing extended data, the portion of the extended data in the extended register module R0 of the (t+1)th operation level (i.e., the extended data in the extended register module R1 of the t-th operation level) is moved forward to the extended register module R1 used for calculating the (t+1)th operation level. 15 The process of storing the extended data is performed simultaneously and stored in the extended register module R0 of the (t+1)th operation level. In this way, the extended register module R0 used for calculating the (t+2)th operation level can be used... 15 After decomposing the process of storing the extended data, the decomposed parts are combined with the extended register module R used to calculate the (t+1)th operation level. 15 The process of storing extended data is handled in parallel. Parallel processing reduces the number of logical operation stages required to compute the extended data in each round, thereby increasing the processing speed of the circuit and the computing chip containing it, facilitating a lower power-to-computing power ratio. Specifically, the 15th extended register module R of the (t+2)th operation stage... 15 The 15th extended data W15 stored in the middle t+2 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t The second extended data W2 is stored in the second extended register module R2 of the t-th operation level. t The 10th extended register module R of the t-th operation level10 The 10th extended data W10 stored in the middle t and the 15th extended register module R of the t-th operation level 15 The 15th extended data W15 stored in the middle t The following relationship can be satisfied: W15 t+2 =W1 t +σ0(W2 t )+W10 t +σ1(W15 t ), where the definitions of σ0, σ1, and + are as described above.

[0091] For example, it can be based on the second extended register module R2 and the tenth extended register module R at the t-th operation level. 10 15th Extended Register Module R 15 The extended data to be stored in the 0th extended register module R0 of the (t+1)th operation level is calculated based on the extended data stored in one or both of the extended register modules and the extended data stored in the 1st extended register module R1 of the t-th operation level. Alternatively, the extended data can be calculated based on the 1st extended register module R1, the 9th extended register module R9, and the 14th extended register module R0 of the t-th operation level. 14 The extended data stored in one or both of these registers, along with the extended data stored in the 0th extended register module R0 of the t-th operation level, are used to calculate the data to be stored in the 15th extended register module R of the (t+1)-th operation level. 15 Extended data within.

[0092] Figure 11 It is shown Figure 9 A schematic diagram of a second example of the extended register module of the operation stage and the extended data operation module between adjacent operation stages in the pipeline structure.

[0093] like Figure 11 As shown, the 0th extended data W0 in the 0th extended register module R0 of the (t+1)th operation stage t+1 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t and the second extended data W2 stored in the second extended register module R2 t Obtained. Specifically, in this example, W0 t+1 =W1 t +σ0(W2 t ).

[0094] Further as Figure 11 As shown, the 15th extended register module R of the (t+1)th operation level 15 Extended data W15 in t+1The 0th extended data W0 is stored in the 0th extended register module R0 of the t-th operation level. t The 9th extended data W9 is stored in the 9th extended register module R9. t and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t Obtained. Specifically, in this example, W15 t+1 =W0 t +W9 t + σ1(W14 t ).

[0095] Further as Figure 11 As shown, the extended data stored in the i-th extended register module of the t-th operation level is directly shifted to the (i-1)-th extended register module of the (t+1)-th operation level, where 2≤i≤15 and i is an integer.

[0096] exist Figure 11 In the example shown, the number of computational logic stages required to finally compute the extended data for the (t+1)th operation stage is reduced to 3, which greatly reduces computational latency and significantly improves the computational speed of the pipeline structure.

[0097] The extended data operation module between the (t+1)th operation level and the (t+2)th operation level can be the same as the extended data operation module between the t-th operation level and the (t+1)th operation level. Further, as... Figure 11 As shown, the 15th extended register module R of the (t+2)th operation stage 15 Extended data W15 in t+2 The 0th extended data W0 is stored in the 0th extended register module R0 of the (t+1)th operation level. t+1 The 9th extended data W9 is stored in the 9th extended register module R9. t+1 and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t+1 Resulting. Specifically, in this example, W15 t+2 =W0 t+1 +W9 t+1 +σ1(W14 t+1 )=W1 t +σ0(W2 t )+W10 t +σ1(W15 t ).

[0098] Figure 12 It is shown Figure 9 A schematic diagram of the third example of the extended register module of the operation stage and the extended data operation module between adjacent operation stages in the pipeline structure.

[0099] like Figure 12 As shown, the 0th extended data W0 in the 0th extended register module R0 of the (t+1)th operation stage t+1 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t and the 10th extended register module R 10 The 10th extended data W10 stored in the middle t Obtained. Specifically, in this example, W0 t+1 =W1 t +W10 t .

[0100] Further as Figure 12 As shown, the 15th extended register module R of the (t+1)th operation level 15 Extended data W15 in t+1 The 0th extended data W0 is stored in the 0th extended register module R0 of the t-th operation level. t The first extended data W1 stored in the first extended register module R1 t and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t Resulting. Specifically, in this example, W15 t+1 =W0 t +σ0(W1 t )+ σ1(W14 t ).

[0101] Further as Figure 12 As shown, the extended data stored in the i-th extended register module of the t-th operation level is directly shifted to the (i-1)-th extended register module of the (t+1)-th operation level, where 2≤i≤15 and i is an integer.

[0102] exist Figure 12 In the example shown, the number of computational logic stages required to finally compute the extended data for the (t+1)th operation stage is reduced to 3, which greatly reduces computational latency and significantly improves the computational speed of the pipeline structure.

[0103] The extended data operation module between the (t+1)th operation level and the (t+2)th operation level can be the same as the extended data operation module between the t-th operation level and the (t+1)th operation level. Further, as... Figure 12 As shown, the 15th extended register module R of the (t+2)th operation stage 15 Extended data W15 in t+2 The 0th extended data W0 is stored in the 0th extended register module R0 of the (t+1)th operation level. t+1The first extended data W1 stored in the first extended register module R1 t+1 and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t+1 Resulting. Specifically, in this example, W15 t+2 =W0 t+1 +σ0(W1 t+1 )+σ1(W14 t+1 )=W1 t +σ0(W2 t )+W10 t +σ1(W15 t ).

[0104] In addition, in some examples, W0 t+1 =W1 t +σ1(W15 t And W15 t+1 =W0 t +σ0(W1 t )+W9 t Therefore, W15 t+2 =W0 t+1 +σ0(W1 t+1 )+W9 t+1 =W1 t +σ0(W2 t )+W10 t +σ1(W15 t This can be used as a reference. Figure 11 to Figure 12 The configuration is implemented similarly, so I won't go into details here.

[0105] exist Figure 10 to Figure 12 In some configurations, the input to the adder comes from combinational logic circuits. For example, Figure 10 The input of adder ADD in the code comes from full adder FAA2, and Figure 11 and Figure 12 The input to adder ADD1 in each of them comes from full adder FAA. Therefore, these configurations exist similar to Figure 1 The problem with the illustrated arithmetic circuit is that the adder has high power consumption due to glitches. Therefore, these configurations can be modified for applications according to the teachings of this disclosure to achieve a pipelined structure with reduced power consumption.

[0106] Figure 13A circuit 300 for performing a hash algorithm according to some embodiments of the present disclosure is shown, where arrows indicate the direction of data transmission. The circuit 300 may include an input unit 310 and an arithmetic unit 320. The input unit 310 may be configured to receive data. The arithmetic unit 320 may be configured to calculate a hash value based on the received data. The arithmetic unit 320 may include a plurality of arithmetic stages 320-0, ..., 320-63 arranged in a pipelined structure. Each arithmetic stage may include an extended register module configured to store extended data. For example, the extended register module may be implemented as a combination of single-bit registers. It should be understood that although the arithmetic unit 320 is depicted in the figures as including 64 arithmetic stages, as mentioned above, this document only provides a non-limiting example of a circuit for performing the SHA-256 algorithm, and the circuit according to the present disclosure can actually be applied to perform any hash algorithm now known or later developed (not limited to the SHA family of algorithms), and may include any suitable number of arithmetic stages. It should also be understood that the actual circuit may have additional components (such as a compression register module), but to avoid obscuring the key points of this disclosure, these other components are not shown in the accompanying drawings and are not discussed herein. Typically, the extended data of the first operational stage 320-0 of the arithmetic unit 320 can be directly taken from the data received by the input unit 310, for example, while the extended data of each operational stage starting from operational stage 320-1 can be determined, for example, based on the extended data of the previous operational stage.

[0107] Generally, the extended register modules of each of the multiple arithmetic stages 320-0, ..., 320-63 can have the same configuration. In some cases, the extended register modules of each of the multiple arithmetic stages 320-0, ..., 320-63 can have different configurations. For example, there may be one or more arithmetic stages that have one or more fewer extended register modules than other arithmetic stages. This disclosure is not limited to any of the above situations.

[0108] like Figure 13 As shown, the multiple operation stages 320-0, ..., 320-63 include a first operation stage 320-a and a second operation stage 320-b immediately following the first operation stage 320-a. In this paper, the operation stage that comes first among two adjacent operation stages in the pipeline structure can be referred to as the first operation stage, and the operation stage that comes later among two adjacent operation stages can be referred to as the second operation stage. Note that "first" and "second" are used only for distinction and not as a limitation.

[0109] Each of the first operational level 320-a and the second operational level 320-b includes extended register modules R0 to R15, respectively configured to store extended data from the 0th to the 15th extensions of that operational level. 15The 15th extended register module includes the first sum register submodule R. 15s1 First carry register submodule R 15c1 The second sum register submodule R 15s2 Second base register submodule R 15c2 .

[0110] Further as Figure 13 As shown, circuit 100 further includes a first extended data processing module 330-a disposed between the first operational stage 320-a and the second operational stage 320-b. The first extended data processing module 330-a includes a first submodule 331 and a second submodule 332.

[0111] The first submodule 331 of the first extended data processing module 330-a can be configured to be based on the 0th extended data W0 of the first processing level 320-a. a And based on the first extended data W1 of the first operation level 320-a a Extended Data W9, No. 9 a and the 14th extended data W14 a At least two of the initial sum s0 and initial carry c0 are calculated. Each of the initial sum s0 and initial carry c0 is partitioned correspondingly to include a first part and a second part, with the first part and the second part representing the portion bits of each part from the least significant bit to the most significant bit. For example, s0 = [s02, s01] and c0 = [c02, c01]. The second part s02 of the initial sum s0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 The first sum register submodule R 15s1 In the middle, and the second part c02 of the initial carry c0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 First carry register submodule R 15c1 middle.

[0112] The second submodule 332 of the first extended data operation module 330-a may include a first adder. The first adder can be configured to sum a first part s01 of the initial sum s0 and a first part c01 of the initial carry c0, thereby producing a first sum s1 and a first carry c1. The first sum s1 is stored in the 15th extended register module R of the second operation stage 320-b. 15 The second sum register submodule R 15s2 In the middle, and the first carry c1 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Second carry register submodule R 15c2 middle.

[0113] In some examples, such as reference Figure 14 The multiple operation levels 320-0, ..., 320-63 also include a third operation level 320-c immediately following the second operation level 320-b. The third operation level 320-c includes a 14th extended data W14 configured to store this operation level. c 14th Extended Register Module R 14 Circuit 300 also includes a second extended data processing module 330-b disposed between the second operational stage 320-b and the third operational stage 320-c. The second extended data processing module 330-b includes a third submodule 333.

[0114] The third submodule 333 of the second extended data operation module 330-b may include a second adder. The second adder is configured to sum the second part s02 of the initial sum s0, the second part c02 of the initial carry c0, and the first carry c1, thereby generating a second sum s2. The second sum s2 is stored in the 14th extended register module R of the third operation stage 320-c. 14 In the middle. For example, the first sum s1 can be obtained from the 15th extended register module R of the second operation level 320-b. 15 The second sum register submodule R 15s2 Shift to the 14th extended register module R of the third arithmetic stage 320-c 14 middle.

[0115] Figure 15 to Figure 17B The following are examples of applying the teachings of this disclosure to... Figure 10 to Figure 12 Several non-restrictive example configurations are obtained by making corresponding modifications. This is understandable. Figure 15 to Figure 17B The grayed-out depiction of some extended register modules and extended data operation modules is for illustrative purposes only and is not intended to be restrictive. Figure 15 to Figure 17B In the example shown, each operation level can have the same configuration both internally and between adjacent operation levels.

[0116] like Figure 15 As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ0 operator, a σ1 operator, and two full adders FAA1 and FAA2, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W1 a Extended Data W9, No. 9 a and the 14th extended data W14 aCalculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into a first part and a second part, with the first part and the second part representing the portion bits of each part from the least significant bit to the most significant bit. For example, s0 = [s02, s01] and c0 = [c02, c01]. The second part s02 of the initial sum s0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 The first sum register submodule R 15s1 In the middle, and the second part c02 of the initial carry c0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 First carry register submodule R 15c1 middle.

[0117] The second submodule 332 of the first extended data operation module 330-a includes a first adder ADD1. The first adder ADD1 is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0, thereby generating a first sum s1 and a first carry c1. The first sum s1 is stored in the 15th extended register module R of the second operation level 320-b. 15 The second sum register submodule R 15s2 In the middle, and the first carry c1 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Second carry register submodule R 15c2 middle.

[0118] The third submodule 333 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes a second adder ADD2. The second adder ADD2 is configured to sum the second part s02 of the initial sum s0, the second part c02 of the initial carry c0, and the first carry c1, thereby producing a second sum s2. The second sum s2 is stored in the 14th extended register module R of the third operation level 320-c. 14 In addition, the first sum s1 is transferred from the 15th extension register module R of the second operation stage 320-b. 15 The second sum register submodule R 15s2 Shift to the 14th extended register module R of the third arithmetic stage 320-c 14 middle.

[0119] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W1 aExtended Data W9, No. 9 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +σ0(W1 a +W9 a +σ1(W14 a ).

[0120] Figure 15 and Figure 10 In comparison, although calculating "W0" a +σ0(W1 a +W9 a +σ1(W14 a This requires an extra round of processing time, but it has no significant negative impact on the assembly line structure. Additionally, Figure 15 Broken Figure 10 The SHA-256 algorithm has an operand limit of 32 bits. Figure 10 The ADD, implemented as a 32-bit adder, is in Figure 15 Instead, it is implemented as two adders, ADD1 and ADD2 (for example, each could be a 16-bit adder, or a combination of a 15-bit adder and a 17-bit adder, or a combination of an 18-bit adder and a 14-bit adder, etc., without particular limitation). Although Figure 15 The 15th extended register module R of the arithmetic stage 15 The number of single-bit registers included may be greater than Figure 10 The 15th extended register module R of the arithmetic stage 15 It includes more single-bit registers (for example, if adders ADD1 and ADD2 are each 16-bit adders, there might be 17 more), but Figure 15 The total area of ​​ADD1 and ADD2 is less than Figure 10 The total area of ​​the ADD, and Figure 15 The input to ADD2 comes from a register, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. Therefore, Figure 15 A significant reduction in adder area / glitch power consumption is achieved at the cost of acceptable register area power consumption.

[0121] like Figure 16A and Figure 16B As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ1 arithmetic unit and a full adder FAA, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W9, No. 9a and the 14th extended data W14 a Calculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into a first part and a second part, with the first part and the second part representing the portion bits of each part from the least significant bit to the most significant bit. For example, s0 = [s02, s01] and c0 = [c02, c01]. The second part s02 of the initial sum s0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 The first sum register submodule R 15s1 In the middle, and the second part c02 of the initial carry c0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 First carry register submodule R 15c1 middle.

[0122] The second submodule 332 of the first extended data operation module 330-a includes a first adder ADD1. The first adder ADD1 is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0, thereby generating a first sum s1 and a first carry c1. The first sum s1 is stored in the 15th extended register module R of the second operation level 320-b. 15 The second sum register submodule R 15s2 In the middle, and the first carry c1 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Second carry register submodule R 15c2 middle.

[0123] The third submodule 333 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes a second adder ADD2. The second adder ADD2 is configured to sum the second part s02 of the initial sum s0, the second part c02 of the initial carry c0, and the first carry c1, thereby producing a second sum s2. The second sum s2 is stored in the 14th extended register module R of the third operation level 320-c. 14 In addition, the first sum s1 is transferred from the 15th extension register module R of the second operation stage 320-b. 15 The second sum register submodule R 15s2 Shift to the 14th extended register module R of the third arithmetic stage 320-c 14 middle.

[0124] Additionally, the 0th extended data W0 of the first operational level 320-a aThe first extended data W1 of the fourth operation level 320-d is obtained by the fourth submodule 334 (which includes a σ0 arithmetic unit and an adder ADD0) of the third extended data operation module 330-d, which is immediately preceding the first operation level 320-a and is located between the first operation level 320-a and the fourth operation level 320-d. d And the second extended data W2 d The calculated value is W0. a = W1 d +σ0(W2 d ).

[0125] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W9, No. 9 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +W9 a +σ1(W14 a In addition, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the first extended data W1 of the fourth operation level 320-d d Second extended data W2 d Extended Data W10 (10th Edition) d And the 15th extended data W15 d The following relationship can be satisfied: W14 c =W1 d +σ0(W2 d +W10 d +σ1(W15 d ), of which W15 d =[{W15s1 d + W15c1 d + W15c2 d},W15s2 d W15s1 d W15c1 d W15s2 d W15c2 d These are the 15th extended register module R of the fourth arithmetic level 320-d. 15 The first sum register submodule R 15s1 First carry register submodule R 15c1 The second sum register submodule R15s2 Second base register submodule R 15c2 The data stored in it.

[0126] Figure 16A and Figure 11 In comparison, although calculating "W1" d +σ0(W2 d +W10 d +σ1(W15 d This requires an extra round of processing time, but it doesn't have a significant negative impact on the assembly line structure. Additionally, Figure 16A Broken Figure 11 The SHA-256 algorithm has an operand limit of 32 bits. Figure 11 ADD1, implemented as a 32-bit adder, is in Figure 16A Instead, it is implemented as two adders, ADD1 and ADD2 (for example, each could be a 16-bit adder, or a combination of a 15-bit adder and a 17-bit adder, or a combination of an 18-bit adder and a 14-bit adder, etc., without particular limitation). Although Figure 16A The 15th extended register module R of the arithmetic stage 15 The number of single-bit registers included may be greater than Figure 11 The 15th extended register module R of the arithmetic stage 15 It includes more single-bit registers (for example, if adders ADD1 and ADD2 are each 16-bit adders, there might be 17 more), but Figure 16A The total area of ​​ADD1 and ADD2 is less than Figure 11 The total area of ​​ADD1, and Figure 11 The input to ADD2 comes from a register, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. Therefore, Figure 16A A significant reduction in adder area / glitch power consumption is achieved at the cost of acceptable register area power consumption.

[0127] like Figure 17A and Figure 17B As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ0 operator, a σ1 operator, and a full adder FAA, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W1 a and the 14th extended data W14 aCalculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into a first part and a second part, with the first part and the second part representing the portion bits of each part from the least significant bit to the most significant bit. For example, s0 = [s02, s01] and c0 = [c02, c01]. The second part s02 of the initial sum s0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 The first sum register submodule R 15s1 In the middle, and the second part c02 of the initial carry c0 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 First carry register submodule R 15c1 middle.

[0128] The second submodule 332 of the first extended data operation module 330-a includes a first adder ADD1. The first adder ADD1 is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0, thereby generating a first sum s1 and a first carry c1. The first sum s1 is stored in the 15th extended register module R of the second operation level 320-b. 15 The second sum register submodule R 15s2 In the middle, and the first carry c1 is stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Second carry register submodule R 15c2 middle.

[0129] The third submodule 333 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes a second adder ADD2. The second adder ADD2 is configured to sum the second part s02 of the initial sum s0, the second part c02 of the initial carry c0, and the first carry c1, thereby producing a second sum s2. The second sum s2 is stored in the 14th extended register module R of the third operation level 320-c. 14 In addition, the first sum s1 is transferred from the 15th extension register module R of the second operation stage 320-b. 15 The second sum register submodule R 15s2 Shift to the 14th extended register module R of the third arithmetic stage 320-c 14 middle.

[0130] Additionally, the 0th extended data W0 of the first operational level 320-a aThe fourth submodule 334 (which includes an adder ADD0) of the third extended data operation module 330-d, which is located between the fourth operation stage 320-d and the first operation stage 320-a, is based on the first extended data W1 of the fourth operation stage 320-d. d and the 10th extended data W10 d The calculated value is W0. a = W1 d +W10 d .

[0131] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W1 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +σ0(W1 a ) +σ1(W14 a In addition, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the first extended data W1 of the fourth operation level 320-d d Second extended data W2 d Extended Data W10 (10th Edition) d And the 15th extended data W15 d The following relationship can be satisfied: W14 c =W1 d +σ0(W2 d +W10 d +σ1(W15 d ), of which W15 d =[{W15s1 d +W15c1 d +W15c2 d},W15s2 d W15s1 d W15c1 d W15s2 d W15c2 d These are the 15th extended register module R of the fourth arithmetic level 320-d. 15 The first sum register submodule R 15s1 First carry register submodule R 15c1 The second sum register submodule R15s2 Second base register submodule R 15c2 The data stored in it.

[0132] Figure 17A and Figure 12 In comparison, although calculating "W1" d +σ0(W2 d +W10 d +σ1(W15 d This requires an extra round of processing time, but it doesn't have a significant negative impact on the assembly line structure. Additionally, Figure 17A Broken Figure 12 The SHA-256 algorithm has an operand limit of 32 bits. Figure 12 ADD1, implemented as a 32-bit adder, is in Figure 17A Instead, it is implemented as two adders, ADD1 and ADD2 (for example, each could be a 16-bit adder, or a combination of a 15-bit adder and a 17-bit adder, or a combination of an 18-bit adder and a 14-bit adder, etc., without particular limitation). Although Figure 17A The 15th extended register module R of the arithmetic stage 15 The number of single-bit registers included may be greater than Figure 12 The 15th extended register module R of the arithmetic stage 15 It includes more single-bit registers (for example, if adders ADD1 and ADD2 are each 16-bit adders, there might be 17 more), but Figure 17A The total area of ​​ADD1 and ADD2 is less than Figure 12 The total area of ​​ADD1, and Figure 17A The input to ADD2 comes from a register, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. Therefore, Figure 17A A significant reduction in adder area / glitch power consumption is achieved at the cost of acceptable register area power consumption.

[0133] In addition, it can be based on W0 t+1 =W1 t +σ1(W15 t W15 t+1 =W0 t +σ0(W1 t )+W9 t And W15 t+2 =W0 t+1 +σ0(W1 t+1 )+ W9 t+1 =W1 t +σ0(W2 t )+W10t +σ1(W15 t (This can be extended to other embodiments. For example, in some embodiments, the first submodule 331 of the first extended data processing module 330-a can be based on the 0th extended data W0 of the first processing level 120-a.) a Extended Data W1 a and the 9th extended data W9 a Calculate the initial sum and initial carry, then proceed to a similar manner. Figure 16A , Figure 17A The initial sum and initial carry are then processed as the first and second numbers by an addition circuit according to various embodiments of the teachings of this disclosure, which will not be elaborated here.

[0134] Alternatively, the initial sum and initial carry calculated by the first submodule 331 of the first extended data operation module 330-a can be divided into three or more parts corresponding to each other, similar to... Figure 4 That would take more rounds to obtain the sum of the initial sum and the initial carry, but this would not have a significant negative impact on the pipeline structure.

[0135] This disclosure may also provide a computing chip including the circuitry described in any of the above embodiments. This disclosure may also provide a computing device including the computing chip described above.

[0136] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing constant relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0137] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0138] As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any stated or implied theory given in the technical field, background art, summary of the invention, or detailed description. As used herein, the term "substantially" means to include any minor variations caused by design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0139] Additionally, terms such as “first,” “second,” etc., may be used herein for reference only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence. It should also be understood that the term “including / comprises” as used herein indicates the presence of the indicated feature, whole, step, operation, unit, and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components, and / or combinations thereof. In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “providing an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting,” “installing / assembling,” and / or “ordering” an object.

[0140] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0141] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0142] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. An addition circuit for calculating a sum of a first number and a second number, the addition circuit having a first input representing the first number and a second input representing the second number and having an output representing the sum of the first number and the second number, each of the first input and the second input being divided into a first part and a second part corresponding to each other to sequentially represent partial bits of the input from a low bit to a high bit, the addition circuit comprising: a first register module configured to store the second part of the first input; a second register module configured to store the second part of the second input; a first adder configured to sum the first part of the first input and the first part of the second input to generate a first sum and a first carry; a third register module coupled to the first adder and configured to store the first carry; and a second adder coupled to the first register module, the second register module, and the third register module to receive the second part of the first input, the second part of the second input, and the first carry from the first register module, the second register module, and the third register module, respectively, and configured to sum the second part of the first input, the second part of the second input, and the first carry to generate a second sum, wherein the first sum and the second sum sequentially represent partial bits of the output from a low bit to a high bit. The first part and the second part of each of the first input and the second input have the same number of bits.

2. The adder circuit of claim 1, wherein, The number of bits of the first part of each of the first input and the second input is greater than the number of bits of the second part of the input.

3. The adder circuit of claim 1, wherein, The number of bits of the first part of each of the first input and the second input is less than the number of bits of the second part of the input.

4. The adder circuit of claim 1, wherein, 5. The addition circuit of any one of claims 1 to 4, further comprising: a fourth register module coupled to the first adder and configured to store the first sum.

6. An arithmetic circuit comprising: a summing module including the addition circuit of any one of claims 1 to 5; and a first arithmetic module coupled to the summing module to provide the first input and the second input of the addition circuit.

7. The arithmetic circuit of claim 6, wherein: the addition circuit includes a fourth register module coupled to the first adder and configured to store the first sum, the arithmetic circuit includes a plurality of arithmetic stages, each of the plurality of arithmetic stages including a respective register module, and the plurality of arithmetic stages includes a first arithmetic stage and a second arithmetic stage immediately following the first arithmetic stage, the second arithmetic stage further including the first to fourth register modules of the addition circuit. ​ ​ The first operation module is arranged between the first operation stage and the second operation stage and is coupled to a first respective register module of the first operation stage, the first operation module being configured to operate on data from the first respective register module to produce a first input and a second input of the addition circuit, and A first adder of the addition circuit is arranged between the first operation stage and the second operation stage.

8. The operation circuit of claim 7, wherein, The plurality of operation stages further comprises a third operation stage immediately after the second operation stage, a third respective register module of the third operation stage being coupled to the summation module to receive an output of the addition circuit, and A second adder of the addition circuit is arranged between the second operation stage and the third operation stage.

9. The operation circuit of claim 8, further comprising: a second operation module arranged between the second operation stage and the third operation stage and coupled to a second respective register module of the second operation stage, the second operation module being configured to operate on data from the second respective register module.

10. The arithmetic circuit according to claim 9, wherein The summation module is a first summation module, the addition circuit is a first addition circuit, and the operation circuit further comprises: a second summation module comprising a second addition circuit, the second addition circuit being the addition circuit of claim 5, wherein the third operation stage further comprises first to fourth register modules of the second addition circuit, the second operation module being coupled to the second summation module to provide a first input and a second input of the second addition circuit, and being configured to operate on data from the second respective register module to produce the first input and the second input of the second addition circuit, and a first adder of the second addition circuit is arranged between the second operation stage and the third operation stage.

11. A circuit for performing a hash algorithm, comprising: an input portion configured to receive data; and an operation portion configured to compute a hash value based on the received data and comprising a plurality of operation stages arranged in a pipeline structure, wherein: the plurality of operation stages comprises a first operation stage and a second operation stage immediately after the first operation stage, each of the first operation stage and the second operation stage comprising a 0th to 15th extension register module respectively configured to store 0th to 15th extension data of the operation stage, the 15th extension register module comprising a first sum register sub-module, a first carry register sub-module, a second sum register sub-module and a second carry register sub-module, the circuit further comprises a first extension data operation module arranged between the first operation stage and the second operation stage, the first extension data operation module comprising a first sub-module and a second sub-module, the first sub-module being configured to operate on the 0th to 15th extension data of the first operation stage to produce a first input and a second input of the first addition circuit, and the second sub-module being configured to operate on the 0th to 15th extension data of the second operation stage to produce a first input and a second input of the second addition circuit. The first sub-module is configured to calculate an initial sum and an initial carry based on the 0th extension data of the first operation stage and based on at least two of the 1st, 9th and 14th extension data of the first operation stage, each of the initial sum and the initial carry is divided correspondingly to each other to include a first part and a second part, the first part and the second part sequentially represent partial bits of each of them from low to high, wherein the second part of the initial sum is stored in a first sum register sub-module of a 15th extension register module of a second operation stage, and the second part of the initial carry is stored in a first carry register sub-module of the 15th extension register module of the second operation stage, and The second sub-module includes a first adder configured to sum the first part of the initial sum and the first part of the initial carry, thereby generating a first sum and a first carry, the first sum is stored in a second sum register sub-module of the 15th extension register module of the second operation stage, and the first carry is stored in a second carry register sub-module of the 15th extension register module of the second operation stage.

12. The circuit of claim 11, wherein, The plurality of operation stages further includes a third operation stage immediately after the second operation stage, the third operation stage includes a 14th extension register module configured to store the 14th extension data of the operation stage, and The circuit further includes a second extension data operation module arranged between the second operation stage and the third operation stage, the second extension data operation module includes a third sub-module, and The third sub-module includes a second adder configured to sum the second part of the initial sum, the second part of the initial carry and the first carry, thereby generating a second sum, the second sum is stored in the 14th extension register module of the third operation stage.

13. The circuit of claim 12, wherein, The first sum is shifted from the second sum register sub-module of the 15th extension register module of the second operation stage into the 14th extension register module of the third operation stage.

14. A computing chip comprising the circuit according to any one of claims 1 to 13.

15. A computing device comprising the computing chip according to claim 14.

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