Silicon carbide power MOSFET and manufacturing method thereof

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide power MOSFET and a manufacturing method thereof. The silicon carbide power MOSFET provided by the invention comprises a substrate, a first epitaxial layer, a first CSL layer, a first P body region, a second epitaxial layer, a second CSL layer and a second P body region, a groove region is arranged between the two P body regions, a P + region is injected into the bottom of the groove, and an N + region is distributed on the side wall of the groove; specifically, the on-resistance is reduced through the double-layer CSL layer and the P body structure, the length of the JFET region is prolonged to limit the short-circuit current, the short-circuit tolerance time is remarkably prolonged, and the structure is suitable for the field of high-power and high-reliability power electronic devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a silicon carbide power MOSFET and a manufacturing method thereof. Background Art

[0002] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not necessarily be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art.

[0003] Power MOSFETs must carry high currents in the on-state and withstand high breakdown voltages in the off-state. Traditional silicon-based MOSFETs suffer from high on-resistance and high switching losses. Silicon carbide (SiC), a third-generation wide-bandgap semiconductor material, offers higher breakdown voltage, lower on-resistance, and lower conduction losses. However, in power device applications, it still faces challenges with excessive on-resistance and short short-circuit withstand time, resulting in increased conduction losses and reduced reliability.

[0004] Traditional MOSFET structural designs designed to reduce on-resistance result in excessively high device saturation current, shortening short-circuit time and reducing reliability. Increasing short-circuit withstand time increases device on-resistance, leading to increased cost and switching losses. Therefore, improving device reliability while reducing on-resistance is a pressing challenge in SiC MOSFET design. This requires researchers to explore device designs that combine low on-resistance with high short-circuit withstand to optimize SiC MOSFET performance. Summary of the Invention

[0005] In response to the above-mentioned problems, the purpose of the present invention is to provide a silicon carbide power MOSFET and a method for manufacturing the same. The silicon carbide power MOSFET manufactured by the present invention has a two-layer cellular structure manufactured by a regrowth technique, and silicon carbide is etched to form a trench structure, and p-type ion implantation is performed at the bottom and sidewalls of the trench to achieve ohmic contact. The double-layer cellular structure provides a double JFET region length, which limits the saturation current of the MOSFET device while reducing the on-resistance. In the short-circuit state, the current flowing through the device is greatly reduced, and the short-circuit tolerance of the device is greatly improved, thereby resolving the contradiction between reducing the on-resistance and improving the short-circuit tolerance.

[0006] Specifically, the present invention provides the following technical solutions: A first aspect of the present invention provides a silicon carbide power MOSFET, comprising, from bottom to top: substrate; A first epitaxial layer, a first CSL layer, a first P body region implanted on the first epitaxial layer, a second epitaxial layer, a second CSL layer, and a second P body region implanted on the second epitaxial layer are sequentially stacked on the substrate; A trench region is provided between the first P body region and the second P body region, wherein the lower half of the trench region is surrounded by a P+ region and the upper half of the trench region is surrounded by N+ regions on both sides; a gate oxide layer and gate polysilicon covering both sides of the second epitaxial layer, wherein the gate oxide layer and gate polysilicon partially cover the second CSL layer, a portion of the second P body region, and a portion of the N+ region; a dielectric layer disposed above and on the sides of the gate polysilicon, and a source metal layer covering the N+ region, the dielectric layer region, and the entire trench region; and a top metal layer disposed above the dielectric layer and the source metal layer.

[0007] Preferably, the thickness of the first CSL layer is 1.2-1.5 μm, the thickness of the second epitaxial layer is 1.5-2.5 μm, and the thickness of the second CSL layer is 1.2-1.5 μm; the thickness of the first P body region is 0.7-1.0 μm, and the thickness of the second P body region is 0.7-1.0 μm.

[0008] Preferably, the etching depth of the trench region is 1.5-3.5 μm, the thickness of the N+ region is 0.1-0.5 μm, and the thickness of the P+ region is 0.1-0.5 μm.

[0009] Preferably, the thickness of the gate oxide layer is 20-80 nm; the thickness of the dielectric layer is 0.3-0.8 μm; and the thickness of the top metal layer is 1-10 μm.

[0010] In the present invention, the thickness and doping concentration of the epitaxial layer are generally determined according to the withstand voltage level of the device being manufactured. For example, when manufacturing a device with a withstand voltage level of 1200 V, the thickness of the first epitaxial layer is 8-15 μm.

[0011] In the present invention, the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thicknesses of the second epitaxial layer and the first P body region.

[0012] A second aspect of the present invention provides a method for manufacturing the above-mentioned silicon carbide power MOSFET, comprising the following steps: S1. growing a first epitaxial layer on a heavily n-type doped substrate and performing blanket ion implantation to form a first CSL layer; S2. Form a first hard mask layer on the surface of the first epitaxial layer, expose an ion implantation window in the first P body region through mask etching, and implant aluminum ions to form the first P body region; S3, growing a second epitaxial layer on the first P body region, and performing blanket ion implantation to form a second CSL layer; S4, forming a second hard mask layer on the surface of the second epitaxial layer, exposing an ion implantation window in the second P body region through mask etching, and implanting aluminum ions to form the second P body region; S5, forming a sidewall region on the sidewall of the second hard mask layer, and implanting nitrogen ions to form an N+ region; S6. Remove the second hard mask layer and etch the third hard mask layer using a mask to expose a window for etching silicon carbide; etch the first epitaxial layer and the second epitaxial layer to form a trench region, where the N+ region is divided into two by the trench region; after etching, implant aluminum ions into the bottom and sidewalls of the trench to form a P+ region; S7, removing the third hard mask layer, depositing a cap layer and performing high-temperature thermal annealing to activate the implanted ions, and then removing the cap layer; S8. Form a gate oxide layer by thermally oxidizing silicon carbide and annealing, deposit and etch n-type doped polysilicon to form a gate region, deposit a dielectric layer and etch the source window, sputter the source metal layer to form an ohmic contact between it and the N+ and P+ regions, evaporate the top metal layer and use a mask to etch out the source region, then perform back-side scribing, cleaning and substrate thinning processes, and form ohmic contacts and electrodes on the back side to complete the device preparation.

[0013] Preferably, in step S1, the substrate is a 4H-SiC n-type heavily doped low-resistivity substrate with a resistivity of 0.015-0.025 Ω·cm.

[0014] Preferably, in step S1 and step S3, the doping concentration of the first epitaxial layer and the second epitaxial layer is 1×10 15 ~1×10 16 cm -3 The doping concentration of the first CSL layer and the second CSL layer is 2×10 16 ~1×10 17 cm -3 .

[0015] Preferably, in step S2 and step S4, the composition of the first hard mask layer and the second hard mask layer is selected from any one of the following: a. Ion implantation barrier layer and oxide layer; b. Ion implantation barrier layer and polysilicon layer; c. Ion implantation barrier layer, polysilicon layer, and metal layer; d. ion implantation barrier layer, polysilicon layer, oxide layer; e. ion implantation barrier layer, polysilicon layer, oxide layer, and metal layer; The ion implantation blocking layer includes a silicon dioxide layer, the oxide layer includes a silicon dioxide layer, and the material of the metal layer includes nickel, titanium, gold, copper, chromium, and aluminum.

[0016] Preferably, in step S2 and step S4, the peak value of the aluminum ion implantation concentration in the first P body region and the second P body region is 1×10 18 ~3×10 18 cm -3 , and adopts reverse doping distribution, the surface doping concentration is lower than the deep doping concentration.

[0017] Preferably, in step S5, the nitrogen ion peak concentration in the N+ region is ≥1×10 20 cm -3 The material of the sidewall region is polysilicon, silicon dioxide or silicon nitride, and the thickness does not exceed 0.5 μm to form a short channel structure with a channel length of ≤0.5 μm.

[0018] Preferably, in step S6, the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thicknesses of the second epitaxial layer and the first P body region, and the surface doping concentration of the P+ region is 1×10 18 ~1×10 19 cm -3 .

[0019] Preferably, in step S6, the composition of the third hard mask layer is selected from any one of the following: a. Oxide layer; b. Metal layer; The oxide layer includes a silicon dioxide layer, and the material of the metal layer includes nickel, titanium, gold, copper, chromium, and aluminum.

[0020] Preferably, in step S7, the component of the cap layer is carbon; the temperature of the high-temperature thermal annealing is 1500-1900° C., the time is 8-15 minutes, and the annealing atmosphere is nitrogen or argon.

[0021] Preferably, in step S8, the material of the source metal layer is nickel, titanium, tungsten, tantalum, molybdenum, aluminum or an alloy thereof, and the material of the top metal layer is aluminum.

[0022] Preferably, in step S8, the source metal layer forms an ohmic contact with the P+ region in step S6, ensuring that the potential of the first P body region is the same as that of the source.

[0023] A third aspect of the present invention provides an application of the silicon carbide power MOSFET described in the first aspect in a semiconductor device.

[0024] One or more embodiments of the present invention have at least the following beneficial effects: (1) The present invention provides a MOSFET structure with low on-resistance and high short-circuit withstand capability. The double CSL layer reduces the on-resistance of the device, and the double P body layer extends the length of the JFET region, making the MOSFET have a smaller current under short-circuit operating conditions, thereby being able to withstand a longer short-circuit time.

[0025] (2) The structure produced by the present invention has an on-resistance of 78.5 mohm when Ids=20 A, which is lower than that of the conventional structure (89.6 mohm). In addition, the structure produced by the present invention is normally closed at a short-circuit time of 3.8 μs and fails just at a short-circuit time of 31 μs (at a bus voltage of 800 V), which is longer than that of the conventional structure (short-circuit withstand time of 3.8 μs).

[0026] (3) In the structure produced by the present invention, a groove is etched to the first P body region and a P+ region is implanted to connect to the ground, so that the potential of the first P body region is the same as that of the source, thereby ensuring the breakdown voltage of the MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0028] Figure 1 This is a schematic cross-sectional view of the structure of a silicon carbide power MOSFET manufactured in Example 1 of the present invention; Figure 2 Schematic diagram of the cross-section of the structure of the device formed after step S2 of the manufacturing method of Example 1 of the present invention; Figure 3 Schematic diagram of the cross-section of the structure of the device formed after step S4 of the manufacturing method of Example 1 of the present invention; Figure 4 Schematic diagram of the cross-section of the structure of the device formed after step S5 of the manufacturing method of Example 1 of the present invention; Figure 5 Schematic diagram of the cross-section of the structure of the device formed after step S6 of the manufacturing method of Example 1 of the present invention; Figure 6 A schematic cross-sectional view of a conventional structure produced in Comparative Example 1 of the present invention; Figure 71 is a comparison diagram of the structure output curves obtained in Example 1 of the present invention and Comparative Example 1; Figure 8 1 is a comparison diagram of the short-circuit withstand time curves of the structures obtained in Example 1 of the present invention and Comparative Example 1; Among them: 1. Substrate; 2. First epitaxial layer; 3. First CSL layer; 4. First hard mask layer; 5. First P body region injection window; 6. First P body region; 7. Second epitaxial layer; 8. Second CSL layer; 9. Second hard mask layer; 10. Second P body region injection window; 11. Second P body region; 12. Sidewall region; 13. N+ region; 14. Third hard mask layer; 15. Trench region; 16. P+ region; 17. Gate oxide layer; 18. Gate polysilicon; 19. Dielectric layer; 20. Source metal layer; 21. Top metal layer. DETAILED DESCRIPTION

[0029] It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used in the present invention have the same meaning as commonly understood by those skilled in the art to which the present invention belongs.

[0030] The present invention will be further described in detail below with reference to specific embodiments. It should be noted that the specific embodiments are intended to explain the present invention rather than to limit it.

[0031] Example 1: A silicon carbide planar gate power MOSFET, such as Figure 1 As shown, from bottom to top include: Substrate 1; a first epitaxial layer 2, a first CSL layer 3, a first P body region 6 implanted on the first epitaxial layer, a second epitaxial layer 7, a second CSL layer 8, and a second P body region 11 implanted on the second epitaxial layer, stacked sequentially thereon; a trench region 15 disposed between the first P body region 6 and the second P body region 11, wherein the lower half of the trench region 15 is surrounded by a P+ region 16, and the upper half is flanked by N+ regions 13; A gate oxide layer 17 and a gate polysilicon 18 covering both sides of the second epitaxial layer 7, the gate oxide layer 17 and the gate polysilicon 18 partially cover the second CSL layer 8, part of the second P body region 11 and part of the N+ region 13; a dielectric layer 19 provided above and on the side of the gate polysilicon 18, and a source metal layer 20 covering the N+ region 13, the dielectric layer 19 region and the entire trench region 15, and a top metal layer 21 provided above the dielectric layer 19 and the source metal layer 20.

[0032] In this embodiment, the substrate is a 4H-SiC n-type heavily doped low-resistivity substrate with a resistivity of 0.020 Ω·cm.

[0033] In this embodiment, the thickness of the first epitaxial layer 2 is 8 μm, and the doping concentration is 1×10 16 cm -3 The thickness of the first CSL layer 3 is 1.2 μm, and the doping concentration is 1×10 16 cm -3 ~2×10 17 cm -3 .

[0034] The thickness of the second epitaxial layer 7 is 2 μm, and the doping concentration is 1×10 16 cm -3 The thickness of the second CSL layer 8 is 1.2 μm, and the doping concentration is 1×10 16 cm -3 ~2×10 17 cm -3 .

[0035] In this embodiment, in order to achieve a sufficient breakdown voltage, the thickness of the first P body region 6 is 1 μm, and the aluminum ion implantation concentration is 1×10 17 cm -3 ~3×10 18 cm -3 The thickness of the second P body region 11 is 1 μm, and the aluminum ion implantation concentration is 1×10 17 cm -3 ~3×10 18 cm -3 ; The doping concentration at this order of magnitude is high enough so that the potential barrier at the source end of the channel will not be lowered by the voltage applied to the drain.

[0036] In this embodiment, the etching depth of the trench region 15 is 2.2 μm; the peak concentration of nitrogen ions in the N+ region 13 is 1×10 20 cm -3 , with a thickness of 0.3 μm; the surface doping concentration of the P+ region 16 is 3×10 18 cm -3 , with a thickness of 0.3 μm to ensure good ohmic contact.

[0037] In this embodiment, the thickness of the gate oxide layer 17 is 50 nm; the thickness of the dielectric layer 19 is 0.5 μm; and the thickness of the top metal layer 21 is 2 μm.

[0038] In this embodiment, according to the above-mentioned silicon carbide planar gate power MOSFET structure, the manufacturing method involved includes the following steps: like Figure 2 As shown in the figure: (1) a first n-type epitaxial layer 2 is grown on the substrate and a blanket implant is performed to form a first CSL layer 3; (2) a first hard mask layer 4 of sufficient thickness is formed on the surface of the wafer, and the first hard mask layer 4 is etched using a mask to expose a window for ion implantation in the first P body region (first P body region implantation window 5); and p-type (e.g., aluminum ion) implantation is performed to form a first P body region 6; In this embodiment, in step (2), the composition of the first hard mask layer 4 from bottom to top includes the following options: a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide); b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer; c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum); d. ion implantation barrier layer (e.g., silicon dioxide layer), polysilicon layer, oxide layer (e.g., silicon dioxide layer); e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

[0039] For example, if the first hard mask layer is selected as a, the first hard mask layer is composed of an ion implantation barrier layer and an oxide layer from bottom to top.

[0040] like Figure 3 As shown in the figure: (3) After the first P body region 6 is implanted, a second epitaxial layer 7 is grown on the wafer surface and a second CSL layer 8 is formed by blanket implantation; (4) a second hard mask layer 9 of sufficient thickness is formed on the wafer surface, and the second hard mask layer is etched using a mask to expose a window for ion implantation in the second P body region (second P body region implantation window 10); and a p-type implantation is performed to form a second P body region 11; In this embodiment, in step (4), the composition of the second hard mask layer 9 from bottom to top includes the following options: a. Ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide); b. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer; c. Ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum); d. ion implantation barrier layer (e.g., silicon dioxide layer), polysilicon layer, oxide layer (e.g., silicon dioxide layer); e. Ion implantation barrier layer (such as silicon dioxide layer), polysilicon layer, oxide layer (such as silicon dioxide layer), metal layer (such as nickel, titanium, gold, copper, chromium, aluminum).

[0041] In this embodiment, to avoid excessively high threshold voltage, the second P body region 11 adopts a reverse doping distribution, with low surface doping concentration and high doping concentration deep below. Since silicon carbide is a wide bandgap semiconductor material, it has a larger PN junction built-in electric field. Silicon carbide can be used to make normally-off accumulation-channel MOSFETs. Therefore, the doping concentration of the channel region is 2×10 16 cm -3 to p-type doping 5×10 16 cm -3 between.

[0042] like Figure 4 As shown: (5) Next, a uniform thin layer is deposited and carpet-etched to the same thickness to form a sidewall region on the sidewall of the second hard mask layer 9 of the second P body region 11 in this step; the sidewall region is used to realize the self-aligned channel of the MOSFET; and n-type implantation is performed to form an N+ region; In this embodiment, the thickness of the uniform thin layer (spacer region) should not exceed 0.5 μm to form a shorter channel not exceeding 0.5 μm, thereby reducing the resistance of the channel region and further reducing the on-resistance of the device.

[0043] In this embodiment, the material of the sidewall region may be polysilicon, silicon dioxide, or silicon nitride.

[0044] like Figure 5 As shown: (6) the dielectric layer 19 and the hard mask layer in step (5) on the wafer surface are removed, and a third hard mask layer 14 of sufficient thickness is formed, and the third hard mask layer 14 is etched using a mask to expose a window for etching silicon carbide; the first epitaxial layer 2 and the second epitaxial layer 7 are etched to form a groove area 15, and the N+ area 13 is now divided into two by the groove area; after the etching is completed, p-type implantation is performed at the bottom and sidewalls of the groove to form a P+ area; after the implantation is completed, the third hard mask layer 14 is removed.

[0045] In this embodiment, the composition of the third hard mask layer 14 is selected from any one of the following: a. Oxide layer; b. Metal layer; The oxide layer includes a silicon dioxide layer, and the material of the metal layer includes nickel, titanium, gold, copper, chromium, and aluminum.

[0046] (7) Next, a cap layer is deposited and thermally annealed at high temperature in an inert gas atmosphere to activate the implanted ions; after the annealing is completed, the cap layer is removed; In this embodiment, the cap layer is composed of carbon; the inert gas is nitrogen or argon; the thermal annealing temperature is between 1500° C. and 1900° C., and the annealing time is between 8 and 15 minutes.

[0047] (8) If Figure 1 As shown, the subsequent production is carried out through the standard MOSFET production process; first, the wafer surface after the above steps is cleaned; a gate oxide layer 17 is formed by thermally oxidizing silicon carbide and annealing; a layer of n-type doped polysilicon gate electrode is deposited, and the gate area (gate polysilicon 18) is etched out using a mask; a layer of dielectric layer 19 is deposited, and a window in the source area is etched out using a mask; a layer of source metal is sputtered and rapidly thermally annealed to form an ohmic contact between the source metal layer 20 and the N+ and P+ areas; the top metal layer 21 is evaporated and the source area is etched out using a mask; back side scribing, cleaning and substrate thinning processes are performed, and ohmic contacts and electrodes are formed on the back side.

[0048] In this embodiment, the source metal may be nickel, titanium, tungsten, tantalum, molybdenum, aluminum or alloys thereof; and the top metal layer may be aluminum.

[0049] Comparative Example 1: like Figure 6 The figure shows the existing traditional structure, which includes from bottom to top: Substrate 1; a first epitaxial layer 2, a second CSL layer 8, a second P body region 11 implanted on the first epitaxial layer, and a P+ region 16 stacked sequentially on the substrate; N+ regions 13 are provided on both sides of the P+ region; A gate oxide layer 17 and a gate polysilicon 18 covering both sides of the first epitaxial layer 2, the gate oxide layer 17 and the gate polysilicon 18 partially covering the second CSL layer, part of the second P body region and part of the N+ region; a dielectric layer 19 arranged above and on the side of the gate polysilicon 18, and a source metal layer 20 covering the N+ region, the dielectric layer region and the entire trench region, and a top metal layer 21 arranged above the dielectric layer and the source metal.

[0050] In this comparative example, the thickness of the first epitaxial layer is 10 μm and the doping concentration is 1×10 16 cm -3 The thickness of the second CSL layer is 1.2 μm, and the doping concentration is 1×10 16 cm -3 ~2×10 17 cm -3 ; In this comparative example, the thickness of the second P body region is 1 μm, and the aluminum ion implantation concentration is 1×10 17 cm -3 ~3×10 18.

[0051] In this comparative example, the peak concentration of nitrogen ions in the N+ region is 1×10 20 cm -3 , with a thickness of 0.3 μm; the surface doping concentration of the P+ region is 3×10 18 cm -3 , with a thickness of 1.0 μm to ensure good ohmic contact; In this comparative example, the thickness of the gate oxide layer is 50 nm; the thickness of the dielectric layer is 0.5 μm; and the thickness of the top metal layer is 2 μm.

[0052] Test Example 1: This test example investigates the performance of the devices prepared in Example 1 and Comparative Example 1. (1) If Figure 7 As shown, under the same device area, the result obtained in Example 1 of the present invention is that the on-resistance of the device is extracted to be 78.5 mohm when Ids=20 A, which is lower than the traditional structure (89.6 mohm) obtained in Comparative Example 1. At the same time, the saturation current of the device is greatly reduced compared with the traditional structure.

[0053] (2) If Figure 8 As shown in Figure 1, short-circuit curves are compared under a bus voltage of 800 V for the same device area. The conventional structure obtained in Comparative Example 1 has a failure time of 3.8 μs, while the structure obtained in the embodiment of the present invention has a failure time of up to 31 μs. Therefore, compared with the comparative example, the short-circuit withstand time of the device structure obtained in the embodiment of the present invention is greatly increased.

[0054] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A silicon carbide power MOSFET, characterized in that: From bottom to top, it includes: substrate; A first epitaxial layer, a first CSL layer, a first Pbody region implanted on the first epitaxial layer, a second epitaxial layer, a second CSL layer, and a second Pbody region implanted on the second epitaxial layer are sequentially stacked on the substrate; A trench region is provided between the first P body region and the second P body region, wherein the lower half of the trench region is surrounded by a P+ region and the upper half of the trench region is surrounded by N+ regions on both sides; a gate oxide layer and gate polysilicon covering both sides of the second epitaxial layer, wherein the gate oxide layer and gate polysilicon partially cover the second CSL layer, a portion of the second P body region, and a portion of the N+ region; a dielectric layer disposed above and on the sides of the gate polysilicon, and a source metal layer covering the N+ region, the dielectric layer region, and the entire trench region; and a top metal layer disposed above the dielectric layer and the source metal layer.

2. The silicon carbide power MOSFET according to claim 1, wherein The thickness of the first CSL layer is 1.2-1.5 μm, the thickness of the second epitaxial layer is 1.5-2.5 μm, the thickness of the second CSL layer is 1.2-1.5 μm, the thickness of the first P body region is 0.7-1.0 μm, and the thickness of the second P body region is 0.7-1.0 μm; The etching depth of the trench region is 1.5-3.5 μm, the thickness of the N+ region is 0.1-0.5 μm, and the thickness of the P+ region is 0.1-0.5 μm; wherein the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thicknesses of the second epitaxial layer and the first P body region; The thickness of the gate oxide layer is 20-80 nm, the thickness of the dielectric layer is 0.3-0.8 μm, and the thickness of the top metal layer is 1-10 μm.

3. A method for manufacturing a silicon carbide power MOSFET according to any one of claims 1 to 2, characterized in that: The following steps are involved: S1. growing a first epitaxial layer on a heavily n-type doped substrate and performing blanket ion implantation to form a first CSL layer; S2. Form a first hard mask layer on the surface of the first epitaxial layer, expose an ion implantation window in the first P body region through mask etching, and implant aluminum ions to form the first P body region; S3, growing a second epitaxial layer on the first P body region, and performing blanket ion implantation to form a second CSL layer; S4, forming a second hard mask layer on the surface of the second epitaxial layer, exposing an ion implantation window in the second P body region through mask etching, and implanting aluminum ions to form the second P body region; S5, forming a sidewall region on the sidewall of the second hard mask layer, and implanting nitrogen ions to form an N+ region; S6, removing the second hard mask layer, and etching the third hard mask layer using a mask to expose a window for etching silicon carbide; etching the first epitaxial layer and the second epitaxial layer to form a trench region, where the N+ region is divided into two by the trench region; After etching, aluminum ions are implanted at the bottom and sidewalls of the trench to form a P+ region; S7, removing the third hard mask layer, depositing a cap layer and performing high-temperature thermal annealing to activate the implanted ions, and then removing the cap layer; S8. Form a gate oxide layer by thermally oxidizing silicon carbide and annealing, deposit and etch n-type doped polysilicon to form a gate region, deposit a dielectric layer and etch the source window, sputter the source metal layer to form an ohmic contact between it and the N+ and P+ regions, evaporate the top metal layer and use a mask to etch out the source region, then perform back side scribing, cleaning and substrate thinning processes, and form ohmic contacts and electrodes on the back side to complete the device preparation.

4. The production method according to claim 3, wherein: In step S1, the substrate is a 4H-SiC n-type heavily doped low-resistivity substrate with a resistivity of 0.015-0.025 Ω·cm; In step S1 and step S3, the doping concentration of the first epitaxial layer and the second epitaxial layer is 1×10 15 ~1×10 16 cm -3 The doping concentration of the first CSL layer and the second CSL layer is 2×10 16 ~1×10 17 cm -3 .

5. The production method according to claim 3, wherein: In step S2 and step S4, the composition of the first hard mask layer and the second hard mask layer is selected from any one of the following: a. Ion implantation barrier layer and oxide layer; b. Ion implantation barrier layer and polysilicon layer; c. Ion implantation barrier layer, polysilicon layer, and metal layer; d. ion implantation barrier layer, polysilicon layer, oxide layer; e. ion implantation barrier layer, polysilicon layer, oxide layer, and metal layer; The ion implantation blocking layer includes a silicon dioxide layer, the oxide layer includes a silicon dioxide layer, and the material of the metal layer includes nickel, titanium, gold, copper, chromium, and aluminum.

6. The production method according to claim 3, wherein: In step S2 and step S4, the peak value of the aluminum ion implantation concentration in the first P body region and the second P body region is 1×10 18 ~3×10 18 cm -3 , and adopts reverse doping distribution, the surface doping concentration is lower than the deep doping concentration; In step S5, the nitrogen ion peak concentration in the N+ region is ≥1×10 20 cm -3 The material of the sidewall region is polysilicon, silicon dioxide or silicon nitride, and the thickness does not exceed 0.5 μm to form a short channel structure with a channel length of ≤0.5 μm.

7. The production method according to claim 3, wherein: In step S6, the etching depth of the trench region is greater than the thickness of the second epitaxial layer and less than the sum of the thickness of the second epitaxial layer and the first P body region, and the surface doping concentration of the P+ region is 1×10 18 ~1×10 19 cm -3 ; In step S6, the composition of the third hard mask layer is selected from any one of the following: a. Oxide layer; b. Metal layer; The oxide layer includes a silicon dioxide layer, and the material of the metal layer includes nickel, titanium, gold, copper, chromium, and aluminum.

8. The production method according to claim 3, wherein: In step S7, the cap layer is composed of carbon; the high-temperature thermal annealing is performed at a temperature of 1500-1900° C. for 8-15 minutes, and the annealing atmosphere is nitrogen or argon.

9. The production method according to claim 3, wherein: In step S8, the material of the source metal layer is nickel, titanium, tungsten, tantalum, molybdenum, aluminum or an alloy thereof, and the material of the top metal layer is aluminum; The source metal layer forms an ohmic contact with the P+ region in step S6, ensuring that the potential of the first P body region is the same as that of the source.

10. Use of the silicon carbide power MOSFET according to any one of claims 1 to 2 in a semiconductor device.

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