Back contact cells and methods of making the same

Abstract

The application provides a back contact cell and a preparation method thereof, and relates to the technical field of solar cells. The preparation method of the back contact cell comprises the following steps: providing a semiconductor substrate; sequentially preparing a tunneling oxide layer and an intrinsic silicon base layer arranged in a stack on the back light surface of the semiconductor substrate; preparing a first doped silicon base layer on the intrinsic silicon base layer; removing the first doped silicon base layer in a first region, so that the intrinsic silicon base layer in the first region is exposed; preparing a second doped silicon base layer on the back light surface; and annealing the intermediate body of the back contact cell to form an electron-doped layer, a hole-doped layer, a tunneling junction and a neutral-doped compensation region. According to the application, the intrinsic silicon base layer in the first region is first exposed, and then the second doped silicon base layer is prepared on the back light surface, and then annealing is performed, so that the electron-doped layer and the hole-doped layer can be formed synchronously, the tunneling junction and the neutral-doped compensation region can be formed, the process flow steps can be reduced, and the risk of conduction of the electron-doped layer and the hole-doped layer can be reduced.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a back contact cell and its preparation method. Background Technology

[0002] Back-contact batteries are a type of battery with high conversion efficiency and promising application prospects. However, the fabrication process of back-contact batteries is usually quite complex and involves many steps, resulting in high manufacturing costs. Summary of the Invention

[0003] This application provides a method for preparing a back contact battery, the method comprising:

[0004] A semiconductor substrate is provided, which has a light-receiving surface and a back-lighting surface after chemical polishing. A tunneling oxide layer and an intrinsic silicon base layer are sequentially stacked on the back-lighting surface.

[0005] A first doped silicon substrate is prepared on an intrinsic silicon substrate;

[0006] Holes are alternately opened in certain areas of the backlight surface. The area with holes in the backlight surface is the first area, and the area without holes is the second area. The first doped silicon substrate in the first area is removed, so that the intrinsic silicon substrate in the first area is exposed.

[0007] A second doped silicon substrate is fabricated on the backlight surface;

[0008] The intermediate of the back contact battery is annealed to form an electron-doped layer, a hole-doped layer, a tunnel junction, and a neutral doping compensation region. The electron-doped layer is formed by driving a doping source from the second doped silicon substrate in the first region into the intrinsic silicon substrate, and the hole-doped layer is formed by driving a doping source from the first doped silicon substrate in the second region into the intrinsic silicon substrate. The tunnel junction is formed by the self-assembly of the first and second doped silicon substrates stacked in the second region. The neutral doping compensation region is located in a third region at the junction of the first and second regions.

[0009] In some embodiments, the intrinsic silicon substrate and the first doped silicon substrate are prepared by different deposition methods, including low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition; based on the film layer differences between the intrinsic silicon substrate and the first doped silicon substrate achieved by different deposition methods, the first doped silicon substrate in the first region is removed, thereby exposing the intrinsic silicon substrate in the first region.

[0010] In some embodiments, the intrinsic silicon substrate is prepared by low-pressure chemical vapor deposition at a deposition temperature of 500-650 degrees Celsius; the first doped silicon substrate is prepared by plasma-enhanced chemical vapor deposition at a deposition temperature of 200-450 degrees Celsius.

[0011] In some embodiments, the step of removing the first doped silicon substrate of the first region to expose the intrinsic silicon substrate of the first region includes: removing the first doped silicon substrate of the first region by laser etching; and performing selective chemical etching by wet cleaning to etch the remaining first doped silicon substrate of the first region while retaining the intrinsic silicon substrate of the first region.

[0012] In some embodiments, the laser power is 60-80W and the laser energy density is 0.25J / cm². 2 -0.35J / cm 2 In the step of selective chemical etching using wet cleaning, the cleaning temperature is 65-75 degrees Celsius.

[0013] In some embodiments, the deposition thickness of the intrinsic silicon substrate is 50-200 nm.

[0014] In some embodiments, the tunneling oxide layer is prepared by low-pressure chemical vapor deposition at a deposition temperature of 400-700 degrees Celsius; the second doped silicon substrate is prepared by plasma-enhanced chemical vapor deposition at a deposition temperature of 350-500 degrees Celsius.

[0015] In some embodiments, the annealing temperature is 880-980 degrees Celsius during the annealing process.

[0016] In some embodiments, after annealing the intermediate of the back contact battery, the method for preparing the back contact battery further includes: removing the neutral doping compensation region of the third region to expose the semiconductor substrate of the third region, specifically including: removing the neutral doping compensation region of the third region by laser etching; performing selective chemical etching by wet cleaning to etch the remaining neutral doping compensation region of the third region while retaining the semiconductor substrate of the third region.

[0017] In some embodiments, the laser power is 60-80W and the laser energy density is 0.25J / cm². 2 -0.35J / cm 2 In the step of selective chemical etching using wet cleaning, the cleaning temperature is 70-80 degrees Celsius.

[0018] In some embodiments, after the step of removing the neutral doped compensation region of the third region, the method for preparing the back contact cell further includes: sequentially preparing a passivation film and an antireflection film on the surface of an intermediate body of the back contact cell; wherein the passivation film covers the light-receiving surface and the back-light-receiving surface of the intermediate body, or the passivation film covers the light-receiving surface, the back-light-receiving surface and the side surface of the intermediate body; and the antireflection film covers the light-receiving surface and the back-light-receiving surface of the intermediate body.

[0019] In some embodiments, the first doped silicon substrate includes a boron doping source and the second doped silicon substrate includes a phosphorus doping source; or, the first doped silicon substrate includes a phosphorus doping source and the second doped silicon substrate includes a boron doping source.

[0020] This application also provides a back contact battery, which is prepared by the back contact battery preparation method described above.

[0021] The beneficial effects of the method for preparing the back contact battery provided in this application are:

[0022] This application removes the first doped silicon substrate from the first region of the backlight surface of a semiconductor substrate, exposing the intrinsic silicon substrate of the first region. Then, a second doped silicon substrate is fabricated on the backlight surface. The intermediate body of the back contact battery is then annealed, allowing the dopant sources of both the first and second doped silicon substrates in the second region to be simultaneously driven into the intrinsic silicon substrate. This forms an electron doped layer in the first region and a hole doped layer in the second region, reducing process steps and fabrication complexity. Furthermore, based on the doping compensation and neutralization effect of the dopant sources in the first and second doped silicon substrates, a neutral doped compensation region is formed in the third region at the boundary between the first and second regions. This neutral doped compensation region has an insulating effect, reducing the risk of conduction between the electron and hole doped layers. After annealing, the stacked first and second doped silicon substrates self-assemble to form a tunnel junction, eliminating the need to remove excess second doped silicon substrate in subsequent processes. This further reduces process steps, lowers fabrication costs, and improves fabrication efficiency. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0024] Figure 1 This is a schematic flowchart of a partial preparation method of a back contact battery provided in some embodiments of this application;

[0025] Figure 2 This is a schematic diagram of a portion of the manufacturing process of a back contact battery provided in some embodiments of this application;

[0026] Figure 3 This is a schematic diagram of the fabrication process of a back contact battery provided in some embodiments of this application;

[0027] Figure 4This is a schematic diagram of the structure of an intermediate body for a back contact battery provided in some embodiments of this application;

[0028] Figure 5 yes Figure 4 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0029] Figure 6 yes Figure 5 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0030] Figure 7 yes Figure 6 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0031] Figure 8 yes Figure 7 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0032] Figure 9 yes Figure 8 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0033] Figure 10 yes Figure 9 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0034] Figure 11 yes Figure 10 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0035] Figure 12 yes Figure 11 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0036] Figure 13 yes Figure 12 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0037] Figure 14 yes Figure 13 A schematic diagram of the structure of the next intermediate of the back contact battery in the embodiment;

[0038] Figure 15 yes Figure 14 A schematic diagram of the back contact battery after it has been manufactured, as shown in the embodiment. Detailed Implementation

[0039] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0040] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0041] It should be understood that the terms "comprising" and "having," and any variations thereof, used in this application and the appended claims, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0042] This application provides a back-contact battery and its fabrication method. A back-contact battery, also known as a BC-type battery, is a solar cell that integrates both positive and negative electrodes on the back surface, allowing the light-receiving surface to absorb more sunlight. The back-contact battery provided in this application is fabricated using the back-contact battery fabrication method described below.

[0043] Please see Figure 1 , Figure 1 This is a schematic flowchart of a partial preparation method of a back contact battery provided in some embodiments of this application.

[0044] In some embodiments, the method for preparing a back contact battery includes the following steps:

[0045] S11: Provides a semiconductor substrate.

[0046] The semiconductor substrate, after chemical polishing, has a light-receiving surface and a backlighting surface. The semiconductor substrate can be a silicon wafer. Examples of semiconductor substrates, but not limited to, are... Figure 4 The structure shown.

[0047] S12: A tunneling oxide layer and an intrinsic silicon base layer are sequentially stacked on the back surface of a semiconductor substrate.

[0048] The tunneling oxide layer is fabricated on the backlight surface of the semiconductor substrate, and the intrinsic silicon substrate is fabricated on the tunneling oxide layer, thereby obtaining a stacked tunneling oxide layer and an intrinsic silicon substrate.

[0049] The intermediate body for the back contact battery obtained through step S12, for example, but not limited to, is as follows: Figure 5 The structure shown.

[0050] S13: Prepare the first doped silicon substrate on the intrinsic silicon substrate.

[0051] The first doped silicon substrate is a silicon-based film layer including a dopant source, and its doping concentration can be set as needed. The specific type of dopant source in the first doped silicon substrate can be set as needed. In some embodiments, the first doped silicon substrate includes a boron dopant source. In other embodiments, the first doped silicon substrate includes a phosphorus dopant source.

[0052] After the first doped silicon substrate is fabricated on the intrinsic silicon substrate, the resulting intermediate of the back contact cell comprises a tunneling oxide layer, an intrinsic silicon substrate, and the first doped silicon substrate stacked together. It is understood that the intermediate of the back contact cell, i.e., the intermediate product in the fabrication process, may differ depending on the steps taken. Therefore, when this document refers to intermediates, it should be understood in conjunction with the corresponding steps.

[0053] The intermediate body for the back contact battery obtained through step S13 is, for example, but not limited to, such as... Figure 6 The structure shown.

[0054] S14: Remove the first doped silicon substrate in the first region, thereby exposing the intrinsic silicon substrate in the first region.

[0055] For ease of explanation, the back contact battery and its intermediates can be defined as having a first region and a second region. The first region and the second region are two different regions on the backlight surface, arranged alternately on the backlight surface. In this application, by removing the first doped silicon substrate, the intrinsic silicon substrate of the first region is exposed, while the intrinsic silicon substrate of the second region is covered by the first doped silicon substrate.

[0056] Optionally, before removing the first doped silicon substrate in the first region, the method further includes: alternately creating holes in a portion of the backlight surface, where the area with holes is the first region and the area without holes is the second region. By alternately creating holes in a portion of the backlight surface, the difficulty of removing the first doped silicon substrate in that region can be reduced, while simultaneously defining the first and second regions. It is understood that in other embodiments, the method may employ, but is not limited to, this step, and the definition of the first and second regions is not limited to this.

[0057] In some embodiments, the area on the backlight surface of the back contact battery and its intermediate can be divided into a first area and a second area. In other embodiments, the area on the backlight surface of the intermediate of the back contact battery may include a first area, a second area, and other areas. The former will be used as an example in the following description.

[0058] The intermediate body for the back contact battery obtained through step S14, for example, but not limited to, is as follows: Figure 8 The structure shown.

[0059] S15: Prepare a second doped silicon substrate on the backlight surface.

[0060] In the first region, a second doped silicon substrate is disposed on the exposed intrinsic silicon substrate. In the second region, a second doped silicon substrate is disposed on the first doped silicon substrate. In the first region, the second doped silicon substrate, the intrinsic silicon substrate, and the tunneling oxide layer are sequentially stacked. In the second region, the second doped silicon substrate, the first doped silicon substrate, the intrinsic silicon substrate, and the tunneling oxide layer are sequentially stacked.

[0061] The second doped silicon substrate is a silicon-based film layer including a dopant source, and its doping concentration can be set as needed. In some embodiments, the first doped silicon substrate includes a boron dopant source, and the second doped silicon substrate includes a phosphorus dopant source. In other embodiments, the first doped silicon substrate includes a phosphorus dopant source, and the second doped silicon substrate includes a boron dopant source.

[0062] Understandably, boron trichloride and phosphine are two commonly used doping sources in the fabrication of back-contact batteries. In other embodiments, the doping sources for the first and second doped silicon substrates can also be other boron and phosphorus sources. The following description mainly uses the example of a P-type doped silicon substrate and an N-type doped silicon substrate.

[0063] The intermediate body of the back contact battery obtained through step S15, for example, but not limited to, is as follows: Figure 9 The structure shown.

[0064] S16: Anneal the intermediate body of the back contact battery.

[0065] Annealing is a process that involves high-temperature treatment of silicon wafers to achieve effects such as lattice repair, impurity activation, and thin film modification.

[0066] After steps S11-S15, the intermediate body of the back contact cell includes two different doping sources. Furthermore, by annealing the intermediate body of the back contact cell, the doping sources of the first doped silicon substrate in the second region and the second doped silicon substrate in the first region can be simultaneously driven into the intrinsic silicon substrate using high temperature.

[0067] Using an annealing process, the second-doped silicon substrate in the first region is driven by high temperature to introduce its phosphorus doping source into the intrinsic silicon substrate. Ultimately, the second-doped silicon substrate and the intrinsic silicon substrate in the first region achieve a stable doping curve, and the grains, after high-temperature recombination, reach an equilibrium crystallization ratio, forming the electron-doped layer (N-region) of the back-contact solar cell. Similarly, the first-doped silicon substrate in the second region is driven by high temperature to introduce its boron doping source into the intrinsic silicon substrate. Ultimately, the first-doped silicon substrate and the intrinsic silicon substrate in the second region achieve a stable doping curve, and the grains, after high-temperature recombination, reach an equilibrium crystallization ratio, forming the hole-doped layer (P-region) of the back-contact solar cell.

[0068] Furthermore, at the boundary between the first and second regions, specifically at the junction of the first and second doped silicon substrates on the intrinsic silicon substrate, a neutral doped compensation region will self-assemble after annealing due to the doping compensation and neutralization effect. For ease of understanding, the boundary between the first and second regions is named the third region, which is composed of a portion of the first region and a portion of the second region. The neutral doped compensation region formed in the third region is doped with doping sources from both the first and second doped silicon substrates at a low concentration, thus providing insulation. It can serve as an insulating region between the N-region and the P-region, which helps reduce the risk of conduction between the N-region and P-region of the back contact battery.

[0069] Furthermore, after annealing, the stacked first and second doped silicon substrates self-assemble to form a highly doped tunnel junction, exhibiting linear conductor characteristics in rectification. Understandably, the first and second doped silicon substrates in the second region are stacked, with the intrinsic silicon substrate of the second region covered by the first doped silicon substrate. After annealing, the intermediate body of the back contact cell can form a tunnel junction in the second region, eliminating the need to remove the second doped silicon substrate in subsequent processes, thus reducing process steps and fabrication complexity.

[0070] Therefore, after annealing the intermediate of the back contact battery, an electron-doped layer, a hole-doped layer, a tunnel junction, and a neutral doping compensation region can be formed. Specifically, the hole-doped layer is formed by a boron dopant source from the first doped silicon substrate in the second region being driven into the intrinsic silicon substrate, and the electron-doped layer is formed by a phosphorus dopant source from the second doped silicon substrate in the first region being driven into the intrinsic silicon substrate. The first and second doped silicon substrates stacked in the second region self-assemble to form a highly doped tunnel junction after high-temperature annealing. Based on the doping compensation and neutralization effect, the neutral doping compensation region is formed at the boundary between the electron-doped layer and the hole-doped layer.

[0071] The current fabrication process for back-contact batteries typically involves the following steps: A tunneling oxide layer, an intrinsic silicon substrate, and a first doped silicon substrate are sequentially layered on the back surface of a semiconductor substrate. The tunneling oxide layer, intrinsic silicon substrate, and first doped silicon substrate in the first region are removed using laser etching and wet cleaning. The light-receiving and back-light-receiving surfaces of the semiconductor substrate are then texturized. Next, a tunneling oxide layer, intrinsic silicon substrate, and a second doped silicon substrate are sequentially layered on the back surface. The tunneling oxide layer, intrinsic silicon substrate, and second doped silicon substrate in the second region are removed using laser etching and wet cleaning.

[0072] In contrast, this application only removes the first doped silicon substrate on the intrinsic silicon substrate in the first region, exposing the intrinsic silicon substrate, and prepares the second doped silicon substrate on the backlight side to obtain the intermediate of the back contact cell. The coating in the second region does not need to be removed, thereby reducing multiple process steps, reducing the complexity of the fabrication process, which is beneficial to reducing the fabrication cost of the back contact cell and improving the fabrication efficiency of the back contact cell.

[0073] It should be noted that annealing simultaneously drives the dopant sources of the two doped silicon substrates into the intrinsic silicon substrate. "Simultaneous driving" refers to achieving this within the same process step (e.g., step S16), rather than specifying a driving time. Simultaneous driving differs from step-by-step driving, which involves driving the dopant sources of the two doped silicon substrates into the intrinsic silicon substrate separately in different process steps.

[0074] The intermediate body of the back contact battery obtained through step S16 is, for example, but not limited to, such as... Figure 10 The structure shown.

[0075] There are various methods for preparing the films in steps S11-S15 above, such as, but not limited to, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD). The specific method can be selected according to the actual situation. Examples provided in this application are shown below. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of a portion of the fabrication process of a back contact battery provided in some embodiments of this application.

[0076] In some embodiments, steps S11-S12 above may include the following steps:

[0077] S111: Provides a semiconductor substrate.

[0078] The semiconductor substrate can be an N-type silicon wafer or a P-type silicon wafer.

[0079] S112: Pre-process the semiconductor substrate.

[0080] Pretreatment includes, but is not limited to, chemical polishing of the semiconductor substrate.

[0081] Since semiconductor substrates may have some problems, such as damaged layers or dirt on the surface, making them unsuitable for direct film preparation, this method can pre-treat the semiconductor substrate in this step to facilitate film preparation in subsequent processes.

[0082] The specific details of the pretreatment can be set according to the actual situation. In some embodiments, this method can employ a wet chemical cleaning method to polish both the light-receiving and back-light-receiving surfaces of the semiconductor substrate and remove the surface damage layer. For example, this step may include alkaline polishing, water washing, alkaline washing, acid washing, pre-dehydration, and drying, etc., to achieve cleaning, polishing, and removal of the surface damage layer of the semiconductor substrate through each step. Each cleaning step can be performed in a corresponding cleaning tank.

[0083] Alkaline polishing primarily involves polishing the surface of a semiconductor substrate using alkaline chemicals (such as KOH, NaOH, etc.) / pure water / additives at a temperature of 70-80 degrees Celsius. Alkaline washing primarily involves removing additives from the surface of the semiconductor substrate using alkaline chemicals (such as KOH, NaOH, etc.) / pure water / additives at a temperature of 55-65 degrees Celsius. The semiconductor substrate has a light-receiving surface and a back-light surface that are positioned opposite each other.

[0084] S113: Preparation of tunneling oxide layer.

[0085] This step can be performed by deposition to prepare a tunneling oxide layer on the back surface of a semiconductor substrate. Specific deposition methods include, but are not limited to, LPCVD. Optionally, this step can be performed at a temperature of 400-700 degrees Celsius using LPCVD to prepare a tunneling oxide layer with a thickness of 1-3 nm, for example, a 2 nm thick tunneling oxide layer. The tunneling oxide layer is silicon oxide.

[0086] S114: Prepare intrinsic silicon substrate.

[0087] This step can be performed by deposition to prepare an intrinsic silicon substrate on the tunneling oxide layer, thereby obtaining a stacked tunneling oxide layer and intrinsic silicon substrate. Optionally, this step uses LPCVD to prepare the intrinsic silicon substrate.

[0088] In this step, an intrinsic silicon substrate is prepared on the tunneling oxide layer at a temperature of 500-650 degrees Celsius, a pressure of 200-500 Pa, and a silane flow rate of 50-2000 sccm. The intrinsic silicon substrate is an intrinsic polycrystalline silicon thin film, and the crystallinity of the polycrystalline silicon can be 2%-20%, for example, 10%.

[0089] In this embodiment, steps S113 and S114 can employ the same film preparation method, such as LPCVD, allowing them to be performed within the same equipment to improve preparation efficiency. Alternatively, steps S113 and S114 can be performed using different equipment.

[0090] In step S13, the preparation method of the first doped silicon substrate can differ from that of the intrinsic silicon substrate. Optionally, the intrinsic silicon substrate is prepared by low-pressure chemical vapor deposition, and the first doped silicon substrate is prepared by plasma-enhanced chemical vapor deposition. The deposition temperature of the intrinsic silicon substrate can be 500-650 degrees Celsius, such as 520 degrees Celsius, 550 degrees Celsius, 600 degrees Celsius, etc.; the deposition temperature of the first doped silicon substrate can be 200-450 degrees Celsius, such as 250 degrees Celsius, 300 degrees Celsius, 350 degrees Celsius, 400 degrees Celsius, etc.

[0091] This method prepares intrinsic silicon substrate and first doped silicon substrate by using different deposition methods, which can make the intrinsic silicon substrate and the first doped silicon substrate have differences in lattice grains and compactness, so as to achieve selective removal in step S14, that is, remove the first doped silicon substrate in the first region while retaining the intrinsic silicon substrate in the first region, so that the intrinsic silicon substrate in the first region is exposed.

[0092] LPCVD is a technique for depositing thin films on a substrate surface through the thermal decomposition or chemical reaction of gaseous precursors under low pressure. The principle of LPCVD is to evacuate the reaction chamber to low pressure, reducing the frequency of gas molecule collisions and allowing the precursor to diffuse more uniformly onto the substrate surface. PECVD is a technique that utilizes plasma-enhanced chemical reactions to achieve thin film deposition at low temperatures. The principle of PECVD is to excite gas to form plasma using radio frequency, microwave, or other methods, generating highly reactive chemical groups. These reactive groups in the plasma then react on the substrate surface to form a thin film. Plasma energy can lower the reaction temperature and simultaneously increase the deposition rate.

[0093] The intrinsic silicon substrate and the first doped silicon substrate prepared by the above method exhibit differences in lattice grain size and film density. In step S14, the first doped silicon substrate in the first region can be selectively removed based on these differences, while retaining the intrinsic silicon substrate in the first region. Step S14 may include: removing a portion of the first doped silicon substrate in the first region using laser etching, followed by selective chemical etching using wet cleaning to etch the remaining first doped silicon substrate in the first region, while retaining the intrinsic silicon substrate in the first region.

[0094] Based on the difference in film layers between the first doped silicon substrate and the intrinsic silicon substrate, step S14 only requires the use of a low-power laser to remove part of the first doped silicon substrate, followed by a wet cleaning step to remove the first doped silicon substrate.

[0095] In this step, the laser power can be 60-80W, such as 65W, 70W, 75W, etc., and the laser energy density can be 0.25J / cm². 2 -0.35J / cm 2 For example, 0.30 J / cm 2 .

[0096] Based on the difference in film grain / density between the intrinsic silicon substrate and the first-doped silicon substrate, this method can achieve the effect of etching the first-doped silicon substrate without damaging the intrinsic silicon substrate by controlling parameters such as cleaning temperature and cleaning solution concentration in step S14. In the step of selective chemical etching using wet cleaning, the cleaning temperature can be 65-75 degrees Celsius, for example, 68 degrees Celsius, 70 degrees Celsius, 73 degrees Celsius, etc.

[0097] The first doped silicon substrate prepared in step S13 may include a first amorphous silicon-based doped film layer and a first silicon-based mask layer stacked together. Step S13 may include: preparing the first amorphous silicon-based doped film layer on the intrinsic silicon substrate; and preparing the first silicon-based mask layer on the first amorphous silicon-based doped film layer. The first amorphous silicon-based doped film layer may include a single amorphous silicon-based doped film, or multiple amorphous silicon-based doped films with varying doping concentrations. The material of the first silicon-based mask layer may be, for example, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, etc.

[0098] Therefore, in step S14, this method first uses a laser to remove part of the first doped silicon substrate in the first region, and then uses wet cleaning to etch away the remaining first doped silicon substrate in the first region, thereby removing the first doped silicon substrate in the first region while retaining the intrinsic silicon substrate in the first region. Specifically, the laser removes at least the first silicon-based mask layer in the first region, exposing the first amorphous silicon-based doped film layer in the first region, which will then be removed in the subsequent wet cleaning process.

[0099] During the wet cleaning process, the first silicon-based mask layer in the second region is removed, while the first amorphous silicon-based doped film layer in the second region is retained. Specifically, this method may use a solution such as, but not limited to, hydrofluoric acid in this step.

[0100] The preparation process parameters for step S13 are shown in the following example:

[0101] The deposition temperature of the first doped silicon substrate is 200-450 degrees Celsius, for example, 250 degrees Celsius, 300 degrees Celsius, 350 degrees Celsius, 400 degrees Celsius, etc.

[0102] The pressure is 200-500 Pa, for example, 300 Pa, 400 Pa, etc.;

[0103] The silane flow rate is 50-3000 sccm, for example, 500 sccm, 1000 sccm, 2000 sccm, etc.;

[0104] The boron doping source flux is 5-3000 sccm, for example, 500 sccm, 1000 sccm, 2000 sccm, etc.;

[0105] Boron doping sources include, but are not limited to, B2H6, BCl3, TMB, BF3, TEB, etc., and the concentration of boron doping sources is 2%-8%, such as 3%, 5%, 7%, etc.

[0106] The deposition thickness of the first amorphous silicon-based doped film is 100-300 nm, for example, 150 nm, 200 nm, 250 nm, etc.; the deposition thickness of the first silicon-based mask layer is 5-20 nm, for example, 10 nm, 15 nm, etc.; and the reaction gas of the first silicon-based mask layer is a mixture of SiH4 and N2O.

[0107] The crystallinity of the first doped silicon substrate film is 10%-20%, such as 12%, 15%, 18%, etc.

[0108] The laser process parameters for step S14 are shown in the following example:

[0109] The laser source is 532nm-ps, with a spot size of 150um*150um and a rectangular spot size of 150um*200um.

[0110] The laser power is 60-80W, for example, 65W, 70W, 75W, etc.;

[0111] The laser's unit energy is 0.25-0.35 J / cm². 2 For example, 0.3 J / cm 2 ;

[0112] The overlap rate is less than 5%, for example, 2%, 3%, 4%, etc.;

[0113] Linear velocity greater than 60m / s, such as 70m / s, 80m / s, 90m / s, etc.

[0114] The cleaning process flow diagram for step S14 is as follows:

[0115] The intermediate is subjected to a series of steps including alkaline polishing, water washing, alkaline washing, acid washing, pre-dehydration, and drying. Each cleaning step can be performed in a cleaning tank, such as an alkaline polishing tank or an alkaline washing tank. In the alkaline polishing step, the solution used is: alkaline chemicals (e.g., KOH, NaOH, etc.) / pure water / additives; the process temperature is 65-75 degrees Celsius, for example, 70 degrees Celsius; the process time is 200-300 seconds, for example, 230 seconds, 250 seconds, 270 seconds, etc. The alkaline polishing step is mainly used to achieve selective chemical etching. In the alkaline washing step, the solution used is: alkaline chemicals (e.g., KOH, NaOH, etc.) / pure water / additives; the process temperature is 55-65 degrees Celsius, for example, 60 degrees Celsius. The alkaline washing step is mainly used to remove additives.

[0116] Based on the above steps, this method can remove the first doped silicon substrate in the first region while retaining the intrinsic silicon substrate in the first region, thereby exposing the intrinsic silicon substrate in the first region and exposing the first doped silicon substrate in the second region, so as to facilitate step S15.

[0117] In other embodiments, steps S12-S13 can also employ the same deposition method to prepare the intrinsic silicon substrate and the first doped silicon substrate, for example, LPCVD. In comparison, the above design is beneficial for improving the film density and lattice grain difference of the intrinsic silicon substrate and the first doped silicon substrate, reducing the difficulty of film removal in step S14, and improving the film removal efficiency in step S14.

[0118] In other embodiments, step S14 may also employ other methods to remove the first doped silicon substrate in the first region while retaining the intrinsic silicon substrate in the first region. For example, the removal of the first doped silicon substrate in the first region may be achieved entirely using laser light. In comparison, the above design is advantageous in improving the removal efficiency of the first doped silicon substrate in the first region and in reducing the risk of the intrinsic silicon substrate in the first region being mistakenly removed.

[0119] In current fabrication processes, a portion of the intrinsic silicon substrate is removed, thus requiring a relatively large thickness of approximately 300 nm initially. This method, based on the aforementioned process, eliminates the need to remove the intrinsic silicon substrate, thereby reducing the thickness of the intrinsic silicon substrate required in step S12. Optionally, the deposition thickness of the intrinsic silicon substrate obtained in step S12 is 50-200 nm, for example, 70 nm, 100 nm, 120 nm, 150 nm, etc.

[0120] Optionally, in step S13, the first doped silicon substrate is prepared by plasma-enhanced chemical vapor deposition (PECVD), and in step S15, the second doped silicon substrate is prepared by PECVD. In other words, the first and second doped silicon substrates are prepared using the same method, so steps S13 and S15 can be performed in the same equipment, which helps to reduce manufacturing costs.

[0121] Similar to the first doped silicon substrate, the second doped silicon substrate prepared in step S15 may include a second amorphous silicon-based doped film layer and a second silicon-based mask layer stacked together. Step S15 may include: preparing the second amorphous silicon-based doped film layer on the backlight surface; and preparing the second silicon-based mask layer on the second amorphous silicon-based doped film layer. The second amorphous silicon-based doped film layer may include a single amorphous silicon-based doped film, or multiple amorphous silicon-based doped films with varying doping concentrations. The material of the second silicon-based mask layer may be, for example, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, etc.

[0122] It should be noted that the film layer fabricated on the backlight surface of the semiconductor substrate mentioned in this article refers to the film layer fabricated on the side facing the backlight surface. Specifically, the film layer may be fabricated on the body of the semiconductor substrate, such as a tunneling oxide layer, or it may be fabricated on other film layers on the backlight surface, such as an intrinsic silicon substrate or a first doped silicon substrate.

[0123] In this method, during the preparation of films (e.g., tunneling oxide layers, intrinsic silicon substrates) using LPCVD, the deposition temperature can be 400-700 degrees Celsius, for example, 450 degrees Celsius, 550 degrees Celsius, 600 degrees Celsius, 650 degrees Celsius, etc. In the preparation of films (e.g., first doped silicon substrates, second doped silicon substrates) using PECVD, the deposition temperature can be 200-500 degrees Celsius, for example, 300 degrees Celsius, 400 degrees Celsius, etc. Optionally, the deposition temperature of the first doped silicon substrate is 200-450 degrees Celsius, for example, 250 degrees Celsius, 300 degrees Celsius, 350 degrees Celsius, 400 degrees Celsius, etc.; and the deposition temperature of the second doped silicon substrate is 350-500 degrees Celsius, for example, 400 degrees Celsius, 450 degrees Celsius, etc.

[0124] In related fabrication processes, because the deposition temperature of phosphorus-doped silicon substrates is usually high, it is often necessary to prepare phosphorus-doped silicon substrates first, followed by boron-doped silicon substrates. This method, based on the above process, achieves similar deposition temperatures for the first and second doped silicon substrates, thus eliminating the need to restrict the preparation order of the phosphorus-doped and boron-doped silicon substrates and thus having a wider range of applications.

[0125] In the example provided in this method, the first doped silicon substrate includes a boron dopant source, and the second doped silicon substrate includes a phosphorus dopant source. An example of the fabrication process parameters for step S15 is as follows:

[0126] The deposition temperature is 350-500 degrees Celsius, for example, 400 degrees Celsius, 450 degrees Celsius, etc.;

[0127] The pressure is 200-500 Pa, for example, 300 Pa, 400 Pa, etc.;

[0128] The silane flow rate is 50-3000 sccm, for example, 1000 sccm, 2000 sccm, etc.;

[0129] The phosphorus doping source flux is 100-3000 sccm, for example, 500 sccm, 1000 sccm, 2000 sccm, etc.;

[0130] The phosphorus doping source is, for example but not limited to, PH3, and the concentration of the phosphorus doping source is 2%-8%, for example, 3%, 5%, 7%, etc.

[0131] The deposition thickness of the second amorphous silicon-based doped film is 100-300 nm, for example, 150 nm, 200 nm, 250 nm, etc.; the deposition thickness of the second silicon-based mask layer is 5-20 nm, for example, 10 nm, 15 nm, etc.; and the reaction gas of the second silicon-based mask layer is a mixture of SiH4 and N2O.

[0132] It should be noted that the process parameters for each step provided in this method may be, but are not limited to, the parameters listed in the examples in this article, and the relevant parameters may also be the process parameters commonly used in this field.

[0133] After obtaining the second doped silicon substrate, this method can anneal the intermediate of the back contact cell in step S16 to form an electron-doped layer, a hole-doped layer, a tunnel junction, and a neutral doping compensation region. In step S16, this method can drive the phosphorus dopant source of the second doped silicon substrate in the first region into the intrinsic silicon substrate, and drive the boron dopant source of the first doped silicon substrate in the second region into the intrinsic silicon substrate, so that the first region forms an electron-doped layer, the second region forms a hole-doped layer and a tunnel junction, and the third region forms a neutral doping compensation region. The equilibrium crystallization ratio achieved by the films in the first and second regions after high-temperature recombination can reach 80%-90%.

[0134] During the annealing process, the annealing temperature can be between 880 and 980 degrees Celsius, for example, 900 degrees Celsius, 920 degrees Celsius, 950 degrees Celsius, etc. In other embodiments, this step can also use other annealing temperatures that can achieve similar effects.

[0135] In this design, the electron-doped layer is called the N-region, and the hole-doped layer is called the P-region. After annealing, the sheet resistance of the P-region can be 80-160 ohms, for example, 100 ohms, 120 ohms, 150 ohms, etc. Optionally, the sheet resistance of the P-region can be 110-120 ohms, for example, 115 ohms.

[0136] After annealing, the sheet resistance of the N-region can be 15-60 ohms, for example, 20 ohms, 30 ohms, 40 ohms, 50 ohms, etc. After annealing, the crystallinity of the back contact battery can be 90%-95%, for example, 91%, 92%, 93%, 94%, etc.

[0137] In current fabrication processes, after obtaining the second doped silicon substrate, it is often necessary to remove the film layer in the second region (e.g., by using laser etching and wet cleaning to remove the tunneling oxide layer, intrinsic silicon substrate, and second doped silicon substrate in the second region), thus exposing the first doped silicon substrate in the second region. This method, based on the above process, eliminates the need to remove the second doped silicon substrate in the second region after obtaining it. The first and second amorphous silicon-based doped films in the second region will self-assemble during annealing to form a highly doped tunnel junction, exhibiting linear conductor rectification characteristics.

[0138] Optionally, after step S16, the method for fabricating the back contact battery further includes: removing the neutral doping compensation region to expose the semiconductor substrate of the third region. The neutral doping compensation region is formed at the boundary between the N-region and the P-region. By removing the neutral doping compensation region, this application allows the N-region and the P-region to be spaced apart, thereby improving the insulation between the N-region and the P-region.

[0139] Understandably, in related fabrication processes, there is often a risk of incomplete film removal. The neutral-doped compensation region prepared by this method is inherently insulating, which helps reduce the risk of conduction between the N-region and P-region even if the neutral-doped compensation region is not completely removed.

[0140] In this step, the method for removing the neutral doped compensation region can be, but is not limited to, etching, laser removal, etc. Optionally, this step includes: using laser etching to remove part of the neutral doped compensation region in the third region; and using wet cleaning to perform selective chemical etching to etch the remaining neutral doped compensation region in the third region while retaining the semiconductor substrate of the third region.

[0141] Optionally, in the step of removing part of the neutral doped compensation region in the third region using laser etching, the laser power is 60-80W, such as 65W, 70W, 75W, etc., and the laser energy density is 0.25J / cm². 2 -0.35J / cm 2 For example, 0.30 J / cm 2In the selective chemical etching step using wet cleaning, the cleaning temperature is 70-80 degrees Celsius, for example, 75 degrees Celsius.

[0142] For the step of removing the neutral doped compensation region, this method provides the following process parameters as an example:

[0143] Laser source: 60W, 532nm-ps, spot size: 50um*50um;

[0144] The unit energy is 0.25-0.35 J / cm². 2 For example, 0.3 J / cm 2 ;

[0145] The overlap rate is less than 10%, for example, 3%, 5%, 8%, etc.;

[0146] Linear velocity greater than 60m / s, such as 70m / s, 80m / s, 90m / s, etc.

[0147] After removing a portion of the neutral doped compensation region using a laser, this method can further etch the remaining at least a portion of the neutral doped compensation region using a wet cleaning method. Understandably, the second silicon-based mask layer obtained in step S15 can be used to protect the second amorphous silicon-based doped film layer during the step of removing at least a portion of the neutral doped compensation region, preventing the second amorphous silicon-based doped film layer from being etched. After the neutral doped compensation region removal is completed, this method can further remove the second silicon-based mask layer by, for example, but not limited to, hydrofluoric acid cleaning.

[0148] The wet cleaning process for this step is illustrated below:

[0149] The intermediate is subjected to the following steps in sequence: alkaline polishing, water washing, alkaline washing, acid washing, pre-dehydration, and drying. Each cleaning step can be carried out in a cleaning tank, such as an alkaline polishing tank or an alkaline washing tank. In the alkaline polishing step, the solution used is: alkaline chemicals (e.g., KOH, NaOH, etc.) / pure water / additives; the process temperature is 70-80 degrees Celsius, for example, 75 degrees Celsius; the process time is 450-600 seconds, for example, 500 seconds, 550 seconds, etc. In the alkaline washing step, the solution used is: alkaline chemicals (e.g., KOH, NaOH, etc.) / pure water / additives; the process temperature is 55-65 degrees Celsius, for example, 60 degrees Celsius.

[0150] In this method, no mask layer is prepared on the light-receiving surface of the semiconductor substrate. Therefore, after the aforementioned wet cleaning process, the light-receiving surface of the semiconductor substrate is etched to form a pyramidal textured surface, achieving an anti-reflection effect. Since the neutral doped compensation region itself is insulating, in other embodiments, the neutral doped compensation region may not be removed after step S16.

[0151] After the N-region and P-region are prepared, this method may further include steps of preparing a passivation film and an anti-reflection film on the surface of the intermediate body of the back contact battery to achieve anti-reflection and passivation effects. The passivation film can be made of aluminum oxide and can be prepared using the ALD method. The anti-reflection film can be made of silicon nitride and can be prepared using the PECVD method.

[0152] Optionally, the passivation film can be formed on the light-receiving surface, the backlighting surface, and the side surface of the intermediate, covering these surfaces. An antireflection film can be deposited on the passivation film on the light-receiving and backlighting surfaces, covering both surfaces. In other embodiments, the passivation film may only cover the light-receiving and backlighting surfaces of the intermediate.

[0153] This method, after the steps of preparing the passivation film and the antireflection film, also includes the step of preparing a metal electrode to complete the preparation of the back contact battery.

[0154] Please see Figure 3 , Figure 3 This is a schematic diagram of the fabrication process of a back contact battery provided in some embodiments of this application.

[0155] The preparation method of a back contact battery may include the following steps:

[0156] S21: Provides a semiconductor substrate.

[0157] The semiconductor substrate can be an N-type silicon wafer or a P-type silicon wafer. The semiconductor substrate has a light-receiving surface and a back-light surface arranged opposite each other. The second surface includes a first region, a second region, and a third region, with the first and second regions spaced apart, and the third region located between the first and second regions. In this embodiment, an N-type silicon wafer is used as the semiconductor substrate. The semiconductor substrate provided in this step is a pre-treated semiconductor substrate. The pre-treatment includes wet cleaning to polish both sides of the semiconductor substrate and removing the surface damage layer of the semiconductor substrate.

[0158] S22: Tunneling oxide layer and intrinsic silicon base layer are prepared by LPCVD.

[0159] On the back surface of a semiconductor substrate, a tunneling oxide layer and an intrinsic silicon base layer are sequentially fabricated using an LPCVD device. The material can be silicon, silicon carbide, etc. The thickness of the intrinsic silicon base layer can be 50-200 nm, for example, 100 nm.

[0160] S23: The first doped silicon substrate is prepared by PECVD.

[0161] A first doped silicon substrate is fabricated on an intrinsic silicon substrate using a PECVD apparatus. The first doped silicon substrate includes a first amorphous silicon-based doped film and a first silicon-based mask layer. The first amorphous silicon-based doped film includes a boron doping source. The first amorphous silicon-based doped film is fabricated on the intrinsic silicon substrate; the first silicon-based mask layer is fabricated on the first amorphous silicon-based doped film and covers it.

[0162] S24: Laser etching is used to remove part of the first doped silicon substrate in the first region.

[0163] A laser device is used to remove the first silicon-based mask layer and part of the first amorphous silicon-based doped film layer in the first region, while retaining the first silicon-based mask layer in the second region.

[0164] S25: The remaining first doped silicon substrate in the first region is etched using a wet cleaning method.

[0165] Based on the difference in grain size and density between the first amorphous silicon-based doped film and the intrinsic silicon substrate, a chemical solution is used to selectively etch the film in the first region to remove the first amorphous silicon-based doped film, thus exposing the intrinsic silicon substrate in the first region. The first silicon-based mask layer in the second region can protect the first amorphous silicon-based doped film layer in the second region during this step. After the first amorphous silicon-based doped film layer in the first region is removed, hydrofluoric acid is used to remove the first silicon-based mask layer in the second region.

[0166] S26: The second doped silicon substrate is prepared by PECVD.

[0167] The second doped silicon substrate includes a second amorphous silicon-based doped film and a second silicon-based mask layer. In this step, the second amorphous silicon-based doped film is fabricated on the backlight surface using a PECVD device, and a second silicon-based mask layer is fabricated on the second amorphous silicon-based doped film. The second amorphous silicon-based doped film includes a phosphorus doping source.

[0168] S27: Perform annealing.

[0169] Annealing is performed using an annealing device to drive the phosphorus doping source in the first region and the boron doping source in the second region into the corresponding intrinsic silicon substrate. This results in the second amorphous silicon-based doped film in the first region achieving a stable doping curve with the intrinsic silicon substrate, and the grains reaching an equilibrium crystallization ratio after high-temperature recombination, forming the electron doping layer (N region) of the back contact solar cell. Similarly, the first amorphous silicon-based doped film in the second region achieves a stable doping curve with the intrinsic silicon substrate, and the grains reaching an equilibrium crystallization ratio after high-temperature recombination, forming the hole doping layer (P region) of the back contact solar cell.

[0170] In the third region (i.e., the boundary between the first and second regions), a neutral doped region with insulating properties is formed based on the doping compensation and neutralization effect of the phosphorus and boron doping sources. This region is doped with boron and phosphorus at low concentrations. In the second region, the first and second amorphous silicon-based doped films self-assemble to form a highly doped tunnel junction, whose rectification characteristics are those of a linear conductor. Therefore, it is not necessary to remove the second doped silicon substrate in the second region after annealing.

[0171] S28: Laser etching is used to remove part of the neutral doped compensation region in the third region.

[0172] A laser device is used to remove part of the neutral doping compensation region in the third region, so that the N region and P region are spaced apart, thereby reducing the risk of conduction between the N region and P region.

[0173] S29: The remaining neutral doped compensation region in the third region is etched using a wet cleaning process.

[0174] A wet cleaning process is used to remove the remaining neutral doped compensation region in the third region. This neutral doped compensation region has an insulating effect, reducing the risk of conduction between the N and P regions even if it is not completely removed in this step. Simultaneously, the light-receiving surface of the semiconductor substrate is etched to create a pyramidal textured surface, achieving an anti-reflective effect.

[0175] S210: Passivation film and antireflection film are prepared sequentially.

[0176] A passivation film is prepared on the surface of the intermediate body of the back contact battery using an ALD (Alternating Discharge) device. The passivation film can be made of aluminum oxide and covers the light-receiving surface, back-lighting surface, and side surface of the intermediate body. Further, a silicon nitride antireflection film is deposited on the passivation film on the light-receiving and back-lighting surfaces of the intermediate body using a PECVD (Pure Chemical Vapor Deposition) device to achieve double-sided antireflection and passivation effects.

[0177] In the passivation step, a TMA and H2O or TMA and O3 process scheme can be used to prepare an alumina passivation film with a thickness of 4nm-15nm. The deposition temperature of the passivation step is 180-290 degrees Celsius. In the antireflection step, a mixed gas of SiH4, NH3 and N2O can be used to adjust the refractive index of the coating to achieve ideal antireflection and passivation conditions.

[0178] S211: Electrode preparation.

[0179] Electrodes are formed using screen printing or laser transfer, and can be either silver electrodes or silver-clad copper electrodes. In this step, laser etching can be used to create openings in the passivation film and antireflection film in the first and second regions of the backlight surface, forming electrodes at these openings. Specifically, this step can employ BC printing technology, where pastes for the P-region fine gate, N-region fine gate, and P / N-region main gate are dried and sintered / photoinjected, combined with a laser-assisted processing flow to fabricate the positive and negative electrodes.

[0180] For details not covered in this embodiment, please refer to the above text; they will not be repeated here.

[0181] This application also provides a back contact battery, which is prepared by the above-described preparation method. The following mainly focuses on the preparation method... Figure 3 The back contact battery prepared by the method shown is illustrated as an example. It is understood that the specific process of the preparation method provided in the embodiments of this application may not be limited to one type, and therefore the structure of the back contact battery prepared by the above method may not be limited to one structure.

[0182] Please see Figures 4 to 15 ,in, Figures 4 to 14 The intermediate structure of the back contact battery obtained through each process step is shown in sequence. Figure 15 The structure of the fabricated back contact battery is shown. For ease of explanation, the back contact battery 100 and its intermediate body are divided into a first region A and a second region B, and the boundary between the first region A and the second region B is defined as a third region C.

[0183] As described in step S21 above and Figure 4 As shown, this application embodiment provides a semiconductor substrate 11.

[0184] Through the above step S22, the result is as follows: Figure 5 The intermediate shown includes a semiconductor substrate 11, a tunneling oxide layer 12, and an intrinsic silicon base layer 13 stacked sequentially.

[0185] Through the above step S23, the result is as follows: Figure 6 The intermediate shown, the intermediate in Figure 5 Based on the intermediate shown, a first doped silicon substrate 14 is also included. The first doped silicon substrate 14 is disposed on the intrinsic silicon substrate 13. The first doped silicon substrate 14 includes a first amorphous silicon-based doped film layer 141 and a first silicon-based mask layer 142. The semiconductor substrate 11, tunneling oxide layer 12, intrinsic silicon substrate 13, first amorphous silicon-based doped film layer 141 and first silicon-based mask layer 142 are sequentially stacked.

[0186] Through the above step S24, the result is as follows: Figure 7 The intermediate shown. Figure 7 The intermediate shown is made from Figure 6 The intermediate shown is obtained by removing the first silicon-based mask layer 142 and part of the first amorphous silicon-based doped film layer 141 in the first region A by laser melting.

[0187] Through the above step S25, the result is as follows: Figure 8 The intermediate shown. This intermediate is made from... Figure 7 The intermediate shown is obtained by removing the remaining first amorphous silicon-based doped film 141 in the first region A by chemical etching and by removing the first silicon-based mask layer 142 in the second region B. Figure 8 The intermediate shown is exposed to the intrinsic silicon substrate 13 in the first region A.

[0188] Through the above step S26, the result is as follows: Figure 9 The intermediate shown, the intermediate in Figure 8 Based on the intermediate shown, a second doped silicon substrate 15 is also included. In the first region A, the second doped silicon substrate 15 is disposed on the exposed intrinsic silicon substrate 13; in the second region B, the second doped silicon substrate 15 is disposed on the first amorphous silicon-based doped film layer 141. The second doped silicon substrate 15 includes a second amorphous silicon-based doped film layer 151 and a second silicon-based mask layer 152 stacked sequentially, with the second silicon-based mask layer 152 disposed on the side of the second amorphous silicon-based doped film layer 151 facing away from the intrinsic silicon substrate 13.

[0189] Through the above step S27, the result is as follows: Figure 10 The intermediate shown comprises an electron-doped layer 21 and a hole-doped layer 22. The electron-doped layer 21 is obtained by driving a phosphorus dopant source from a first region A into the intrinsic silicon substrate 13, and the hole-doped layer 22 is obtained by driving a boron dopant source region from a second region B into the intrinsic silicon substrate 13. As described above, the intermediate also has a neutral doping compensation region (not shown) formed in a third region and a tunnel junction (not shown) formed in the second region.

[0190] Through the above step S28, the result is as follows: Figure 11 The intermediate shown, the intermediate in Figure 10 Based on the intermediate shown, a portion of the film layer in the third region is removed by laser melting.

[0191] Through the above step S29, the result is as follows: Figure 12 The intermediate shown, the intermediate in Figure 11Based on the intermediate shown, the remaining film layer in the third region is removed by chemical etching, exposing the semiconductor substrate 11. The light-receiving surface of the semiconductor substrate 11 is formed by chemical etching to create a pyramidal textured surface, that is, the light-receiving surface of the semiconductor substrate 11 is a rough surface.

[0192] Through the above step S210, the result is as follows: Figure 13 and Figure 14 The intermediate shown. Figure 13 The intermediate shown also includes a passivation film 16, which will... Figure 12 The intermediate shown is coated to form Figure 13 The structure shown is such that a passivation film 16 covers the light-receiving surface, the backlighting surface, and the side surface of the intermediate. Figure 14 The intermediate shown also includes an antireflective coating 17, which covers... Figure 13 The light-receiving and back-light-receiving surfaces of the intermediate shown are used to form Figure 14 The structure shown.

[0193] Through the above step S211, the result is as follows: Figure 15 The back contact battery 100 shown, the back contact battery 100 in Figure 14 Based on the intermediate shown, it also includes a first electrode 23 and a second electrode 24. The first electrode 23 is disposed in the first region A and contacts the electron-doped layer 21, and the second electrode 24 is disposed in the second region B and contacts the hole-doped layer 22. The first electrode 23 is the negative electrode of the back-contact battery 100, and the second electrode 24 is the positive electrode of the back-contact battery 100.

[0194] For details regarding the structure of the back contact battery 100 that are not fully described, please refer to the above text; they will not be repeated here.

[0195] It should be understood that the terminology used in this specification and appended claims is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. Similarly, the terms “first” and “second” in the description of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include one or more of the stated features. Furthermore, the term “multiple” in the description of this application means two or more, unless otherwise explicitly specified.

[0196] In the description of this application, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0197] The above description is only a partial embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for preparing a back contact battery, characterized in that, The method for preparing the back contact battery includes: A semiconductor substrate is provided, which has a light-receiving surface and a back-lighting surface after chemical polishing. A tunneling oxide layer and an intrinsic silicon base layer are sequentially stacked on the back-lighting surface. A first doped silicon substrate is prepared on the intrinsic silicon substrate; Holes are alternately opened in a portion of the backlight surface, the area with holes is the first area, and the area without holes is the second area. The first doped silicon substrate in the first area is removed, so that the intrinsic silicon substrate in the first area is exposed. A second doped silicon substrate is prepared on the backlight surface; The intermediate body of the back contact battery is annealed to form an electron-doped layer, a hole-doped layer, a tunnel junction, and a neutral doping compensation region. The electron-doped layer is formed by a doping source from the second-doped silicon substrate in the first region being driven into the intrinsic silicon substrate. The hole-doped layer is formed by a doping source from the first-doped silicon substrate in the second region being driven into the intrinsic silicon substrate. The tunnel junction is formed by the self-assembly of the first-doped silicon substrate and the second-doped silicon substrate stacked in the second region. The neutral doping compensation region is located in a third region at the boundary between the first region and the second region.

2. The method for preparing a back contact battery according to claim 1, characterized in that, The intrinsic silicon substrate and the first doped silicon substrate are prepared by different deposition methods, including low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition. Based on the film layer differences between the intrinsic silicon substrate and the first doped silicon substrate achieved by different deposition methods, the first doped silicon substrate in the first region is removed, thereby exposing the intrinsic silicon substrate in the first region.

3. The method for preparing a back contact battery according to claim 2, characterized in that, The intrinsic silicon substrate is prepared by low-pressure chemical vapor deposition at a deposition temperature of 500-650 degrees Celsius; the first doped silicon substrate is prepared by plasma-enhanced chemical vapor deposition at a deposition temperature of 200-450 degrees Celsius.

4. The method for preparing a back contact battery according to claim 1, characterized in that, The step of removing the first doped silicon substrate in the first region to expose the intrinsic silicon substrate in the first region includes: Laser etching is used to remove a portion of the first doped silicon substrate in the first region; Selective chemical etching is performed using wet cleaning to etch the remaining first doped silicon substrate in the first region while retaining the intrinsic silicon substrate in the first region.

5. The method for preparing a back contact battery according to claim 4, characterized in that, The laser power is 60-80W, and the laser energy density is 0.25J / cm². 2 -0.35J / cm 2 In the step of selective chemical etching using wet cleaning, the cleaning temperature is 65-75 degrees Celsius.

6. The method for preparing a back contact battery according to claim 1, characterized in that, The intrinsic silicon substrate has a deposition thickness of 50-200 nm.

7. The method for preparing a back contact battery according to claim 1, characterized in that, The tunneling oxide layer is prepared by low-pressure chemical vapor deposition at a deposition temperature of 400-700 degrees Celsius; the second doped silicon substrate is prepared by plasma-enhanced chemical vapor deposition at a deposition temperature of 350-500 degrees Celsius.

8. The method for preparing a back contact battery according to claim 1, characterized in that, During the annealing process, the annealing temperature is 880-980 degrees Celsius.

9. The method for preparing a back contact battery according to claim 1, characterized in that, After the step of annealing the intermediate of the back contact battery, the method for preparing the back contact battery further includes: Removing the neutral doping compensation region from the third region to expose the semiconductor substrate in the third region specifically includes: Laser etching is used to remove a portion of the neutral doping compensation region in the third region; Selective chemical etching is performed using wet cleaning to etch the remaining neutral doped compensation region in the third region while retaining the semiconductor substrate in the third region.

10. The method for preparing a back contact battery according to claim 9, characterized in that, The laser power is 60-80W, and the laser energy density is 0.25J / cm². 2 -0.35J / cm 2 In the step of selective chemical etching using wet cleaning, the cleaning temperature is 70-80 degrees Celsius.

11. The method for preparing a back contact battery according to claim 9, characterized in that, After the step of removing the neutral doped compensation region in the third region, the method for fabricating the back contact cell further includes: A passivation film and an anti-reflection film are sequentially prepared on the surface of the intermediate body of the back contact battery; wherein the passivation film covers the light-receiving surface and the back-light surface of the intermediate body, or the passivation film covers the light-receiving surface, the back-light surface and the side surface of the intermediate body; the anti-reflection film covers the light-receiving surface and the back-light surface of the intermediate body.

12. The method for preparing a back contact battery according to any one of claims 1-11, characterized in that, The first doped silicon substrate includes a boron doping source, and the second doped silicon substrate includes a phosphorus doping source; or The first doped silicon substrate includes a phosphorus doping source, and the second doped silicon substrate includes a boron doping source.

13. A back-contact battery, characterized in that, The back contact battery is prepared by the back contact battery preparation method according to any one of claims 1-12.

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