Three-dimensional memory device and method for forming three-dimensional memory device

Abstract

A three-dimensional (3D) memory device (400) and a method for forming a three-dimensional (3D) memory device (400) are disclosed. In certain aspects, the 3D memory device comprises: a stack comprising interleaved conductive layers (414) and dielectric layers (416); and a channel structure (412) extending through the stack in a first direction (Y). The channel structure includes a memory film (424) and a semiconductor channel (422) exceeding the memory film in a first direction, and the memory film surrounds the semiconductor channel. An adhesive layer (440) is disposed on the semiconductor channel beyond the memory film and is in contact with the semiconductor channel beyond the memory film. A conductor layer (442) is disposed on the adhesive layer and is in contact with the adhesive layer.

Description

Background Art

[0001] The present disclosure relates to a three-dimensional (3D) memory device and a method of manufacturing the same.

[0002] Planar memory cells have been scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing techniques. However, as the feature size of memory cells approaches a lower limit, planar processing and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] 3D memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0004] In one aspect, the present disclosure provides a three-dimensional (3D) memory device. The 3D memory device may include: a memory stack including interlaced conductive layers and dielectric layers; and a channel structure extending through the memory stack in a first direction. The channel structure may include a memory film and a semiconductor channel extending beyond the memory film in the first direction, and the memory film may surround the semiconductor channel. An adhesive layer may be disposed on the semiconductor channel extending beyond the memory film and in contact with the semiconductor channel extending beyond the memory film. A conductor layer may be disposed on the adhesive layer and in contact with the adhesive layer.

[0005] In some embodiments, the adhesion layer may contact a sidewall of the semiconductor channel beyond the memory film.

[0006] In some embodiments, the adhesive layer may be in contact with the memory stack at one side of the adhesive layer and in contact with the conductor layer at another side of the adhesive layer.

[0007] In some embodiments, the adhesion layer may include one of a Ti / TiN layer, a Ta / TaN layer, or a composite layer having a conductive material.

[0008] In some embodiments, the thickness of the adhesive layer may be between about With between.

[0009] In some embodiments, a 3D memory device may include: a plurality of peripheral contacts, each of the plurality of peripheral contacts extending in a first direction and contacting an adhesive layer; and a first isolation structure extending through the conductor layer and the adhesive layer and in a second direction perpendicular to the first direction. The first isolation structure may include a dielectric material.

[0010] In some embodiments, a first isolation structure can be disposed between two peripheral contacts of the plurality of peripheral contacts to electrically isolate the two peripheral contacts.

[0011] In some embodiments, a 3D memory device may include a gap structure extending through a memory stack in a first direction, wherein the gap structure may include a gap core and an insulating layer surrounding the gap core. The gap core may include a conductive material. The gap core may extend beyond the insulating layer in the first direction and may contact the adhesive layer.

[0012] In some embodiments, the adhesive layer may contact the sidewalls of the slot core beyond the insulating layer.

[0013] In some embodiments, the insulating layer of the slit structure may be substantially flush with a top surface of the memory stack.

[0014] In some embodiments, the 3D memory device may include a second isolation structure extending through the conductor layer and stopping at an adhesion layer located on the seam structure. The second isolation structure may include a dielectric material.

[0015] In some embodiments, the memory stack may include a first conductive layer in contact with a side of the adhesive layer opposite the conductor layer.

[0016] In some embodiments, the first conductive layer may be a polysilicon layer.

[0017] In some embodiments, the first conductive layer may be one of the conductive layers of the memory stack that is closest to the adhesive layer.

[0018] In some embodiments, the first conductive layer can include tungsten.

[0019] In some embodiments, the semiconductor channel may exceed the first conductive layer in the first direction, and the adhesion layer may contact at least a portion of the first conductive layer.

[0020] In some embodiments, an upper end of the memory film may be substantially flush with a top surface of the first conductive layer.

[0021] In some embodiments, an upper end of the memory film may be lower than a top surface of the first conductive layer.

[0022] In some embodiments, a 3D memory device may include a gap structure that extends through a memory stack in a first direction, wherein the gap structure may include a gap core that includes a conductive material; and the gap core may exceed the first conductive layer in the first direction and may contact the adhesive layer.

[0023] In some embodiments, the conductor layer can include at least one of aluminum or tungsten.

[0024] In some embodiments, a 3D memory device may include a peripheral contact extending in a first direction and may be in contact with the adhesive layer.

[0025] In some embodiments, the adhesive layer can contact the sidewalls of the peripheral contacts.

[0026] In some embodiments, the memory stack may include a first conductive layer in contact with the adhesive layer, wherein the first conductive layer may be a polysilicon layer; and the polysilicon layer may extend in a third direction perpendicular to the first direction. The peripheral contacts and the channel structure may penetrate the polysilicon layer.

[0027] In one aspect, the present disclosure provides a method for forming a three-dimensional (3D) memory device. The method may include: forming a first semiconductor structure, the first semiconductor structure including a memory stack and a channel structure, the channel structure extending through the memory stack in a first direction and including a memory film and a semiconductor channel, the memory film surrounding the semiconductor channel; removing a portion of the memory film to expose a portion of the semiconductor channel; forming an adhesive layer disposed on and in contact with a portion of the semiconductor channel exposed beyond a remaining portion of the memory film; and forming a conductor layer disposed on and in contact with the adhesive layer.

[0028] In some embodiments, forming the adhesion layer may include forming the adhesion layer in contact with a sidewall of the semiconductor channel beyond the memory film.

[0029] In some embodiments, forming the first semiconductor structure may further include: forming a channel hole extending in a first direction through the stacked structure, a portion of the stacked structure being replaced to form a memory stack; and forming a storage film and a semiconductor channel along sidewalls of the channel hole to form a channel structure. The storage film may include a tunneling layer, a storage layer, and a barrier layer.

[0030] In some embodiments, the method may further include: removing a first portion of the conductor layer and a first portion of the adhesive layer to expose the memory stack and form a first trench extending in a second direction perpendicular to the first direction; and filling the first trench with a dielectric material to form a first isolation structure.

[0031] In some embodiments, forming the first semiconductor structure may further include forming a slot structure extending through the memory stack in a first direction, wherein the slot structure may include a slot core and an insulating layer surrounding the slot core, and the slot core may include a conductive material. The method may further include removing a portion of the insulating layer at one end of the slot structure to form an exposed slot core extending beyond the insulating layer in the first direction; and forming the adhesive layer may include forming the adhesive layer in contact with the exposed slot core.

[0032] In some embodiments, forming the adhesive layer may further include forming the adhesive layer in contact with sidewalls of the exposed slit core exceeding the insulating layer.

[0033] In some embodiments, the method may further include: removing a second portion of the conductor layer to form a second trench, thereby exposing the adhesive layer located on the gap core, the second trench extending in a second direction perpendicular to the first direction; and filling the second trench with a dielectric material to form a second isolation structure.

[0034] In some embodiments, removing a portion of the memory film may include removing a portion of the memory film surrounding one end of the semiconductor channel, stopping at the memory stack.

[0035] In some embodiments, forming the first semiconductor structure may further include: forming a first conductive layer over the substrate; and forming a channel structure extending through the first conductive layer into the substrate.

[0036] In some embodiments, removing the portion of the memory film may include removing a portion of the memory film, stopping at the first conductive layer.

[0037] In some embodiments, forming a first conductive layer may include: forming a polysilicon layer above a substrate; and forming a first semiconductor structure may also include: after forming the polysilicon layer, forming a stack structure including an alternating sacrificial layer and a dielectric layer; and replacing the sacrificial layer of the stack structure with a conductive layer to form a memory stack.

[0038] In some embodiments, the polysilicon layer may extend from a memory core region of the 3D memory device to a peripheral region of the 3D memory device in a second direction perpendicular to the first direction.

[0039] In some embodiments, forming the first semiconductor structure may include forming a stacked structure including alternating sacrificial layers and dielectric layers; and forming the first conductive layer may include replacing one of the sacrificial layers closest to the substrate with a conductive layer. The first conductive layer may include a conductive layer.

[0040] In some embodiments, forming the adhesive layer may include forming the adhesive layer in contact with at least a portion of the first conductive layer.

[0041] In some embodiments, the method may further include performing a surface treatment on the exposed portion of the semiconductor channel before forming the adhesion layer.

[0042] In some embodiments, the surface treatment can include laser activation.

[0043] In some embodiments, the method may further include: forming a second semiconductor structure including a peripheral circuit of the 3D memory device; and bonding the first semiconductor structure to the second semiconductor structure.

[0044] In some embodiments, forming the first semiconductor structure may further include: forming a first bonding layer; forming the second semiconductor structure may further include: forming a second bonding layer; and bonding the first semiconductor structure to the second semiconductor structure may include: bonding the first bonding layer of the first semiconductor structure to the second bonding layer of the second semiconductor structure.

[0045] In some embodiments, the peripheral circuit of the second semiconductor structure may be coupled to the memory stack of the first semiconductor structure through the first bonding layer and the second bonding layer.

[0046] In one aspect, the present disclosure provides a system. The system may include a 3D memory device configured to store data and comprising: a first semiconductor structure comprising a memory stack including interleaved conductive layers and dielectric layers; a channel structure extending through the memory stack in a first direction, the channel structure comprising a memory film and a semiconductor channel extending beyond the memory film in the first direction, the memory film surrounding the semiconductor channel; an adhesive layer disposed on and in contact with the semiconductor channel extending beyond the memory film; and a conductor layer disposed on and in contact with the adhesive layer; and a second semiconductor structure comprising peripheral circuitry bonded to the first semiconductor structure. The system may also include a memory controller coupled to the 3D memory device and configured to control the 3D memory device.

[0047] In some implementations, the system can include a host coupled to a memory controller.

[0048] In some implementations, the memory controller can be coupled to the 3D memory device through a conductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0050] Figure 1 A side view of a cross section of a 3D memory device is shown.

[0051] Figure 2A A flowchart illustrating an exemplary method for forming a 3D memory device according to some aspects of the present disclosure is shown.

[0052] Figure 2B A flowchart is shown of another exemplary method for forming a 3D memory device according to aspects of the present disclosure.

[0053] Figure 3 A schematic diagram of an exemplary 3D memory device according to some aspects of the present disclosure is shown.

[0054] Figures 4A-4E A fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure is shown.

[0055] Figure 5A-5B Various configurations of semiconductor channels according to aspects of the present disclosure are shown, each semiconductor channel extending beyond a storage film in the channel structure.

[0056] Figures 6A-6E A fabrication process for forming another exemplary 3D memory device according to aspects of the present disclosure is shown.

[0057] Figures 7A-7E A fabrication process for forming yet another exemplary 3D memory device according to aspects of the present disclosure is shown.

[0058] Figure 8 A block diagram of an exemplary system having a 3D memory device according to some aspects of the present disclosure is shown.

[0059] Figure 9A A diagram is shown of an exemplary memory card having a 3D memory device according to some aspects of the present disclosure.

[0060] Figure 9B A diagram of an exemplary solid-state drive (SSD) having a 3D memory device according to aspects of the present disclosure is shown.

[0061] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0062] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of this disclosure. Moreover, this disclosure may also be used in a variety of other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with each other and in ways not explicitly depicted in the accompanying drawings, so that such combinations, adjustments, and modifications are within the scope of this disclosure.

[0063] Generally, terms can be understood, at least in part, from usage in context. For example, depending at least in part on the context, the terms "at least one" and "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "an" or "the" can also be understood to convey singular usage or to convey plural usage. Additionally, also depending at least in part on the context, the terms "based on" and "according to" can be understood as not necessarily intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described.

[0064] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “over” means not only “over something” or “on something,” but also can include the meaning of “over something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0065] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0066] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0067] As used herein, the term "layer" may refer to a material portion comprising an area with a thickness. A layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below. A layer may comprise multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (wherein interconnect lines and / or vertical interconnect via contacts are formed) and one or more dielectric layers.

[0068] As the layers of 3D memory devices increase, backside source technology has achieved further performance optimization and cost reduction. This advancement has a significant impact on the semiconductor industry. For example, Figure 1 1 shows a side view of a cross section of the 3D memory device 100. Figure 1 As shown, the 3D memory device 100 may include a memory structure 102 bonded to a complementary metal oxide semiconductor (CMOS) structure 104 at a bonding interface 106. The memory structure 102 may include multiple semiconductor structures (e.g., one or more channel structures 108, one or more gap structures 110, one or more contact structures 112, and other components), while the semiconductor CMOS structure 104 may include one or more semiconductor circuits ( Figure 1 not shown).

[0069] In the 3D memory device 100, the copper interface formed in the bonded semiconductor structure and the structure itself may impose certain restrictions on the post-bonding thermal treatment process. For example, the manufacturing process may require that the bottom polysilicon layer 114 in the 3D memory device 100 be deposited at a relatively low temperature. Subsequently, a portion of the bottom polysilicon layer 114 may be removed to expose the memory stack 116 at its bottom (given that the bottom polysilicon layer 114 is not formed). Figure 1 ), and an oxide layer 118 may be formed on the remaining bottom polysilicon layer 114 and the exposed memory stack 116. Thereafter, a portion of the oxide layer 118 may be removed (e.g., by etching) to form a trench. As a result, one or more conductive materials (e.g., aluminum) may be deposited in the trench to serve as a pad 120 in this backside trench isolation structure.

[0070] It is worth noting that at least the combination of the above-mentioned techniques may result in process complexity, which may pose challenges in semiconductor production. In addition, issues related to polysilicon activation reflow and material diffusion (e.g., silicon / aluminum diffusion between the bottom polysilicon layer 114 and the pad 120) may need to be considered and resolved. It is well known that simplifying the semiconductor manufacturing process may be a key goal to enhance production efficiency and product quality. Therefore, by reducing process complexity, better control of process and cost can be expected.

[0071] In view of the above disadvantages, the present disclosure introduces one or more solutions, wherein a portion of the memory film can be removed from the channel structure of the memory structure 102, and a conductive material can be formed to connect the semiconductor channel and the contact structure. Figure 1 The bottom polysilicon layer 114 shown in FIG is a film. Therefore, the backside pad isolation can be omitted. At the same time, after removing part of the storage film, gate induced drain leakage (GIDL) activation can be completed by a surface treatment process (e.g., laser activation) on the exposed surface. As a result, the conductive material can replace the bottom polysilicon layer 114 and serve as part of the pad structure as well as the backside common source structure. In short, the backside manufacturing process can be simplified and the cost can also be reduced.

[0072] Figure 2A FIG. 1 is a flow chart illustrating an exemplary method 200 for forming a 3D memory device according to some aspects of the present disclosure. Figure 3 Schematic diagram of an exemplary 3D memory device 300 according to some aspects of the present disclosure is shown. It should be understood that the operations shown in method 200 are not exhaustive, and other techniques may also be applied before, after, or between any of the operations shown. In addition, Figure 2A Some of the operations in the Figure 2A The operations shown in the figure are performed in a different order.

[0073] refer to Figure 2A , the method 200 may begin at operation 202, wherein a first semiconductor structure 304 (in Figure 3 ) can be formed on a carrier substrate 302, and at operation 204, a second semiconductor structure 306 can be formed on another substrate 310. In some embodiments, the first semiconductor structure 304 and the second semiconductor structure 306 can be formed sequentially, while in other embodiments, they can be formed in a parallel manner. Subsequently, at operation 206, as shown Figure 3 As shown, a first semiconductor structure 304 located on a carrier substrate 302 may be bonded to a second semiconductor structure 306 located on a substrate 310 in a face-to-face bonding manner to form a bonding interface 308 .

[0074] In the present disclosure, the term "face-to-face bonding" may be used to refer to bonding the first semiconductor structure 304 and the second semiconductor structure 306 in a manner such that the carrier substrate 302 and the substrate 310 are arranged outside the bonding structure, thereby forming a bonding interface 308 between the first semiconductor structure 304 and the second semiconductor structure 306. In some embodiments of the present disclosure, the bonding technique may include hybrid bonding. In some embodiments, a treatment process (e.g., plasma treatment, wet treatment, and / or thermal treatment) may be applied to the bonding surface(s) of at least one of the first semiconductor structure 304 and the second semiconductor structure 306 to improve the bonding conditions before the bonding operation.

[0075] Additionally, the term "memory device" may be used to refer to a bonded chip that includes a first semiconductor structure 304, which may include a memory structure, and a second semiconductor structure 306, which may include a semiconductor circuit (e.g., configured to control the memory structure). In some examples, the first semiconductor structure 304 and the second semiconductor structure 306 may be joined at a bonding interface 308. In some embodiments, each of the carrier substrate 302 and the substrate 310 may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0076] Figures 4A-4E A fabrication process for forming an exemplary 3D memory device 400 is shown, according to some aspects of the present disclosure. Figure 2A and Figures 4A-4E They will be described together below.

[0077] Obviously, Figures 4A-4E The x-axis and y-axis in FIG. 4 are used to illustrate the spatial relationships of components in a 3D memory device 400 having a substrate 310 on which a second semiconductor structure 306 is formed. The substrate 310 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, when the substrate is located in the lowest plane of the semiconductor device in the y-direction, it is possible to determine whether a component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of the semiconductor device (e.g., the 3D memory device 400) relative to the substrate (e.g., substrate 310) in the y-direction (i.e., the vertical direction). The same concept used to describe spatial relationships can be applied throughout this disclosure.

[0078] exist Figure 2A At operation 206 in , the following can be obtained: Figure 4A, a bonding structure of a memory device having a first semiconductor structure 304 and a second semiconductor structure 306 is shown in FIG. In some embodiments, the memory device may include a 3D memory device 400. In some examples, the first semiconductor structure 304 of the 3D memory device 400 may include a first bonding layer 404 located at a bonding interface 308. The first bonding layer 404 may include a plurality of first bonding contacts 406 and a dielectric electrically isolating the first bonding contacts 406. The first bonding contacts 406 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The remaining areas of the first bonding layer 404, excluding the first bonding contacts 406, may be formed using a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The first bonding contacts 406 and the surrounding dielectric in the first bonding layer 404 may be used for hybrid bonding.

[0079] To form the first bonding layer 404, an ILD layer may be deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, a first bonding contact 406 may be formed through the ILD layer using wet etching and / or dry etching (e.g., reactive ion etching (RIE)), followed by one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0080] Similarly, if Figure 4AAs shown, the second semiconductor structure 306 of the 3D memory device 400 may include a second bonding layer 408 located at the bonding interface 308. The second bonding layer 408 of the second semiconductor structure 306 may include a plurality of second bonding contacts 410 and a dielectric electrically isolating the second bonding contacts 410. Similarly, the second bonding contacts 410 of the second semiconductor structure 306 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining region of the second bonding layer 408 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The second bonding contacts 410 located in the second bonding layer 408 and the surrounding dielectric may be used for hybrid bonding. In some embodiments, in a face-to-face bonding, the second bonding contacts 410 of the second semiconductor structure 306 and the first bonding contacts 406 of the first semiconductor structure 304 may be in direct contact to achieve electrical connection. The second bonding layer 408 and the second bonding contact 410 of the second semiconductor structure 306 may be formed similarly to the first bonding layer 404 and the first bonding contact 406 .

[0081] In some embodiments, a bonding interface 308 can be formed between the first bonding layers 404 and 408 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) that can achieve both metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 308 can refer to the location where the first bonding layer 404 and the second bonding layer 408 meet and bond. In practice, the bonding interface 308 can be a layer of a particular thickness that includes the top surface of the first bonding layer 404 of the first semiconductor structure 304 and the bottom surface of the second bonding layer 408 of the second semiconductor structure 306.

[0082] In some embodiments, the first semiconductor structure 304 of the 3D memory device 400 may further include an interconnect layer 420 located above the first bonding layer 404 to transmit electrical signals. The interconnect layer 420 may include multiple interconnects, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Figure 4AThe interconnect layer 420 in the interconnect layer 420 is simplified to a single layer with certain interconnects. However, it is understood that the interconnect layer 420 may also include one or more ILD layers in which interconnect lines and VIA contacts may be formed. The interconnect lines and VIA contacts located in the interconnect layer 420 may include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer located in the connection layer 420 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0083] In some embodiments, the 3D memory device 400 may include a NAND flash memory device in which memory cells may be provided in the form of an array of NAND memory strings. Each NAND memory string may include a corresponding channel structure 412. For example, Figure 4A As shown, each channel structure 412 can extend vertically through a plurality of pairs, each pair of the plurality of pairs including a stacked conductive layer 414 and a stacked dielectric layer 416. The interlaced stacked conductive layers 414 and stacked dielectric layers 416 can be part of a memory stack 418. The number of pairs of stacked conductive layers 414 and stacked dielectric layers 416 in the memory stack 418 can determine the number of memory cells in the 3D memory device 400. It should be understood that in some embodiments, the memory stack 418 can have a multi-level architecture (not shown) that can include multiple memory levels stacked on top of each other. The number of pairs of stacked conductive layers 414 and stacked dielectric layers 416 in each memory level can be the same or different. In the figures, the number of pairs of stacked conductive layers 414 and stacked dielectric layers 416 is shown for illustrative purposes only and is not intended to limit the present disclosure.

[0084] As described above, the memory stack 418 may include a plurality of interleaved stack conductive layers 414 and stack dielectric layers 416. The stack conductive layers 414 and stack dielectric layers 416 in the memory stack 418 may be arranged in a vertical direction (ie, along the Figure 4Ay-axis in the memory stack 418). In other words, except for the layers located at the top or bottom of the memory stack 418, each stack conductive layer 414 can be adjacent to two stack dielectric layers 416 on both sides, and each stack dielectric layer 416 can be adjacent to two stack conductive layers 414 on both sides. The stack conductive layers 414 can include a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each stack conductive layer 414 can include a gate electrode surrounded by an adhesion layer and a gate dielectric layer. The gate electrodes of the stack conductive layers 414 can extend laterally as word lines, terminating at one or more stepped structures of the memory stack 418. The stack dielectric layers 416 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0085] In some embodiments, each channel structure 412 can be formed by a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel 422) and a composite dielectric layer (e.g., as a storage film 424). In some embodiments, the semiconductor channel 422 can include silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. In some embodiments, the storage film 424 can be a composite layer that includes a tunneling layer, a storage layer (also known as a "charge trapping layer"), and a blocking layer. In one example, the term "storage film" can refer to a composite layer of silicon oxide / silicon oxynitride / silicon oxide (or referred to as an "ONO" structure), including a tunneling layer, a storage layer, a blocking layer, and any other appropriate layers. The channel hole can be completely or partially filled with a cap layer and / or an air gap including a dielectric material (e.g., silicon oxide). The channel structure 412 can have a cylindrical shape (e.g., a pillar shape). In some embodiments, the capping layer, semiconductor channel 422, tunneling layer of storage film 424, storage layer, and barrier layer may be arranged radially from the center of the pillar to the outer surface in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof.

[0086] To form the memory stack 418, in some embodiments, a stack structure including multiple pairs of first dielectric layers (referred to herein as "stack sacrificial layers") and second dielectric layers (referred to herein as "stack dielectric layers") can be formed on the carrier substrate 302. In the present disclosure, the stack sacrificial layers and the stack dielectric layers together can be referred to as "dielectric layer pairs". The stack structure can include staggered stack sacrificial layers and stack dielectric layers. The stack dielectric layers and the stack sacrificial layers can be alternately deposited over the carrier substrate 302 to form a stack structure. In some embodiments, each stack dielectric layer can include a layer of silicon oxide, and each stack sacrificial layer can include a layer of silicon nitride. The stack structure can be formed by one or more thin film deposition processes, including but not limited to: CVD, PVD, ALD, or any combination thereof.

[0087] In some embodiments, a staircase structure may be formed on the edge of the stack structure. The staircase structure may be formed by performing multiple so-called “trim-etch” cycles on the dielectric layer pair of the stack structure toward the carrier substrate 302. Figure 4A As shown, due to repeated trim-etch cycles applied to the dielectric layer pairs of the stacked structure, the stacked structure may have one or more sloped edges and a top dielectric layer pair that is shorter than a bottom dielectric layer pair.

[0088] In order to form a channel structure 412 that extends vertically through the stack structure into the carrier substrate 302, a plurality of openings can be formed such that each opening can correspond to a channel hole and can be a location for forming a single channel structure 412 in a subsequent process. In some embodiments, the manufacturing process for forming the channel holes of the channel structure 412 can include wet etching and / or dry etching, such as deep RIE (DRIE). According to some embodiments, the etching of the channel holes continues until it stops, for example, at the carrier substrate 302. In some embodiments, the etching conditions (e.g., etching rate and time, and the applied etchant) can be controlled to ensure that each channel hole has reached the carrier substrate 302. In some embodiments, multiple etching operations can be employed, and subsequent (multiple) etching operations can be continued until each channel hole reaches the carrier substrate 302 to minimize groove variations in the channel holes and the channel structures 412 formed therein. The present disclosure is not limited in this regard.

[0089] Subsequently, a storage film 424 including a barrier layer, a storage layer, and a tunneling layer, and a semiconductor channel can be sequentially formed along the sidewalls and bottom surface of the channel hole in this order. In some embodiments, the barrier layer, the storage layer, and the tunneling layer can first be deposited in this order along the sidewalls and bottom surface of the channel hole using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the storage film 424. In some examples, a semiconductor material (e.g., polysilicon (e.g., undoped polysilicon)) can then be deposited over the tunneling layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the semiconductor channel 422. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (or referred to as a "SONO" structure) can be sequentially deposited to form the barrier layer, storage layer, and tunneling layer of the storage film 424, as well as the semiconductor channel 422. As a result, the memory film 424 may be formed to surround the semiconductor channel 422 at the periphery of the semiconductor channel 422 .

[0090] In some embodiments, a capping layer may be formed in the channel hole to completely or partially fill the channel hole. By adjusting the amount of the capping layer filled, the semiconductor channel 422 may be formed with or without an air gap. The capping layer may be formed by depositing a dielectric material (e.g., silicon oxide) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, a channel plug 426 may then be formed in the top portion of the channel hole (the "top" orientation being defined before the first semiconductor structure 304 is flipped and bonded to the second semiconductor structure 306). The channel plug 426 may include a semiconductor material (e.g., polysilicon).

[0091] To form the channel plug 426, in some embodiments, the portion of the storage film 424, the semiconductor channel 422, and the cap layer disposed on the top surface of the stacked structure may be removed and planarized by chemical mechanical polishing (CMP), wet etching, and / or dry etching. A recess may then be formed in the top portion of the channel hole by wet etching and / or dry etching the portion of the semiconductor channel 422 and the cap layer in the top portion of the channel hole. Subsequently, the channel plug 426 may be formed by depositing a semiconductor material (e.g., polysilicon) into the recess via one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). In some embodiments, the channel plug 426 may function as a drain of the channel structure 412.

[0092] To replace the stack structure to form the memory stack 418, in some embodiments, a slit opening can be formed that extends vertically through the stack structure into the carrier substrate 302. According to some embodiments, etching of the slit openings can continue until stopped, for example, at the carrier substrate 302. In some embodiments, etching conditions (e.g., etching rate and time, as well as the applied etchant) can be controlled to ensure that each slit opening has reached the carrier substrate 302. In some embodiments, the manufacturing process for forming the slit openings can include wet etching and / or dry etching (e.g., DRIE). Gate replacement can then be performed through the slit openings to replace the stack structure with the memory stack 418, which includes the stack conductive layer 414 and the stack dielectric layer 416. In some embodiments, a plurality of lateral recesses can be formed by removing the stack sacrificial layer through the slit openings. In some embodiments, the stack sacrificial layer can be removed by applying an etchant through the slit openings, thereby generating lateral recesses, each of which is staggered between the stack dielectric layers. The etchant may include any suitable etchant that selectively etches the stack sacrificial layer relative to the stack dielectric layer.

[0093] Subsequently, the stacked conductive layer 414 (which may include a gate electrode and an adhesion layer) may be deposited into the lateral recess through the slit opening. In some embodiments, a gate dielectric layer may be deposited into the lateral recess before the stacked conductive layer 414, so that the stacked conductive layer 414 may be deposited on the gate dielectric layer. The stacked conductive layer 414, such as a metal layer (e.g., including tungsten), may be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, a gate dielectric layer (e.g., a high-k dielectric layer) may be formed along the sidewalls and also at the bottom of the slit opening. Accordingly, as Figure 4A As shown, according to some embodiments, a memory stack 418 is formed including alternating stacked conductive layers 414 and stacked dielectric layers 416 , thereby replacing the stack structure.

[0094] In some embodiments, as Figure 4AAs shown, the first semiconductor structure 304 of the 3D memory device 400 may include a filler layer 430 located above the memory stack 418. In some embodiments, the filler layer 430 may include a dielectric material and may be part of the memory stack 418, for example, one of the stack dielectric layers 416 that is closer to / closest to the carrier substrate 302. In some embodiments, one of the stack dielectric layers 416 that serves as the filler layer 430 may have a greater thickness than the other stack dielectric layers. Alternatively, the filler layer 430 may be additionally formed on the carrier substrate 302 before forming the memory stack 418. In some embodiments, the filler layer 430 may include one or more pad oxide layers (e.g., silicon oxide layers) located between the memory stack 418 and the carrier substrate 302 to mitigate stress between the different layers and prevent delamination. In some embodiments, the filler layer 430 may be formed using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0095] In some embodiments, based on the gap opening, a gap structure 432 may be formed that vertically extends through the memory stack 418 (which may include the filler layer 430) into the carrier substrate 302. In some embodiments, as Figure 4A As shown, the slot structure 432 may include a slot core 434 (i.e., a conductive layer) located within an insulating layer 436, with the slot core 434 extending along the y-direction. That is, the insulating layer 436 may surround the slot core 434 at its periphery. In other embodiments, the slot structure 432 may be formed by completely filling the slot opening with one or more conductive materials (e.g., polysilicon and / or tungsten). In still other embodiments, the slot structure 432 may be formed by completely filling the slot opening with one or more dielectric materials.

[0096] In some embodiments, to form the insulating layer 436 of the slot structure 432, one or more dielectric materials may be deposited into the slot opening using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to partially fill the sidewalls of the slot opening. In some examples, the dielectric material may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. Subsequently, a conductive material may be used to fill the remaining space of the slot opening of the slot structure 432 to form a slot core 434 of the slot structure 432. In some embodiments, the insulating layer 436 may surround the periphery of the slot core 434. In some examples, the conductive material used to form the slot core 434 may include one or more of polysilicon, silicide, germanium, silicon germanium, copper, aluminum, cobalt, and tungsten. By adjusting the amount of the conductive material(s) filled in the slot opening, the slot structure 432 may be formed with or without an air gap. In some embodiments, a glue layer may be formed between the gap core 434 and the insulating layer 436 to enhance adhesion between the gap core 434 and the insulating layer 436. In some embodiments, each gap structure 432 may extend laterally, thereby separating the plurality of channel structures 412 into a plurality of memory blocks. In other words, the memory stack 418 may be divided into a plurality of memory blocks by the gap structures 432, so that the array of channel structures 412 can be separated into memory blocks.

[0097] In some embodiments, the second semiconductor structure 306 bonded to the first semiconductor structure 304 can include semiconductor circuitry fabricated using CMOS. In some embodiments, the semiconductor circuitry can include peripheral circuitry 428 configured to control and sense the 3D memory device 400. The peripheral circuitry 428 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the 3D memory device 400, including, but not limited to, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., wordline drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry 428 can include transistors formed on the substrate 310, wherein all or a portion of the transistors can be formed in the substrate 310 (e.g., below the top surface of the substrate 310) and / or directly on the substrate 310. In some examples, the substrate 310 can be a silicon substrate.

[0098] In some examples, multiple transistors can be formed on substrate 310 using a variety of processes, including but not limited to: photolithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions (not shown) are formed in substrate 310 by ion implantation and / or thermal diffusion, which doped regions, for example, function as source regions and / or drain regions of the transistors. In some embodiments, isolation regions can also be formed in substrate 310 by wet etching and / or dry etching and thin film deposition. As a result, transistors can form peripheral circuitry 428 on substrate 310. According to some embodiments, the transistors are high-speed transistors using advanced logic processes (e.g., technology nodes of 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0099] although Figure 4A Details of the peripheral circuit 428 are not shown, but it is apparent that in some embodiments, the peripheral circuit 428 may also include any other circuit compatible with advanced logic processes, including logic circuits (such as processors and programmable logic devices (PLDs)), or memory circuits (such as static random access memory (SRAM) and dynamic RAM (DRAM)).

[0100] Similarly, in some embodiments, the second semiconductor structure 306 of the 3D memory device 400 may further include an interconnect layer (not shown) located above the peripheral circuitry 428 to transmit electrical signals to and from the peripheral circuitry 428. The interconnect layer may include a plurality of interconnects (also referred to herein as contacts), including lateral interconnect lines and vertical interconnect via (VIA) contacts. As used herein, the term "interconnect" may broadly include any appropriate type of interconnect, such as MEOL interconnects and BEOL interconnects. The interconnect layer may further include one or more interlayer dielectric (ILD) layers (also known as intermetallic dielectric (IMD) layers) in which the interconnect lines and VIA contacts may be formed. That is, the interconnect layer may include interconnect lines and VIA contacts located in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials, including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof.

[0101] In some embodiments, the first semiconductor structure 304 may further include one or more peripheral contacts 438, each peripheral contact 438 extending vertically outside the memory core region. In some embodiments, the first semiconductor structure 304 may include a filler structure 431 located in a peripheral region outside the memory core region, the memory stack 418 is located in the memory core region, and the filler structure 431 may include one or more dielectric materials. In some embodiments, each peripheral contact 438 may have a depth greater than the depth of the filler structure 431, thereby extending vertically from the first bonding layer 404 of the first semiconductor structure 304 to the carrier substrate 302 located in the peripheral region or extending in front of the carrier substrate 302. In some embodiments, as Figure 4A As shown, unlike the channel structure 412 and the slit structure 432 that extend further into the carrier substrate 302 , the peripheral contact 438 may stop at the filling structure 431 and may not extend vertically into the carrier substrate 302 .

[0102] Each peripheral contact 438 can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by a glue layer (e.g., a TiN layer). In some embodiments, the peripheral contact 438 can be configured to be electrically coupled to the second semiconductor structure 306. For example, the peripheral contact 438 can be configured to connect to an interconnect layer of the second semiconductor structure 306 and electrically couple to the peripheral circuit 428 located in the second semiconductor structure 306.

[0103] After the first semiconductor structure 304 having the semiconductor memory structure is bonded to the second semiconductor structure 306 having the peripheral circuit, the method 200 may proceed to Figure 2A At operation 208, the carrier substrate 302 and a portion of the storage film 424 may be removed in sequence to expose a portion of the semiconductor channel 422. Figure 4B As shown, the memory device 400 can be accessed from the back side (ie, Figure 4B The carrier substrate 302 can be completely removed by etching (top side in the image). In some embodiments, the carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some embodiments, the carrier substrate 302 can be stripped away. In some embodiments where the carrier substrate 302 may include silicon, the carrier substrate 302 can be removed using silicon CMP. In some embodiments, the carrier substrate 302 (silicon substrate) can be removed using wet etching using tetramethylammonium hydroxide (TMAH).

[0104] During / after removal of the carrier substrate 302, a portion of the memory film 424, including the storage layer, barrier layer, and tunneling layer, facing and proximate the carrier substrate 302 can be removed to expose a portion of the semiconductor channel 422 extending beyond the top of the memory stack 418. In some embodiments, the carrier substrate 302 and the portion of the memory film 424 can be removed by applying an etchant to the carrier substrate 302. The etchant can include any suitable etchant that selectively etches the carrier substrate 302 relative to the channel structure 412 (e.g., the semiconductor channel 422). In some embodiments, etching operations can also be performed to remove portions of the memory film 424 of the channel structure 412. For example, the memory film 424 of the channel structure 412 can be etched, stopping at the memory stack 418. In some examples, the channel structure 412 can extend beyond the memory film 424 by, for example, approximately 10 nm. That is, after operation 208, the semiconductor channel 422 can extend vertically beyond the memory film 424.

[0105] At operation 208, in some embodiments, a plurality of wet etching processes may be performed sequentially. For example, a storage layer comprising silicon nitride may be selectively removed using wet etching with an appropriate etchant (e.g., phosphoric acid). Then, a barrier layer and a tunneling layer comprising silicon oxide may be selectively removed using wet etching with an appropriate etchant (e.g., hydrofluoric acid) without etching the semiconductor channel 422 comprising polysilicon. The etching of the storage layer, barrier layer, and tunneling layer may be controlled by adjusting the etching time and / or etching rate and the etchant so that the etching does not proceed beyond the desired etching depth. That is, according to some embodiments, the etching of the storage film 424 may be controlled so that the upper end of the semiconductor channel 422 may exceed the upper end of the storage film 424. In other words, the semiconductor channel 422 may extend further beyond the memory stack 418 than the storage film 424. For example, as Figure 4B As shown, the memory film 424 may terminate at a top surface of the memory stack 418 (eg, at a fill layer 430 of the memory stack 418 ), while the semiconductor channel 422 may extend above the top surface of the memory stack 418 .

[0106] In this disclosure, the terms “exceed” or “extend beyond” are used interchangeably to describe that the upper end of the storage film 424 is located vertically below the upper end of the semiconductor channel 422 in the channel structure 412. Figure 4BAs shown, according to some embodiments, after removing a portion of the storage film 424, the upper end of the storage film 424 is not aligned with the upper end of the semiconductor channel 422 in the vertical direction. In some embodiments, the upper end of the storage film 424 can be flush with the memory stack 418 (i.e., the top surface of the memory stack 418 including the filling layer 430). That is, the vertical level of the storage film 424 can be substantially the same as the vertical level of the memory stack 418. In some embodiments, as Figure 4B As shown, the upper end of the memory film 424 may be located below the top surface of the memory stack 418 including the filling layer 430. In other words, the upper end of the memory film 424 may be flush with or lower than the top surface of the memory stack 418.

[0107] In some embodiments, as Figure 4B As shown, the top of the semiconductor channel 422 exceeding the memory film 424 may include a flat surface. That is, points on the top surface of the semiconductor channel 422 may be substantially at the same level in a horizontal direction. Figure 5A-5B 4 shows other configurations of semiconductor channels 422 according to some aspects of the present disclosure, each semiconductor channel 422 extending beyond the storage film in the channel structure. Figure 5A As shown, the top of the semiconductor channel 422 beyond the storage film 424 may include a tongue-shaped profile 423. The term "tongue-shaped" may refer to a configuration in which the semiconductor channel 422 has a tongue-shaped feature that protrudes from the edge of the top of the semiconductor channel 422 and may have the most protruding portion approximately at the top center. In other embodiments, such as Figure 5B As shown, the top of the semiconductor channel 422 extending beyond the storage film 424 may include a concave profile 425. In contrast to a tongue-shaped profile, the term "concave" may refer to a configuration in which the semiconductor channel 422 extends outwardly to create a raised portion at the edge of the top of the semiconductor channel and may have a lowest portion approximately at the center of the top. In some embodiments, a portion of the semiconductor channel 422 at an appropriate location on the top of the semiconductor channel 422 may be removed to form a Figure 5A The tongue-shaped profile 423 and Figure 5B Concave contour in.

[0108] exist Figure 2ADuring operation 208 in step 208 , in some embodiments, a portion of the insulating layer 436 of the slot structure 432 (which, in one example, may also include a glue layer of the slot structure 432 ) may also be removed to expose a slot core 434 of the slot structure 432 beyond the memory stack 418 . In some embodiments, the portion of the insulating layer 436 may be removed by applying an etchant. The etchant may include any suitable etchant that selectively etches the insulating layer 436 relative to the slot core 434 . For example, the insulating layer 436 of the slot structure 432 may be etched, stopping at the memory stack 418 . In some embodiments, the etching process(es) of the insulating layer 436 may be controlled such that an upper end of the slot core 434 is located above an upper end of the insulating layer 436 . In other words, the slot core 434 may extend further beyond the memory stack 418 than the insulating layer 436 . For example, the insulating layer 436 may terminate substantially at the top surface of the memory stack 418 , while the slot core 434 may extend above the top surface of the memory stack 418 .

[0109] More specifically, according to some embodiments, during the manufacturing process, after removing portions of the insulating layer 436, the upper end of the insulating layer 436 of the slot structure 432 is not aligned with the upper end of the slot core 434 in the vertical direction. Figure 4B As shown, the upper end of the insulating layer 436 is located below the upper end of the slot core 434 in the slot structure 432. In some embodiments, the upper end of the insulating layer 436 can be flush with the memory stack 418. That is, the vertical level of the insulating layer 436 can be approximately the same as the vertical level of the memory stack 418. In some examples, the upper end of the insulating layer 436 can be located above the top surface of the memory stack 418. That is, the upper end of the insulating layer 436 can be flush with or exceed the top surface of the memory stack 418.

[0110] exist Figure 2ADuring operation 208 in , the top end of the peripheral contact 438 may also be exposed. In some embodiments, after or during the removal of the carrier substrate 302, a portion of the filling structure 431 in the first semiconductor structure 304 may be removed by applying an etchant. The etchant may include any suitable etchant that selectively etches the filling structure 431 relative to the peripheral contact 438, and the etching time may be controlled. In some embodiments, after the portion of the filling structure 431 is removed, the top end of the peripheral contact 438 may extend beyond the remaining filling structure 431. In some embodiments, the removal of the filling structure 431, the removal of the insulating layer 436 of the gap structure 432, and the removal of the storage film 424 of the channel structure 412 may be performed simultaneously, while in other embodiments, they may be performed in a different order, and the present disclosure is not limited thereto.

[0111] Back to Figure 2A , method 200 may proceed to operation 210, where a surface treatment (e.g., an activation process) may be performed on the exposed surface of the first semiconductor structure 304 (e.g., the exposed portion of the semiconductor channel 422). In some embodiments, heat may be applied to a limited depth / region on the exposed surface of the first semiconductor structure 304. In some embodiments, the heat may be transferred to a lower location of the first semiconductor structure 304, and the limited depth / region may be located vertically between the memory stack 418 and the top surface of the first semiconductor structure 304. In some examples, the limited depth / region does not extend beyond the bonding interface 308 to avoid heating the bonding interface 308 and the copper interconnect used to connect the first semiconductor structure 304 to the second semiconductor structure 306. In some embodiments, the heat may be applied and focused by a laser, and may include laser activation.

[0112] In some embodiments, the activation process(es) may facilitate the subsequent formation of an adhesion layer. In some embodiments, the activation process(es) may also enhance hole carriers induced by gate induced drain leakage (GIDL) at the bottom select gate (BSG) and the top select gate (TSG) during a subsequent erase operation. In some embodiments, the memory device 400 may utilize GIDL current for efficient erase operations. That is, according to some embodiments, the memory device 400 may be configured to generate a GIDL auxiliary body bias when performing an erase operation. It should be understood that one or more stacked conductive layers in the stacked conductive layer 414 close to the top of the semiconductor channel 422 (i.e., the source of the channel structure 412) may serve as (multiple) bottom select gate lines coupled to each BSG, and one or more stacked conductive layers in the stacked conductive layer away from the top of the semiconductor channel 422 may be (multiple) top select gate lines. The remaining stacked conductive layers in the stacked conductive layer 414 may serve as word lines.

[0113] Back to Figure 2A , the method 200 may proceed to operation 212, where an adhesion layer 440 (eg, Figure 4C In some embodiments, an adhesion layer 440 may be formed over or on the memory stack 418 (e.g., the memory stack 418 that may include the fill layer 430). In some embodiments, the adhesion layer 440 may include a Ti / TiN layer, a Ta / TaN layer, a composite layer having a metal material (e.g., tungsten), or the like. In some embodiments, the thickness of the adhesion layer 440 may be between about 1000Å and about 2000Å. With The adhesion layer 440 may be arranged to enhance adhesion between the first semiconductor structure 304 and a conductor layer formed thereafter.

[0114] In some embodiments, an adhesion layer 440 may be formed to cover the exposed portion of the semiconductor channel 422. For example, the adhesion layer 440 may be formed on the exposed surface of the semiconductor channel 422, including the top surface and sidewalls (eg, Figure 4C ), thereby increasing the contact area. Thus, the adhesive layer 440 can also contact the exposed top end of the storage film 424 surrounding the semiconductor channel 422. In some embodiments, the first semiconductor structure 304 of the 3D memory device 400 can include an adhesive layer 440, which can electrically connect the plurality of channel structures 412. As a result, the adhesive layer 440 can provide electrical connections between the sources of an array of NAND memory strings located in the same block, that is, provide an array common source (ACS).

[0115] In some embodiments, an adhesive layer 440 may be formed to cover the exposed portion of the slot core 434 of the slot structure 432. For example, the adhesive layer 440 may be formed on the exposed slot core 434 of the slot structure 432, including the top surface and sidewalls (e.g., Figure 4C At the same time, the adhesive layer 440 can also contact the exposed top of the insulating layer 436 surrounding the gap core 434.

[0116] In some embodiments, an adhesive layer 440 may also be formed to cover the peripheral contacts 438. In some embodiments, such as Figure 4C As shown, the adhesive layer 440 may be formed to cover the sidewalls of the peripheral contacts 438, and the top ends of the peripheral contacts 438 may extend beyond the filling structure 431. In some embodiments, the adhesive layer 440 may be formed to cover the top ends and sidewalls of the peripheral contacts 438. While the adhesive layer 440 and the peripheral contacts 438 may be electrically connected, the present disclosure is not limited thereto.

[0117] During the manufacturing process, to form adhesion layer 440, one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) may be used to deposit a semiconductor layer or a metal layer to contact the exposed portion of semiconductor channel 422 and the outer region of semiconductor channel 422. In some embodiments, adhesion layer 440 may be configured to block material diffusion (e.g., silicon / aluminum diffusion between memory stack 418 and a conductor layer formed thereafter).

[0118] Back to Figure 2A , the method 200 may proceed to operation 214, where a conductor layer 442 (eg, Figure 4D ). In some embodiments, one or more conductive materials may be deposited on adhesion layer 440 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to cover adhesion layer 440. In some embodiments, the one or more conductive materials may include Al, W, or a combination thereof. In some embodiments, a planarization process (e.g., CMP) may then be performed to remove excess portions of conductor layer 442. In some embodiments, conductor layer 442 may serve as part of a pad structure and a backside common source structure.

[0119] Method 200 may proceed to operation 216. At operation 216, one or more isolation structures may be formed. In some embodiments, one or more first trenches and one or more second trenches may be formed. The one or more first trenches may be part of a first isolation structure 444, and the one or more second trenches may be part of a second isolation structure 446. In some embodiments, one or more first trenches may be formed in a peripheral region of the memory device 400 using wet etching and / or dry etching (e.g., RIE) to expose the fill structure 431 located below the adhesion layer 440, each first trench extending through the conductor layer 442 and the adhesion layer 440. In some examples, the one or more first trenches may be arranged between two peripheral contacts 438 to electrically insulate the two peripheral contacts 438. In some embodiments, as Figure 4E As shown, one or more first trenches can be patterned using photolithography to align them between two peripheral contacts 438. The etching of the one or more first trenches can be configured to completely remove the adhesion layer 440 to expose the fill structure 431 below. In some embodiments, the portion of the fill structure 431 located below the adhesion layer 440 can also be removed. Subsequently, a first spacer can be deposited into the one or more first trenches. In some examples, the first spacer can include a first dielectric material. The first spacer can form a first isolation structure 444 to electrically isolate adjacent peripheral contacts 438 located in the peripheral region of the memory device 400.

[0120] In some embodiments, one or more second trenches may be formed in appropriate locations using wet etching and / or dry etching (eg, RIE), with each second trench extending through the conductor layer 442. Figure 4E As shown, one or more second trenches can be patterned using photolithography to align with the top of the gap structure 432. In some examples, the etching of the one or more second trenches can be stopped at the adhesion layer 440 located on the top of the gap core 434 to expose the adhesion layer 440 below. Subsequently, a second spacer can be deposited into the one or more second trenches and can become part of the second isolation structure 446. In some examples, the second spacer can include a second dielectric material. The second dielectric material can be the same as or different from the first dielectric material. The second isolation structure 446 can include a second spacer. In some embodiments, the second isolation structure can be arranged to relieve stress caused by the adhesion layer 440.

[0121] In some embodiments, one or more pins 448 may be formed in the memory device 400. In some examples, such as Figure 4EAs shown, one or more openings are formed by removing a portion of conductor layer 442 using wet etching and / or dry etching. Subsequently, a conductive material may be deposited into the one or more openings to form one or more pins 448. At least one of pins 448 may be used to connect to a memory controller coupled to a host in a memory system including memory device 400.

[0122] Figure 2B A flow chart of another exemplary method for forming a 3D memory device according to some aspects of the present disclosure is shown. In the present disclosure, the removal operation of a portion of the carrier substrate 302 and the storage film 424 can be controlled to ensure that the removal can be completed at an appropriate depth in the vertical direction. As described above, the removal conditions (such as the removal rate and time, and the removal method applied) can be adjusted to ensure that the desired depth has been reached. In some embodiments, a stop layer located between the carrier substrate 302 and the memory stack 418 can be arranged for similar purposes. The removal operation (s) can be stopped by the stop layer to minimize the groove variation among the removal operations of the storage film 424 of each channel structure 412.

[0123] As mentioned above, in Figure 2A When forming the first semiconductor structure 304 at operation 202 in the embodiment, a stacked structure including an alternating first dielectric layer (i.e., a sacrificial layer) and a second dielectric layer (i.e., a dielectric layer in a memory stack 418 in a subsequent operation) can be formed on the carrier substrate 302. In some embodiments, forming the first semiconductor structure 304 can include: Figure 2B A stop layer is formed at operation 202A in the process. Figures 6A-6E 1 shows a corresponding manufacturing process for forming an exemplary 3D memory device 600 with a stop layer according to some aspects of the present disclosure. It will be appreciated that for ease of illustration, Figure 2B Only part of the manufacturing process is shown. Figure 2B The rest of the Figure 2A The operations shown in are similar or identical.

[0124] exist Figure 2B At operation 202A in FIG. 2 , in some embodiments, before forming a stack structure including alternating sacrificial layers and dielectric layers, a stop layer 602 can be formed over the carrier substrate 302. In some embodiments, the stop layer 602 can be disposed between the carrier substrate 302 and the stack structure formed thereafter. In the present disclosure, the stop layer 602 can be considered as part of the memory stack 418 formed after gate replacement, while it is understood that in some embodiments, the stop layer 602 can extend laterally to the peripheral region.

[0125] In some examples, stop layer 602 may include polysilicon and may be a polysilicon layer, and therefore, in the present disclosure, stop layer 602 may be referred to as a top polysilicon layer. In some embodiments, in addition to serving as an etch stop layer, polysilicon layer 602 may also be used as an interconnect layer for connecting a gate located in the core region with a gate located in the peripheral region. When the stop layer is a conductive layer, the stop layer may be referred to as a "first conductive layer" in the present disclosure.

[0126] In some embodiments, before forming the stacked structure, a polysilicon layer 602 can be formed over the carrier substrate 302 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Subsequently, alternating sacrificial layers and dielectric layers can be formed over the polysilicon layer 602.

[0127] Figure 2B The manufacturing processes and operations not shown in FIG can be compared with those in FIG. Figure 2A The manufacturing process and operation are the same or similar, wherein a channel structure 412, a memory stack 418 replacing the stack structure, a gap structure 432, and one or more peripheral contacts 438 can be formed. In some embodiments, any suitable semiconductor components can be additionally formed in the first semiconductor structure 304. The present disclosure is not limited in this regard. In some embodiments, a second semiconductor structure 306 having a semiconductor circuit (e.g., a peripheral circuit) can be formed. Subsequently, the first semiconductor structure 304 and the second semiconductor structure 306 can be used as described above with respect to Figure 2A The bonding may be performed using the same or similar techniques as described for operation 206 in FIG.

[0128] Back to Figure 2B , method 201 may proceed to operation 208A. In some examples, Figure 2B Operation 208A in Figure 2A The operation 208 in is similar. Figure 2B At operation 208A in , when removing the storage film 424 of the channel structure 412 and the insulating layer 436 of the gap structure 432 to control the desired remaining depth, the polysilicon layer 602 can be applied as (for example) an etch stop layer instead of controlling the etching conditions (such as the etching rate and time, and the applied etchant) to ensure that the desired depth has been reached.

[0129] At operation 208A, the carrier substrate 302 and a portion of the storage film 424 may be removed in sequence to expose a portion of the semiconductor channel 422. Figure 6B As shown, the carrier substrate 302 may be completely removed from the back side of the memory device 600 (ie, Figure 6BWhen / after removing the carrier substrate 302, a portion of the memory film 424, including the storage layer, the barrier layer, and the tunneling layer, that faces toward and is proximate to the carrier substrate 302 can be removed, stopping at the polysilicon layer 602 to expose a top portion of the semiconductor channel 422 that extends beyond the memory stack 418. In some examples, the semiconductor channel 422 can exceed / extend beyond the memory film 424, for example, by approximately 10 nm.

[0130] After removing part of the storage film 424, the semiconductor channel 422 can be constructed similarly to Figure 4B In some examples, the upper end of the storage film 424 is located below the upper end of the semiconductor channel 422 in the channel structure 412. In some examples, the semiconductor channel 422 beyond the storage film 424 may have a Figure 5A or Figure 5B The same or similar profiles as shown in .

[0131] Similarly, a portion of the insulating layer 436 of the slot structure 432 may also be removed, stopping at the polysilicon layer 602 to expose the slot core 434 of the slot structure 432. In some embodiments, the slot core 434 may extend further beyond the polysilicon layer 602 than the insulating layer 436. For example, Figure 6B As shown, the insulating layer 436 may terminate approximately at the top surface of the polysilicon layer 602 , while the slot core 434 may extend above the top surface of the polysilicon layer 602 .

[0132] exist Figure 2B At operation 208A in FIG. 2 , after removing the carrier substrate 302 (and in some examples, a portion of the filling structure 431 may also be removed), the top of the peripheral contact 438 may be exposed and extend beyond the polysilicon layer 602. In some embodiments, the removal of the filling structure 431, the removal of the insulating layer 436 of the gap structure 432, and the removal of the storage film 424 of the channel structure 412 may be performed simultaneously, while in other embodiments, they may be performed in a different order.

[0133] Figure 2B Subsequent operations in Figure 2A For example, according to Figure 2A In operation 210, a surface treatment may be performed on the exposed surface (including the exposed semiconductor channel) of the first semiconductor structure 304. In an embodiment, the surface treatment may include laser activation. These operations may also be applied to the first semiconductor structure 304 having the polysilicon layer 602.

[0134] Similarly, according to Figure 2A Operation 212 in, such as Figure 6C As shown, an adhesion layer 604 can be formed in contact with the exposed portion of the semiconductor channel 422. In some embodiments, the adhesion layer 604 can be formed in contact with the polysilicon layer 602. In some embodiments, the adhesion layer 604 can include a Ti / TiN layer, a Ta / TaN layer, a composite layer having a metal material (e.g., tungsten), etc. In some embodiments, the adhesion layer 604 can be formed to cover the exposed portion of the semiconductor channel 422. For example, the adhesion layer 604 can be formed on the exposed surface of the semiconductor channel 422, including the top surface and sidewalls (e.g., the bottom surface) of the semiconductor channel 422. Figure 6C as shown), thereby increasing the contact area.

[0135] In some embodiments, the first semiconductor structure 304 of the 3D memory device 600 may include an adhesive layer 604 that may electrically connect the plurality of channel structures 412. For example, the adhesive layer 604 may provide electrical connections between sources of an array of NAND memory strings located in the same block, i.e., provide an array common source (ACS). In some embodiments, the adhesive layer 604 may be formed to cover the gap core 434 of the gap structure 432. For example, the adhesive layer 604 may be formed on the exposed gap core 434 of the gap structure 432, including the top surface and sidewalls (e.g., the gap core 434). Figure 6C In some embodiments, an adhesive layer 604 may be formed to cover the peripheral contacts 438. In some embodiments, as shown Figure 6C As shown, the adhesive layer 604 may be formed to cover the sidewalls of the peripheral contacts 438 , and the top ends of the peripheral contacts 438 may extend beyond the adhesive layer 604 .

[0136] Then, according to operation 214, Figure 6D As shown, a conductor layer 442 can be formed in contact with the adhesion layer 604. In some embodiments, one or more conductive materials can be deposited on the adhesion layer 604 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to cover the adhesion layer 604. In some embodiments, the one or more conductive materials can include Al, W, or a combination thereof. In some embodiments, a planarization process (e.g., CMP) can then be performed to remove excess portions of the conductor layer 442. In some embodiments, the conductor layer 442 can serve as part of a pad structure as well as a backside common source structure. Subsequently, as Figure 6EAs shown, one or more isolation structures may be formed by removing a portion of the conductive layer 442 (and may include one or more other layers). One or more first trenches may be formed in a peripheral region of the memory device 600, each first trench extending through the conductive layer 442 and the adhesive layer 604. In some embodiments, as shown Figure 6E As shown, one or more first trenches may penetrate the polysilicon layer 602 and become part of the first isolation structure 444. For further details, see Figures 4A-4E The corresponding description.

[0137] according to Figure 2B , a stop layer may be arranged above the carrier substrate 302 and act as, for example, an etch stop layer to ensure that removal can be completed at an appropriate depth in the vertical direction. In some embodiments, the first semiconductor structure 304 may include Figure 2B The stop layer at operation 202A in FIG. Figures 7A-7E Another fabrication process for forming an exemplary 3D memory device 700 with a stop layer according to some aspects of the present disclosure is shown.

[0138] exist Figure 2B At operation 202A in FIG. 3 , in some embodiments, a stop layer 701 can be formed over the carrier substrate 302. In some examples, a memory stack 418 formed thereafter can include the stop layer 701. As described above, when forming the first semiconductor structure 304, a stack structure including multiple pairs of sacrificial layers and dielectric layers can be formed on the carrier substrate 302. Subsequently, a slit opening can be formed that extends vertically through the stack structure. Through the slit opening, a gate replacement can then be performed through the slit opening to replace the stack structure with a memory stack 418 that includes a stack conductive layer 414 and a stack dielectric layer 416. According to Figure 2B In operation 202A, in some embodiments, the stopping layer 701 may be one of the conductive layers 414 of the memory stack 418 that is closer to / closest to the carrier substrate 302 .

[0139] Figure 2B The manufacturing processes and operations not shown in FIG can be compared with those in FIG. Figure 2AThe manufacturing process and operations are the same or similar, wherein a channel structure 412, a gap structure 432, and one or more peripheral contacts 438 can be formed. In some embodiments, any suitable semiconductor components can be additionally formed in the first semiconductor structure 304. The present disclosure is not limited in this regard. In some embodiments, a second semiconductor structure 306 having a semiconductor circuit (e.g., a peripheral circuit) can be formed. Subsequently, the first semiconductor structure 304 and the second semiconductor structure 306 can be bonded using the same or similar techniques as described above with respect to operation 206.

[0140] Back to Figure 2B , method 201 may proceed to operation 208A. In some examples, Figure 2B Operation 208A in Figure 2A The operation 208 in is similar. Figure 2B At operation 208A in , when removing the storage film 424 of the channel structure 412 and the insulating layer 436 of the gap structure 432 to control the desired depth, a stop layer 701 (or the conductive layer 414 of the memory stack 418 that is closer / closest to the carrier substrate 302) can be applied as (for example) an etch stop layer instead of controlling the etching conditions (such as the etching rate and time, and the applied etchant) to ensure that the desired depth has been reached.

[0141] At operation 208A, the carrier substrate 302 and a portion of the storage film 424 may be removed in sequence to expose a portion of the semiconductor channel 422. Figure 7B As shown, the back side (ie, Figure 7B The carrier substrate 302 is completely removed (at the top side in FIG). While or after removing the carrier substrate 302, a portion of the storage film 424, including the storage layer, the barrier layer, and the tunneling layer, that faces toward and is proximate to the carrier substrate 302 can be removed, stopping at the stop layer 701 to expose a portion of the semiconductor channel 422 that extends beyond the top of the memory stack 418. In some examples, the semiconductor channel 422 can extend beyond the storage film 424 by, for example, approximately 10 nm.

[0142] After removing part of the storage film 424, the structure of the semiconductor channel 422 can be similar to Figure 4B In some examples, the upper end of the storage film 424 is located below the upper end of the semiconductor channel 422 in the channel structure 412. In some examples, the semiconductor channel 422 beyond the storage film 424 may have a Figure 5A or Figure 5B The same or similar profiles as shown in .

[0143] Similarly, a portion of the insulating layer 436 of the slot structure 432 may also be removed, stopping at the stop layer 701, to expose the slot core 434 of the slot structure 432. In some embodiments, the slot core 434 may extend further beyond the stop layer 701 than the insulating layer 436. For example, Figure 7B As shown, the insulating layer 436 may terminate substantially at the top surface of the stopping layer 701 , while the slot core 434 may extend above the top surface of the stopping layer 701 .

[0144] According to some embodiments, Figure 2B At operation 208A in FIG, after removing the carrier substrate 302, the top end of the peripheral contact 438 may be exposed and exceed the stop layer 701. In some embodiments, the removal of the insulating layer 436 of the gap structure 432 and the removal of the storage film 424 of the channel structure 412 may be performed simultaneously, while in other embodiments, they may be performed in a different order.

[0145] Figure 2B Subsequent operations in Figure 2A For example, according to Figure 2A In operation 210, a surface treatment may be performed on the exposed surface of the first semiconductor structure 304 (including the exposed semiconductor channel). In an embodiment, the surface treatment may include laser activation. These operations may also be applied to the first semiconductor structure 304 having the stop layer 701.

[0146] Similarly, according to Figure 2A Operation 212 in, such as Figure 7C As shown, an adhesion layer 702 can be formed in contact with the exposed portion of the semiconductor channel 422. In some embodiments, the adhesion layer 702 can be formed in contact with the stop layer 701. As a result, the conductive layer 414 acting as the stop layer 701 is the conductive layer of the memory stack 418 that is closer to / closest to the adhesion layer 702. In some embodiments, the adhesion layer 702 can include a Ti / TiN layer, a Ta / TaN layer, a composite layer having a metal material (e.g., tungsten), etc. In some embodiments, the adhesion layer 702 can be formed to cover the exposed portion of the semiconductor channel 422. For example, the adhesion layer 702 can be formed on the exposed surface of the semiconductor channel 422, including the top surface and sidewalls (e.g., the top surface) of the semiconductor channel 422. Figure 7C as shown), thereby increasing the contact area.

[0147] In some embodiments, the first semiconductor structure 304 of the 3D memory device 700 may include an adhesive layer 702 that may electrically connect the plurality of channel structures 412. For example, the adhesive layer 702 may provide electrical connections between sources of an array of NAND memory strings located in the same block, i.e., provide an array common source (ACS). In some embodiments, the adhesive layer 702 may be formed to cover the gap core 434 of the gap structure 432. For example, the adhesive layer 702 may be formed on the exposed gap core of the gap structure 432, including the top surface and sidewalls (e.g., the gap core 434). Figure 7C In some embodiments, an adhesive layer 702 may be formed to cover the peripheral contacts 438. In some embodiments, as shown Figure 6C As shown, the adhesive layer 702 may be formed to cover the sidewalls of the peripheral contacts 438 , and the top ends of the peripheral contacts 438 may extend beyond the adhesive layer 702 .

[0148] Then, according to operation 214, Figure 7D As shown, a conductor layer 442 can be formed in contact with the adhesion layer 702. In some embodiments, one or more conductive materials can be deposited on the adhesion layer 702 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to cover the adhesion layer 702. In some embodiments, the one or more conductive materials can include Al, W, or a combination thereof. In some embodiments, a planarization process (e.g., CMP) can then be performed to remove excess portions of the conductor layer 442. In some embodiments, the conductor layer 442 can serve as part of a pad structure as well as a backside common source structure. Subsequently, as Figure 7E As shown, one or more isolation structures can be formed by removing a portion of the conductor layer 442 (and can include one or more other layers). For example, a portion of the conductor layer 442 and a portion of the adhesive layer 702 can be removed to expose the filling structure 431 below, thereby forming one or more first trenches, and a first spacer can be filled into the one or more first trenches to form a first isolation structure. In some embodiments, a portion of the filling structure 431 can also be removed. For further details, see the Figures 4A-4E The corresponding description.

[0149] Figure 8A block diagram of an exemplary system 800 having a 3D memory device 804 according to some aspects of the present disclosure is shown. The system 800 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 8 As shown, system 800 may include a host 808 and a memory system 802 having one or more 3D memory devices 804 and a memory controller 806. Host 808 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device.

[0150] 3D memory device 804 can be any 3D memory device disclosed herein, such as 3D memory devices 300, 400, 600, and 700 shown in the corresponding figures. In some embodiments, each 3D memory device 804 includes a NAND flash memory. Consistent with the scope of the present disclosure, 3D memory devices 300, 400, 600, and 700 can include a channel structure having a storage film and a semiconductor channel, wherein the semiconductor channel extends beyond the storage film in a first direction. An adhesion layer can be disposed on and in contact with the semiconductor channel extending beyond the storage film, and can also be disposed on and in contact with the adhesion layer. Thus, backside pad isolation can be omitted. Furthermore, after removing a portion of the storage film, gate-induced drain leakage (GIDL) activation can be performed by a surface treatment process (e.g., laser activation) on the exposed surface. As a result, a conductive material can replace the bottom polysilicon layer and serve as a portion of the pad structure and the backside common source structure. In summary, the backside manufacturing process can be simplified and costs can also be reduced.

[0151] According to some embodiments, the memory controller 806 is coupled to the 3D memory device 804 and the host 808 and can be configured to control the 3D memory device 804. The memory controller 806 can manage data stored in the 3D memory device 804 and communicate with the host 808. In some embodiments, the memory controller 806 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 806 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 806 can be configured to control the operations of the 3D memory device 804 (e.g., read operations, erase operations, and program operations). The memory controller 806 may also be configured to manage various functions related to data stored or to be stored in the 3D memory device 804, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the memory controller 806 may also be configured to process error correction code (ECC) for data read from or written to the 3D memory device 804. The memory controller 806 may also be configured to perform any other appropriate functions, such as formatting the 3D memory device 804. The memory controller 806 may communicate with an external device (e.g., a host 808) according to a specific communication protocol. For example, the memory controller 806 may communicate with the external device using at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-Express) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer miniature interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0152] The memory controller 806 and one or more 3D memory devices 804 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage device (UFS) package or an eMMC package). That is, the memory system 802 can be implemented and packaged into different types of terminal electronic products. Figure 9AIn one example shown in FIG, the memory controller 806 and the single 3D memory device 804 may be integrated into a memory card 902. The memory card 902 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 902 may also include a memory card that connects the memory card 902 to a host (e.g., Figure 8 Host 808 in the memory card connector 904 electrically coupled. Figure 9B In another example shown in , the memory controller 806 and the plurality of 3D memory devices 804 may be integrated into an SSD 906. The SSD 906 may also include a processor that interfaces the SSD 906 with a host (e.g., Figure 8 In some embodiments, the storage capacity and / or operating speed of the SSD 906 is greater than the storage capacity and / or operating speed of the memory card 902.

[0153] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teaching and guidance provided herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0154] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device comprising: a stack comprising alternating conductive and dielectric layers; a channel structure extending through the stack in a first direction, the channel structure comprising a storage film and a semiconductor channel extending beyond the storage film in the first direction, the storage film surrounding the semiconductor channel; an adhesive layer disposed on the semiconductor channel beyond the memory film and in contact with the semiconductor channel beyond the memory film; as well as A conductor layer is provided on the adhesive layer and in contact with the adhesive layer.

2. The 3D memory device according to claim 1, wherein The adhesive layer contacts a sidewall of the semiconductor channel beyond the memory film.

3. The 3D memory device according to claim 1 , wherein: The adhesive layer is in contact with the stacked body at one side of the adhesive layer and is in contact with the conductor layer at the other side of the adhesive layer.

4. The 3D memory device according to claim 1 , wherein: The adhesion layer includes one of a Ti / TiN layer, a Ta / TaN layer, or a composite layer including a conductive material.

5. The 3D memory device according to claim 1, wherein The thickness of the adhesive layer is between about With between.

6. The 3D memory device according to claim 1 , further comprising: a plurality of peripheral contacts, each of the plurality of peripheral contacts extending in the first direction and in contact with the adhesive layer; as well as A first isolation structure extends through the conductor layer and the adhesive layer and in a second direction perpendicular to the first direction, the first isolation structure comprising a dielectric material.

7. The 3D memory device according to claim 6, wherein: The first isolation structure is disposed between two peripheral contacts of the plurality of peripheral contacts to electrically isolate the two peripheral contacts.

8. The 3D memory device according to claim 1 , further comprising: a gap structure extending through the stack in the first direction, wherein: The slot structure includes a slot core and an insulating layer surrounding the slot core, wherein the slot core includes a conductive material; and The slot core exceeds the insulating layer in the first direction and contacts the adhesive layer.

9. The 3D memory device according to claim 8, wherein The adhesive layer contacts sidewalls of the slot core that extend beyond the insulating layer.

10. The 3D memory device according to claim 8, wherein The insulating layer of the slit structure is substantially flush with a top surface of the stacked body.

11. The 3D memory device according to claim 8, further comprising: A second isolation structure extends through the conductor layer and stops at the adhesive layer on the slot structure, the second isolation structure comprising a dielectric material.

12. The 3D memory device according to claim 1, wherein The stack includes a first conductive layer in contact with a side of the adhesive layer opposite to the conductor layer.

13. The 3D memory device according to claim 12, wherein: The first conductive layer is a polysilicon layer.

14. The 3D memory device according to claim 12, wherein: The first conductive layer is one of the conductive layers of the stacked body that is closest to the adhesive layer.

15. The 3D memory device according to claim 14, wherein The first conductive layer includes tungsten.

16. The 3D memory device according to claim 12, wherein: The semiconductor channel exceeds the first conductive layer in the first direction, and the adhesive layer contacts at least a portion of the first conductive layer.

17. The 3D memory device according to claim 12, wherein: An upper end of the storage film is substantially flush with a top surface of the first conductive layer.

18. The 3D memory device according to claim 12, wherein An upper end of the storage film is lower than a top surface of the first conductive layer.

19. The 3D memory device of claim 12, further comprising: a gap structure extending through the stack in the first direction, wherein: The slot structure includes a slot core, the slot core including a conductive material; and The slot core exceeds the first conductive layer in the first direction and contacts the adhesive layer.

20. The 3D memory device according to claim 1, wherein The conductor layer includes at least one of aluminum or tungsten.

21. The 3D memory device of claim 1 , further comprising: A peripheral contact extends in the first direction and contacts the adhesive layer.

22. The 3D memory device according to claim 21, wherein The adhesive layer contacts sidewalls of the peripheral contacts.

23. The 3D memory device according to claim 21, wherein The stack comprises a first conductive layer in contact with the adhesive layer, wherein: The first conductive layer is a polysilicon layer; and The polysilicon layer extends in a third direction perpendicular to the first direction, and the peripheral contact and the channel structure penetrate the polysilicon layer.

24. A method for forming a three-dimensional (3D) memory device, comprising: forming a first semiconductor structure, the first semiconductor structure including a stack and a channel structure, the channel structure extending through the stack in a first direction and including a storage film and a semiconductor channel, the storage film surrounding the semiconductor channel; removing a portion of the storage film to expose a portion of the semiconductor channel; forming an adhesive layer disposed on and in contact with the exposed portion of the semiconductor channel exceeding the remaining portion of the memory film; as well as A conductor layer is formed, the conductor layer being disposed on the adhesive layer and in contact with the adhesive layer.

25. The method according to claim 24, wherein Forming the adhesive layer includes forming the adhesive layer in contact with a sidewall of the semiconductor channel that extends beyond the memory film.

26. The method according to claim 24, wherein Forming the first semiconductor structure further includes: forming a channel hole extending in the first direction through a stacked structure, a portion of which is replaced to form the stacked body; and The storage film and the semiconductor channel are formed along the sidewalls of the channel hole to form the channel structure, wherein the storage film includes a tunneling layer, a storage layer, and a barrier layer.

27. The method of claim 24, further comprising: removing a first portion of the conductor layer and a first portion of the adhesive layer to expose the stack and form a first trench extending in a second direction perpendicular to the first direction; as well as The first trench is filled with a dielectric material to form a first isolation structure.

28. The method of claim 24, wherein: Forming the first semiconductor structure further includes: forming a gap structure extending through the stack in the first direction, wherein the gap structure includes a gap core and an insulating layer surrounding the gap core, and the gap core includes a conductive material; The method further includes: removing a portion of the insulating layer at one end of the slot structure to form an exposed slot core exceeding the insulating layer in the first direction; and Forming the adhesive layer includes forming the adhesive layer in contact with the exposed slit core.

29. The method according to claim 28, wherein Forming the adhesive layer further includes forming the adhesive layer in contact with sidewalls of the exposed slot core that extend beyond the insulating layer.

30. The method of claim 28, further comprising: removing a second portion of the conductor layer to form a second trench, thereby exposing the adhesive layer on the slot core, the second trench extending in a second direction perpendicular to the first direction; as well as The second trench is filled with a dielectric material to form a second isolation structure.

31. The method of claim 24, wherein: Removing the portion of the storage film includes: The portion of the memory film surrounding one end of the semiconductor channel is removed, stopping at the stack.

32. The method of claim 24, wherein: Forming the first semiconductor structure further includes: forming a first conductive layer over the substrate; and The channel structure is formed to extend through the first conductive layer into the substrate.

33. The method according to claim 32, wherein Removing the portion of the storage film includes: The portion of the storage film is removed, stopping at the first conductive layer.

34. The method of claim 32, wherein: Forming the first conductive layer includes: forming a polysilicon layer over the substrate; and Forming the first semiconductor structure further includes: After forming the polysilicon layer, forming a stack structure including alternating sacrificial layers and dielectric layers; and The sacrificial layer of the stacked structure is replaced by a conductive layer to form the stacked body.

35. The method according to claim 34, wherein The polysilicon layer extends from a memory core region of the 3D memory device to a peripheral region of the 3D memory device in a second direction perpendicular to the first direction.

36. The method of claim 32, wherein: Forming the first semiconductor structure includes: forming a stacked structure including alternating sacrificial layers and dielectric layers; and Forming the first conductive layer includes: replacing one of the sacrificial layers closest to the substrate with a conductive layer, and the first conductive layer includes the conductive layer.

37. The method of claim 32, wherein: Forming the adhesive layer includes forming the adhesive layer in contact with at least a portion of the first conductive layer.

38. The method of claim 24, further comprising: Before forming the adhesion layer, a surface treatment is performed on the exposed portion of the semiconductor channel.

39. The method according to claim 38, wherein The surface treatment includes laser activation.

40. The method of claim 24, further comprising: forming a second semiconductor structure including peripheral circuits of the 3D memory device; as well as The first semiconductor structure is bonded to the second semiconductor structure.

41. The method of claim 40, wherein: Forming the first semiconductor structure further includes: forming a first bonding layer; Forming the second semiconductor structure further includes: forming a second bonding layer; and Bonding the first semiconductor structure to the second semiconductor structure includes bonding the first bonding layer of the first semiconductor structure to the second bonding layer of the second semiconductor structure.

42. The method according to claim 41, wherein The peripheral circuit of the second semiconductor structure is coupled to the stack of the first semiconductor structure through the first bonding layer and the second bonding layer.

43. A system comprising: A three-dimensional (3D) memory device configured to store data and comprising: A first semiconductor structure, comprising: a stack comprising alternating conductive and dielectric layers; a channel structure extending through the stack in a first direction, the channel structure comprising a storage film and a semiconductor channel extending beyond the storage film in the first direction, the storage film surrounding the semiconductor channel; an adhesive layer provided on the semiconductor channel beyond the memory film and in contact with the semiconductor channel beyond the memory film; and a conductor layer disposed on the adhesive layer and in contact with the adhesive layer; and a second semiconductor structure including peripheral circuits bonded to the first semiconductor structure; and a memory controller coupled to the 3D memory device and configured to control the 3D memory device.

44. The system of claim 43, further comprising a host coupled to the memory controller.

45. The system of claim 43, wherein: The memory controller is coupled to the 3D memory device through the conductor layer.

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