A high-precision wide-range current detection circuit
By using a high-precision, wide-range current detection circuit, combined with Auto-Zero dynamic zeroing technology and an additional feedback loop, the problems of high power loss and insufficient current detection accuracy in high-side switching current detection are solved, and accurate current detection is achieved in the range from large current to small current.
Patent Information
- Application Number
- CN202510936633.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-08
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2045-07-08
AI Technical Summary
Existing technologies for high-side switch current detection suffer from problems such as high power loss under high current loads, strict requirements for detection resistor accuracy and temperature stability, and difficulty in maintaining accurate current detection ratio when the load current is extremely low.
A high-precision, wide-range current detection circuit is employed, which combines an auxiliary operational amplifier A1, a power transistor MP, a sampling transistor MS, a PMOS transistor PM0, a resistor RS, an operational amplifier OP, a charge pump, a driver module DRIVER, and a high-voltage domain floating ground module HVSS_Gen. By utilizing Auto-Zero dynamic zeroing technology and an additional feedback loop, the input mismatch of the operational amplifier is reduced, and the overdrive voltage of the power transistor is adjusted when the load current is low to maintain an accurate current detection ratio.
It maintains accurate current sensing ratio across a load current range from high to low current, reduces op-amp input mismatch, minimizes power loss, and improves sensing accuracy.
Smart Images
Figure CN120722048B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a detection circuit, in particular a high-precision wide-range current detection circuit, and belongs to the technical field of semiconductor integrated circuits. BACKGROUND
[0002] In modern electronic systems, high-side switches have become indispensable circuit elements. The devices are not only widely used in automotive electronics as key load switches, but also can be integrated with protection functions for applications such as hot plug control and surge suppression. In particular, in load switch applications, to ensure that the system can monitor the load state in real time and accurately transmit the diagnostic information to the main control unit, the output current must be precisely detected, and accurate power regulation must be achieved.
[0003] The prior art mainly adopts two types of technical solutions to realize the current detection function of the high-side switch:
[0004] The first technical solution adopts a resistive detection architecture (as shown in FIG. 1). This solution obtains the current signal by connecting a detection resistor Rsense in series with the load loop, and transmits the detection voltage to the ROUT resistor by means of the virtual short feature of the operational amplifier, and then generates a sampling current proportional to the load current on the PMOS tube, whose value is (Rsense x ILoad) / R1. Finally, the current signal is converted into a measurable voltage signal Vout through the output resistor Rout. Figure 6
[0005] Although this detection architecture has the advantage of simple design, it has obvious limitations in engineering practice: on the one hand, when the system needs to handle large current loads, considerable power loss will occur on the detection resistor; on the other hand, this solution requires strict requirements for the resistance value accuracy and temperature stability of the detection resistor.
[0006] The second technical solution is based on the SenseFET technology (as shown in FIG. 2). This solution ingeniously utilizes the ratio of the number of crystal elements of the main power unit to the sampling unit in the power tube, and ensures that the source potentials of the two are consistent through the closed-loop control of the operational amplifier, thereby obtaining a sampling current strictly proportional to the main loop current. When the MOS works in the linear region, it is equivalent to a linear resistor, whose resistance Ron and mobility μ, gate oxide capacitance Figure 7 , width-length ratio and overdrive voltage Vgs-Vth are related as:
[0007]
[0008] The theoretical formula can be derived as:
[0009]
[0010] According to the above theoretical analysis, to improve the current proportion accuracy K, the interference of must be reduced as much as possible. However, this scheme has an inherent defect: when the load current is extremely low, tends to zero, making it difficult for the system to maintain accurate current detection proportion accuracy in the highest to lowest range of load current (from large current to small current). SUMMARY
[0011] The technical problem to be solved by the present application is to provide a high-precision wide-range current detection circuit that reduces the input end mismatch of the operational amplifier and maintains accurate current detection proportion accuracy in the highest to lowest range of load current.
[0012] To solve the above technical problems, the technical solution adopted by the present application is:
[0013] A high-precision wide-range current detection circuit, comprising an auxiliary operational amplifier A1, a power tube MP, a sampling tube MS, a PMOS tube PM0, a resistor RS, an operational amplifier OP, a charge pump Charge Pump, a driving module DRIVER, and a high-voltage domain floating ground module HVSS_Gen, the drain of the power tube MP, the drain of the sampling tube MS, and the input of the charge pump Charge Pump are connected to the power supply voltage VCC, the gate of the power tube MP and the gate of the sampling tube MS are connected to the output of the driving module DRIVER, the source of the power tube MP is connected to the non-inverting input of the auxiliary operational amplifier A1, the load LOAD, and the inverting input of the operational amplifier OP, and generates an output voltage OUT, the source of the sampling tube MS is connected to the inverting input of the auxiliary operational amplifier A1 and the source of the PMOS tube PM0, the output of the auxiliary operational amplifier A1 is connected to the gate of the PMOS tube PM0, the drain of the PMOS tube PM0 is connected to one end of the resistor RS and generates a voltage signal VSENS, the other end of the resistor RS is grounded, the non-inverting input of the operational amplifier OP is connected to a reference voltage VREF, the output of the operational amplifier OP is connected to the input of the driving module DRIVER, the output of the charge pump Charge Pump is connected to the high-voltage end of the driving module DRIVER and generates a voltage signal VCP, and the output of the high-voltage domain floating ground module HVSS_Gen is connected to the low-voltage end of the driving module DRIVER and generates a voltage signal HVSS.
[0014] Further, the auxiliary operational amplifier A1 comprises a main transconductance amplifier Gm1, a transimpedance amplifier R, an auxiliary transconductance amplifier Gm2, switches S1-S7 and a capacitor C1, one end of the switch S1 is connected to the inverting input terminal of the auxiliary operational amplifier A1, one end of the switch S2 is connected to one end of the switch S3 and one end of the switch S4 and is the non-inverting input terminal of the auxiliary operational amplifier A1, the other end of the switch S1 is connected to the other end of the switch S3 and the inverting input terminal of the main transconductance amplifier Gm1, the other end of the switch S2 is connected to the other end of the switch S4 and the non-inverting input terminal of the main transconductance amplifier Gm1, the output terminal of the main transconductance amplifier Gm1 is connected to the input terminal of the transimpedance amplifier R and the output terminal of the auxiliary transconductance amplifier Gm2, the output terminal of the transimpedance amplifier R is connected to one end of the switch S5, one end of the switch S6 and one end of the capacitor C1 and generates the output signal Vout1, the other end of the switch S5 is the output terminal of the auxiliary operational amplifier A1, the other end of the capacitor C1 is connected to the ground, the other end of the switch S6 is connected to the inverting input terminal of the auxiliary transconductance amplifier Gm2, one end of the switch S7 is connected to the non-inverting input terminal of the auxiliary transconductance amplifier Gm2, and the other end of the switch S7 is connected to the bias voltage VCM.
[0015] Further, the switches S1, S2 and S5 are controlled by the control signal φ1, the switches S3, S4, S6 and S7 are controlled by the control signal φ2, and the control signal φ1 and the control signal φ2 are a pair of opposite phase signals.
[0016] Further, the driving module DRIVER comprises NMOS transistor M1, NMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, NMOS transistor M6, PMOS transistor M7, PMOS transistor M8, PMOS transistor M9, NMOS transistor M10, NMOS transistor M11, current source IB1, current source IB2, current source IB3, inverter INV and switches S8-S11, the drain of NMOS transistor M1 is connected with the gate of NMOS transistor M1 and the gate of NMOS transistor M2 and serves as the input terminal of the driving module DRIVER, the source of NMOS transistor M1 is connected with the source of NMOS transistor M2 and one end of current source IB1, the drain of NMOS transistor M2 is connected with the drain of PMOS transistor M3, the gate of PMOS transistor M3, the gate of PMOS transistor M4 and the gate of PMOS transistor M5, the drain of PMOS transistor M4 is connected with the input terminal of inverter INV and one end of current source IB2 at node A, the drain of PMOS transistor M5 is connected with one end of switch S8, the other end of switch S8 is connected with one end of switch S9, one end of switch S10, the drain of NMOS transistor M10, the gate of NMOS transistor M10 and the gate of NMOS transistor M11, the other end of switch S9 is connected with the drain of NMOS transistor M6, the output terminal of inverter INV is connected with the gate of NMOS transistor M6, the other end of switch S10 is connected with the drain of PMOS transistor M8, the gate of PMOS transistor M8 is connected with the gate of PMOS transistor M7, the drain of PMOS transistor M7 and one end of current source IB3 and the gate of PMOS transistor M9, the other end of current source IB3 is grounded, the drain of PMOS transistor M9 is connected with one end of switch S11, the other end of switch S11 is connected with the drain of NMOS transistor M11 and serves as the output terminal of the driving module DRIVER, the source of PMOS transistor M3, the source of PMOS transistor M4, the source of PMOS transistor M5, the source of PMOS transistor M7, the source of PMOS transistor M8 and the source of PMOS transistor M9 are connected with voltage signal VCP, the other end of current source IB1, the other end of current source IB2, the source of NMOS transistor M6, the source of NMOS transistor M10 and the source of NMOS transistor M11 are connected with voltage signal HVSS.
[0017] Further, the switches S8, S9, S11 are controlled by control signal φ3, the switch S10 is controlled by control signal φ4, the control signal φ3 and the control signal φ4 are a pair of inverse signals.
[0018] Further, the high voltage domain floating ground module HVSS_Gen comprises a coarse ground generating circuit, a reference voltage circuit, a feedback resistance network, a low voltage error amplifier EA, a regulating tube NM1 and a current adaptive regulating circuit, the coarse ground generating circuit generates a voltage VSS based on a power supply voltage VCC, the reference voltage circuit generates a reference voltage VREF based on the power supply voltage VCC and the voltage VSS, a non-inverting input terminal of the low voltage error amplifier EA is connected to the reference voltage VREF, an inverting input terminal of the low voltage error amplifier EA is connected to an output terminal of the feedback resistance network, an output terminal of the error amplifier EA is connected to a gate of the regulating tube NM1 and an input terminal of the current adaptive regulating circuit, a drain of the regulating tube NM1 is connected to the power supply voltage VCC, a source of the regulating tube NM1 is connected to an output terminal of the current adaptive regulating circuit and generates a voltage signal HVSS, and the feedback resistance network divides the power supply voltage VCC and the voltage signal HVSS and outputs.
[0019] Further, the coarse ground generating circuit comprises a PMOS tube PM2, a PMOS tube PM3, an NMOS tube NM6, a high voltage NMOS tube NM7, a high voltage NMOS tube NM8, a current source I1 and a current source I2, a source of the PMOS tube PM2 and a drain of the NMOS tube NM6 are connected to the power supply voltage VCC, a gate of the PMOS tube PM2 is connected to a drain of the PMOS tube PM2 and a source of the PMOS tube PM3, a gate of the PMOS tube PM3 is connected to a drain of the PMOS tube PM3, a gate of the NMOS tube NM6 and a drain of the high voltage NMOS tube NM7, a source of the NMOS tube NM6 is connected to a drain of the high voltage NMOS tube NM8 and generates the voltage VSS, a gate of the high voltage NMOS tube NM7 and a gate of the high voltage NMOS tube NM8 are connected to an enable signal EN, a source of the high voltage NMOS tube NM7 is connected to one end of the current source I1, a source of the high voltage NMOS tube NM8 is connected to one end of the current source I2, the other end of the current source I1 and the other end of the current source I2 are grounded.
[0020] Furthermore, the current adaptive regulation circuit includes an NMOS transistor NM2, a high-voltage PMOS transistor PM1, an NMOS transistor NM3, an NMOS transistor NM4, a high-voltage NMOS transistor NM5, and a current source I0. One end of the current source I0 is connected to the power supply voltage VCC, and the other end of the current source I0 is connected to the drain of the NMOS transistor NM2 and the source of the high-voltage PMOS transistor PM1. The gate of the NMOS transistor NM2 serves as the input terminal of the current adaptive regulation circuit and is connected to the output terminal of the low-voltage error amplifier EA and the gate of the regulating transistor NM1. The source of the NMOS transistor NM2... The high-voltage PMOS transistor PM1 is connected to the drain of the high-voltage NMOS transistor NM5 and serves as the output of the current adaptive regulation circuit to generate a voltage signal HVSS. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage VSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3, and the gate of the NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of the NMOS transistor NM4. The sources of the NMOS transistors NM3 and NM4 are grounded.
[0021] Furthermore, the feedback resistor network includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VCC, and the other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the feedback resistor network. The other end of resistor R2 is connected to the voltage signal HVSS.
[0022] Compared with the prior art, the present invention has the following advantages and effects:
[0023] 1. This invention uses Auto-Zero dynamic zeroing technology to significantly reduce operational amplifier input mismatch;
[0024] 2. This invention introduces an additional loop that only intervenes when the load current is very low to regulate the overdrive voltage of the power transistor. ,Will By fixing a certain voltage, the system can maintain accurate current sensing ratio across the range of load current from highest to lowest (from high current to low current). Attached Figure Description
[0025] Figure 1 This is a schematic diagram of a high-precision, wide-range current detection circuit according to the present invention.
[0026] Figure 2 This is the circuit diagram of the auxiliary operational amplifier A1 of the present invention.
[0027] Figure 3 This is a circuit diagram of the driver module (DRIVER) of this invention.
[0028] Figure 4is a circuit diagram of a high-voltage domain floating ground module HVSS_Gen of the present application.
[0029] Figure 5 is a circuit diagram of a coarse adjustment ground generation circuit of the present application.
[0030] Figure 6 is a schematic diagram of a resistive sensing architecture of the prior art.
[0031] Figure 7 is a schematic diagram of a SenseFET technology based architecture of the prior art. DETAILED DESCRIPTION
[0032] In order to make the present application clearer, the technical solutions adopted by the present application to achieve the predetermined technical objectives will be described in detail below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and the technical means or technical features in the embodiments of the present application can be replaced without creative labor. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
[0033] As shown in Figure 1 A high-precision wide-range current detection circuit of the present application includes an auxiliary operational amplifier A1, a power tube MP, a sampling tube MS, a PMOS tube PM0, a resistor RS, an operational amplifier OP, a charge pump Charge Pump, a driving module DRIVER, and a high-voltage domain floating ground module HVSS_Gen. The drain of the power tube MP, the drain of the sampling tube MS, and the input of the charge pump Charge Pump are connected to a power supply voltage VCC. The gate of the power tube MP is connected to the gate of the sampling tube MS and the output of the driving module DRIVER. The source of the power tube MP is connected to the non-inverting input of the auxiliary operational amplifier A1, a load LOAD, and the inverting input of the operational amplifier OP, and generates an output voltage OUT. The source of the sampling tube MS is connected to the inverting input of the auxiliary operational amplifier A1 and the source of the PMOS tube PM0. The output of the auxiliary operational amplifier A1 is connected to the gate of the PMOS tube PM0. The drain of the PMOS tube PM0 is connected to one end of the resistor RS and generates a voltage signal VSENS. The other end of the resistor RS is grounded. The non-inverting input of the operational amplifier OP is connected to a reference voltage VREF. The output of the operational amplifier OP is connected to the input of the driving module DRIVER. The output of the charge pump Charge Pump is connected to the high-voltage end of the driving module DRIVER and generates a voltage signal VCP. The output of the high-voltage domain floating ground module HVSS_Gen is connected to the low-voltage end of the driving module DRIVER and generates a voltage signal HVSS.
[0034] The current signal is converted into a voltage signal VSENS by sampling the load current IL with a sampling ratio of 1:K and using a sampling resistor RS. To achieve high-precision current sampling in a wide dynamic range, the system uses an auxiliary operational amplifier A1 to force the source potentials of the sampling transistor MS and the power transistor MP to be equal. The auxiliary operational amplifier A1 uses the dynamic auto-zero technology to effectively suppress the input offset voltage to below 1 mV. In the feedback control loop, the source voltage of the power transistor MP is sampled and fed back to the operational amplifier OP. The output signal of the operational amplifier OP is transmitted to the driving module DRIVER, which operates in the high-voltage domain and is powered by the charge pump Charge Pump and the high-voltage domain floating ground module HVSS_Gen. Finally, the driving module DRIVER dynamically adjusts the gate voltage of the power transistor MP to ensure that the output voltage OUT is stable within the ideal working range.
[0035] As shown in Figure 2 The auxiliary operational amplifier A1 includes a main transconductance amplifier Gm1, a transimpedance amplifier R, an auxiliary transconductance amplifier Gm2, switches S1-S7, and a capacitor C1. One end of the switch S1 serves as the inverting input terminal of the auxiliary operational amplifier A1. One end of the switch S2 is connected to one end of the switch S3 and one end of the switch S4, and serves as the non-inverting input terminal of the auxiliary operational amplifier A1. The other end of the switch S1 is connected to the other end of the switch S3 and the inverting input terminal of the main transconductance amplifier Gm1. The other end of the switch S2 is connected to the other end of the switch S4 and the non-inverting input terminal of the main transconductance amplifier Gm1. The output terminal of the main transconductance amplifier Gm1 is connected to the input terminal of the transimpedance amplifier R and the output terminal of the auxiliary transconductance amplifier Gm2. The output terminal of the transimpedance amplifier R is connected to one end of the switch S5, one end of the switch S6, and one end of the capacitor C1, and generates an output signal Vout1. The other end of the switch S5 serves as the output terminal of the auxiliary operational amplifier A1. The other end of the capacitor C1 is grounded. The other end of the switch S6 is connected to the inverting input terminal of the auxiliary transconductance amplifier Gm2. One end of the switch S7 is connected to the non-inverting input terminal of the auxiliary transconductance amplifier Gm2. The other end of the switch S7 is connected to the bias voltage VCM.
[0036] The switches S1, S2, and S5 are controlled by the control signal φ1, and the switches S3, S4, S6, and S7 are controlled by the control signal φ2. The control signal φ1 and the control signal φ2 are a pair of complementary signals.
[0037] The first stage, first control signal φ1 control switch S1, S2, S5 closed, control signal φ2 control switch S3, S4, S6, S7 is disconnected, auxiliary operational amplifier A1 is in the amplification stage, the output signal Vout1 voltage output end is: Vout1=gm1*R*Vos1, wherein gm1 is the main transconductance amplifier Gm1 amplification factor, R is the transimpedance amplifier R amplification factor, Vos1 is the main transconductance amplifier Gm1 positive input end introduced by the offset voltage, the voltage and DC voltage input signal Vout1 are all on the capacitor C1, and the voltage is maintained after the control signal φ1 is disconnected stage external PMOS PM1 state. The second stage, control signal φ2 control switch S3, S4, S6, S7 is closed, control signal φ1 control switch S1, S2, S5 is disconnected, auxiliary operational amplifier A1 into the zero phase, auxiliary operational amplifier A1 input short circuit, output circuit, auxiliary transconductance amplifier Gm2 intervention, capacitor C1 will have the first stage main transconductance amplifier Gm1 mismatch charge information input to the auxiliary transconductance amplifier Gm2 negative feedback loop will offset voltage Vos1 mismatch charge offset, while considering the auxiliary transconductance amplifier Gm2 introduced by the offset voltage Vos2, can be written as:
[0038] ;
[0039] The corresponding input end equivalent mismatch will be greatly reduced. Bias voltage VCM and the first stage DC bias point after the average value is the same:
[0040] .
[0041] As Figure 3As shown, the driving module DRIVER comprises NMOS transistor M1, NMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, NMOS transistor M6, PMOS transistor M7, PMOS transistor M8, PMOS transistor M9, NMOS transistor M10, NMOS transistor M11, current source IB1, current source IB2, current source IB3, inverter INV and switches S8-S11, the drain of NMOS transistor M1 is connected with the gate of NMOS transistor M1 and the gate of NMOS transistor M2 and serves as the input terminal of the driving module DRIVER, the source of NMOS transistor M1 is connected with the source of NMOS transistor M2 and one end of current source IB1, the drain of NMOS transistor M2 is connected with the drain of PMOS transistor M3, the gate of PMOS transistor M3, the gate of PMOS transistor M4 and the gate of PMOS transistor M5, the drain of PMOS transistor M4 is connected with the input terminal of inverter INV and one end of current source IB2 at node A, the drain of PMOS transistor M5 is connected with one end of switch S8, the other end of switch S8 is connected with one end of switch S9, one end of switch S10, the drain of NMOS transistor M10, the gate of NMOS transistor M10 and the gate of NMOS transistor M11, the other end of switch S9 is connected with the drain of NMOS transistor M6, the output terminal of inverter INV is connected with the gate of NMOS transistor M6, the other end of switch S10 is connected with the drain of PMOS transistor M8, the gate of PMOS transistor M8 is connected with the gate of PMOS transistor M7, the drain of PMOS transistor M7 and one end of current source IB3 and the gate of PMOS transistor M9, the other end of current source IB3 is grounded, the drain of PMOS transistor M9 is connected with one end of switch S11, the other end of switch S11 is connected with the drain of NMOS transistor M11 at GATE node and serves as the output terminal of the driving module DRIVER, the source of PMOS transistor M3, the source of PMOS transistor M4, the source of PMOS transistor M5, the source of PMOS transistor M7, the source of PMOS transistor M8 and the source of PMOS transistor M9 are connected with voltage signal VCP, the other end of current source IB1, the other end of current source IB2, the source of NMOS transistor M6, the source of NMOS transistor M10 and the source of NMOS transistor M11 are connected with voltage signal HVSS.
[0042] Switches S8, S9 and S11 are controlled by control signal φ3, switch S10 is controlled by control signal φ4, control signal φ3 and control signal φ4 are a pair of inverse signals.
[0043] When output voltage OUT is in low voltage state, the output of operational amplifier OP is in low level.
[0044] When the voltage of the output voltage OUT is in the lower range relative to the power supply voltage VCC, the operational amplifier OP outputs a low level, causing the NMOS transistor M1 and the NMOS transistor M2 to be turned off. At this time, the PMOS transistors M3, M4 and M5 are in a high resistance state due to the absence of a bias current, the node A is pulled down to a low level by the current source IB2, and the NMOS transistor M6 is turned on through the inverter INV.
[0045] In the first stage: the control signal φ3 controls the switches S8, S9 and S11 to be closed, and the control signal φ4 controls the switch S10 to be opened. The PMOS transistor M9 mirrors the current source IB3 current to charge the GATE node, causing the voltage of the GATE node to rise. The NMOS transistors M10 and M11 are turned off due to the pull-down effect of the NMOS transistor M6, and do not affect the charging process.
[0046] In the second stage: the control signal φ3 controls the switches S8, S9 and S11 to be opened, and the control signal φ4 controls the switch S10 to be closed. The PMOS transistor M8, the NMOS transistor M10 and the NMOS transistor M11 accurately copy the current source IB3 current to form a discharge path for the GATE node, causing the voltage of the GATE node to drop. At this time, the dynamic adjustment of the voltage of the GATE node is determined by the charging and discharging current of the current source IB3.
[0047] When the output voltage OUT is in a high voltage state, the operational amplifier OP outputs a high level.
[0048] When the voltage of the output voltage OUT is too high, the operational amplifier OP outputs a high level to activate the NMOS transistors M1 and M2 (the current of the NMOS transistor M2 is 3 times that of the NMOS transistor M1). At this time, the PMOS transistor M4 mirrors the 0.75*IB1 current, which is greater than the current of the current source IB2, causing the node A to be pulled high, the inverter INV outputs a low level, and the NMOS transistor M6 is turned off.
[0049] In the first stage: the control signal φ3 controls the switches S8, S9 and S11 to be closed, and the control signal φ4 controls the switch S10 to be opened. The PMOS transistor M5 mirrors the 0.75*IB1 current, and the PMOS transistor M9 mirrors the IB3 current in the first stage. The charging current of the GATE node is IB3+0.75*IB1 (enhanced charging capability).
[0050] In the second stage: the control signal φ3 controls the switches S8, S9 and S11 to be opened, and the control signal φ4 controls the switch S10 to be closed. The discharging current of the GATE node is still IB3 (maintaining the reference discharge).
[0051] Due to the fact that the charging current is significantly greater than the discharging current, the voltage of the GATE node continues to rise, thereby adjusting the gate of the power transistor and reducing the voltage of the output voltage OUT, achieving closed-loop control.
[0052] As shown in Figure 4 The high-voltage domain floating ground module HVSS_Gen comprises a coarse ground generating circuit, a reference voltage circuit, a feedback resistance network, a low-voltage error amplifier EA, a regulating tube NM1 and a current adaptive adjusting circuit. The coarse ground generating circuit generates a voltage VSS based on a power supply voltage VCC. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VCC and the voltage VSS. The non-inverting input terminal of the low-voltage error amplifier EA is connected to the reference voltage VREF. The inverting input terminal of the low-voltage error amplifier EA is connected to the output terminal of the feedback resistance network. The output terminal of the error amplifier EA is connected to the gate of the regulating tube NM1 and the input terminal of the current adaptive adjusting circuit. The drain of the regulating tube NM1 is connected to the power supply voltage VCC. The source of the regulating tube NM1 is connected to the output terminal of the current adaptive adjusting circuit and generates a voltage signal HVSS. The feedback resistance network divides the power supply voltage VCC and the voltage signal HVSS and outputs.
[0053] As shown in Figure 5 The coarse ground generating circuit comprises a PMOS tube PM2, a PMOS tube PM3, an NMOS tube NM6, a high-voltage NMOS tube NM7, a high-voltage NMOS tube NM8, a current source I1 and a current source I2. The source of the PMOS tube PM2 and the drain of the NMOS tube NM6 are connected to the power supply voltage VCC. The gate of the PMOS tube PM2 is connected to the drain of the PMOS tube PM2 and the source of the PMOS tube PM3. The gate of the PMOS tube PM3 is connected to the drain of the PMOS tube PM3, the gate of the NMOS tube NM6 and the drain of the high-voltage NMOS tube NM7. The source of the NMOS tube NM6 is connected to the drain of the high-voltage NMOS tube NM8 and generates the voltage VSS. The gate of the high-voltage NMOS tube NM7 and the gate of the high-voltage NMOS tube NM8 are connected to an enable signal EN. The source of the high-voltage NMOS tube NM7 is connected to one end of the current source I1. The source of the high-voltage NMOS tube NM8 is connected to one end of the current source I2. The other end of the current source I1 and the other end of the current source I2 are grounded.
[0054] The current self-adapting adjusting circuit comprises NMOS NM2, high-voltage PMOS PM1, NMOS NM3, NMOS NM4, high-voltage NMOS NM5 and current source I0. One end of the current source I0 is connected to the power supply voltage VCC, and the other end of the current source I0 is connected to the drain of the NMOS NM2 and the source of the high-voltage PMOS PM1. The gate of the NMOS NM2 is connected to the output of the low-voltage error amplifier EA and the gate of the adjusting tube NM1 as the input of the current self-adapting adjusting circuit. The source of the NMOS NM2 is connected to the drain of the high-voltage NMOS NM5 and generates the voltage signal HVSS as the output of the current self-adapting adjusting circuit. The gate of the high-voltage PMOS PM1 is connected to the voltage VSS. The drain of the high-voltage PMOS PM1 is connected to the drain of the NMOS NM3, the gate of the NMOS NM3 and the gate of the NMOS NM4. The gate of the high-voltage NMOS NM5 is connected to the enable signal EN. The source of the high-voltage NMOS NM5 is connected to the drain of the NMOS NM4. The source of the NMOS NM3 and the source of the NMOS NM4 are grounded.
[0055] The feedback resistance network comprises resistors R1 and R2. One end of the resistor R1 is connected to the power supply voltage VCC. The other end of the resistor R1 is connected to one end of the resistor R2 and serves as the output of the feedback resistance network. The other end of the resistor R2 is connected to the voltage signal HVSS.
[0056] The coarse adjustment generating circuit provides the ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. When the enable signal EN becomes high, the NMOS NM7 and the NMOS NM8 are turned on, the gate-source voltage of the PMOS PM2 is |VGS1|, the gate-source voltage of the PMOS PM3 is |VGS2|, and the gate-source voltage of the NMOS NM6 is VGS3. The voltage HVSS is represented as: HVSS=VDD-|VGS1|-|VGS2|-VGS3.
[0057] The reference voltage circuit provides the accurate reference voltage VREF for the low-voltage error amplifier EA. The reference voltage VREF is connected to the non-inverting input of the low-voltage error amplifier EA and obtains the accurate voltage signal HVSS through the feedback resistance network composed of the resistors R1 and R2 and the adjusting tube NM1. The voltage signal HVSS is represented as:
[0058] .
[0059] When the power supply voltage VCC is powered on, the enable signal EN becomes high level, the circuit output voltage HVSS is first generated in a rough adjustment, the voltage HVSS provides a ground voltage for the reference voltage circuit, and then the feedback resistor network, the low-voltage error amplifier EA, the adjusting tube NM1 and the current adaptive adjusting circuit start to work, and the finally output voltage signal HVSS is the accurate floating reference ground voltage with a fixed voltage difference from the power supply voltage VDD.
[0060] The working interval of the reference voltage circuit is the power supply voltage VDD to the voltage VSS, and the working interval of the low-voltage error amplifier EA is the power supply voltage VDD to the voltage signal HVSS. The voltage difference between the working interval of the reference voltage circuit and the working interval of the low-voltage error amplifier EA is low voltage, and high-voltage tubes are not required, which greatly saves the area.
[0061] The current I0 generated by the current source I0 is divided into two paths and flows into the NMOS tube NM2 and the high-voltage PMOS tube PM1 respectively. It is assumed that the current flowing through the NMOS tube NM2 is I1, and the current flowing through the high-voltage PMOS tube PM1 is I2, then I0=I1+I2; since the width-length ratio of the adjusting tube NM1 and the NMOS tube NM2 is in the ratio of m:1, the current flowing through the adjusting tube NM1 is m*I1; the current flowing through the NMOS tube NM3 is equal to the current I2 flowing through the high-voltage PMOS tube PM1, and since the width-length ratio of the NMOS tube NM4 and the NMOS tube NM3 is in the ratio of n:1, the current flowing through the NMOS tube NM4 is n*I2.
[0062] The load works between the power supply voltage VCC and the voltage signal HVSS, and the load current is IL. The current flowing through the NMOS tube NM4 is equal to the sum of the current I1 flowing through the NMOS tube NM2, the current m*I1 of the adjusting tube NM1 and the load current IL, and therefore the current flowing through the NMOS tube NM4 is represented as:
[0063] .
[0064] If the load current increases, the current flowing through the NMOS tube NM4 increases, that is, I2 increases, and because I0=I1+I2, the current I1 flowing through the NMOS tube NM2 decreases, thereby realizing that the power consumption changes with the load current.
[0065] When the load is not working, that is, the load current IL=0, at this time the current flowing through the NMOS tube NM4 is only:
[0066] .
[0067] And the corresponding current of the floating ground generating circuit in the prior art is , so the current is reduced by , thereby reducing the power consumption of the circuit when the load is not working.
[0068] The present application uses Auto-Zero dynamic zeroing technology to greatly reduce the input mismatch of the operational amplifier; the present application introduces an additional loop, which only intervenes in the work when the load current is very low, to adjust the overdrive voltage of the power tube , the is fixed at a certain voltage, so that the system can maintain accurate current detection proportion accuracy at the same time in the highest to the lowest range of load current (from large current to small current).
[0069] The above is only the preferred embodiment of the present application, not any form of limitation on the present application, although the present application has been disclosed as above with the preferred embodiment, however, it is not intended to limit the present application, any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content for equivalent embodiments, but as long as it does not deviate from the technical solution of the present application, according to the technical essence of the present application, within the spirit and principles of the present application, any simple modification, equivalent replacement and improvement of the above embodiments, all still belong to the protection scope of the technical solution of the present application.
Claims
1. A high-precision, wide-range current detection circuit, characterized in that: This system includes an auxiliary operational amplifier (OPA) A1, a power transistor (MP), a sampling transistor (MS), a PMOS transistor (PM0), a resistor (RS), an operational amplifier (OP), a charge pump (DRIVER), a driver module (DRIVER), and a high-voltage floating ground module (HVSS_Gen). The drains of the power transistor (MP), the sampling transistor (MS), and the input of the charge pump are connected to the power supply voltage VCC. The gate of the power transistor (MP) is connected to the gate of the sampling transistor (MS) and the output of the driver module (DRIVER). The source of the power transistor (MP) is connected to the non-inverting input of the auxiliary OPA A1, the load (LOAD), and the inverting input of the OPA OP, generating an output voltage (OUT). The source of the sampling transistor (MS) is connected to the inverting input of the auxiliary OPA A1 and the source of the PMOS transistor (PM0). The output of the auxiliary OPA A1 is connected to the gate of the PMOS transistor (PM0). The drain of the PMOS transistor (PM0) is connected to one end of the resistor (RS), generating a voltage signal (VSENS). The other end of the resistor (RS) is grounded. The non-inverting input of the OPA OP is connected to the reference voltage (VREF). The output of the OPA OP is connected to the input of the driver module (DRIVER). The charge pump... The output of Pump is connected to the high-voltage terminal of the driver module and generates a voltage signal VCP. The output of the high-voltage domain floating ground module HVSS_Gen is connected to the low-voltage terminal of the driver module and generates a voltage signal HVSS. The high-voltage floating ground module HVSS_Gen includes a coarse-tuning ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment transistor NM1, and a current adaptive adjustment circuit. The coarse-tuning ground generation circuit generates a voltage VSS based on the power supply voltage VCC. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VCC and the voltage VSS. The non-inverting input of the low-voltage error amplifier EA is connected to the reference voltage VREF, and the inverting input of the low-voltage error amplifier EA is connected to the output of the feedback resistor network. The output of the error amplifier EA is connected to the gate of the adjustment transistor NM1 and the input of the current adaptive adjustment circuit. The drain of the adjustment transistor NM1 is connected to the power supply voltage VCC, and the source of the adjustment transistor NM1 is connected to the output of the current adaptive adjustment circuit to generate a voltage signal HVSS. The feedback resistor network divides the power supply voltage VCC and the voltage signal HVSS for output.
2. The high-precision wide-range current detection circuit according to claim 1, characterized in that: The auxiliary operational amplifier A1 includes a main transconductance amplifier Gm1, a transimpedance amplifier R, an auxiliary transconductance amplifier Gm2, switches S1-S7, and a capacitor C1. One end of switch S1 serves as the inverting input of auxiliary operational amplifier A1. One end of switch S2 is connected to one end of switches S3 and one end of switch S4, serving as the non-inverting input of auxiliary operational amplifier A1. The other end of switch S1 is connected to the other end of switch S3 and the inverting input of the main transconductance amplifier Gm1. The other end of switch S2 is connected to the other end of switch S4 and the non-inverting input of the main transconductance amplifier Gm1. The output terminal of the transimpedance amplifier Gm1 is connected to the input terminal of the transimpedance amplifier R and the output terminal of the auxiliary transconductance amplifier Gm2. The output terminal of the transimpedance amplifier R is connected to one end of switch S5, one end of switch S6 and one end of capacitor C1 to generate the output signal Vout1. The other end of switch S5 serves as the output terminal of the auxiliary operational amplifier A1. The other end of capacitor C1 is grounded. The other end of switch S6 is connected to the inverting input terminal of the auxiliary transconductance amplifier Gm2. One end of switch S7 is connected to the non-inverting input terminal of the auxiliary transconductance amplifier Gm2. The other end of switch S7 is connected to the bias voltage VCM.
3. The high-precision wide-range current detection circuit according to claim 2, characterized in that: The switches S1, S2, and S5 are controlled by control signal φ1, and the switches S3, S4, S6, and S7 are controlled by control signal φ2. Control signal φ1 and control signal φ2 are a pair of inverted signals.
4. The high-precision wide-range current detection circuit according to claim 1, characterized in that: The drive module (DRIVER) includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11, current sources IB1, IB2, and IB3, an inverter INV, and switches S8 to S11. The drain of NMOS transistor M1 is connected to the gate of NMOS transistor M1 and the gate of NMOS transistor M2, and serves as the drive module (DRIVE). The input terminal of R is connected to the source of NMOS transistor M1, the source of NMOS transistor M2, and one end of current source IB1. The drain of NMOS transistor M2 is connected to the drain, gate, gate, and gate of PMOS transistor M3, PMOS transistor M4, and PMOS transistor M5. The drain of PMOS transistor M4 is connected to the input terminal of inverter INV and one end of current source IB2 at node A. The drain of PMOS transistor M5 is connected to one end of switch S8. The other end of switch S8 is connected to one end of switch S9, one end of switch S10, and NMOS transistor M1. The drain of NMOS transistor M10, the gate of NMOS transistor M10, and the gate of NMOS transistor M11 are connected. The other end of switch S9 is connected to the drain of NMOS transistor M6. The output of inverter INV is connected to the gate of NMOS transistor M6. The other end of switch S10 is connected to the drain of PMOS transistor M8. The gate of PMOS transistor M8 is connected to the gate of PMOS transistor M7. The drain of PMOS transistor M7 and one end of current source IB3 are connected to the gate of PMOS transistor M9. The other end of current source IB3 is grounded. The drain of PMOS transistor M9 is connected to the drain of switch S11. One end is connected, and the other end of switch S11 is connected to the drain of NMOS transistor M11 and serves as the output terminal of the driver module. The sources of PMOS transistors M3, M4, M5, M7, M8, and M9 are connected to the voltage signal VCP. The other ends of current source IB1 and IB2, the sources of NMOS transistors M6, M10, and M11 are connected to the voltage signal HVSS.
5. A high-precision, wide-range current detection circuit according to claim 4, characterized in that: The switches S8, S9, and S11 are controlled by control signal φ3, and the switch S10 is controlled by control signal φ4. Control signal φ3 and control signal φ4 are a pair of inverted signals.
6. The high-precision wide-range current detection circuit according to claim 1, characterized in that: The coarse ground generation circuit includes PMOS transistors PM2 and PM3, NMOS transistor NM6, high-voltage NMOS transistor NM7 and NM8, current source I1, and current source I2. The source of PMOS transistor PM2 and the drain of NMOS transistor NM6 are connected to the power supply voltage VCC. The gate of PMOS transistor PM2 is connected to the drain of PMOS transistor PM2 and the source of PMOS transistor PM3. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3, the gate of NMOS transistor NM6, and the drain of high-voltage NMOS transistor NM7. The source of NMOS transistor NM6 is connected to the drain of high-voltage NMOS transistor NM8 and generates voltage VSS. The gates of high-voltage NMOS transistor NM7 and NM8 are connected to the enable signal EN. The source of high-voltage NMOS transistor NM7 is connected to one end of current source I1, and the source of high-voltage NMOS transistor NM8 is connected to one end of current source I2. The other ends of current sources I1 and I2 are grounded.
7. The high-precision wide-range current detection circuit according to claim 1, characterized in that: The current adaptive regulation circuit includes an NMOS transistor NM2, a high-voltage PMOS transistor PM1, an NMOS transistor NM3, an NMOS transistor NM4, a high-voltage NMOS transistor NM5, and a current source I0. One end of the current source I0 is connected to the power supply voltage VCC, and the other end of the current source I0 is connected to the drain of the NMOS transistor NM2 and the source of the high-voltage PMOS transistor PM1. The gate of the NMOS transistor NM2 serves as the input terminal of the current adaptive regulation circuit and is connected to the output terminal of the low-voltage error amplifier EA and the gate of the regulating transistor NM1. The source of the NMOS transistor NM2 is connected to the high-voltage PMOS transistor PM1. The drain of NMOS transistor NM5 is connected and serves as the output of the current adaptive regulation circuit to generate a voltage signal HVSS. The gate of high-voltage PMOS transistor PM1 is connected to the voltage VSS. The drain of high-voltage PMOS transistor PM1 is connected to the drain of NMOS transistor NM3, the gate of NMOS transistor NM3, and the gate of NMOS transistor NM4. The gate of high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of high-voltage NMOS transistor NM5 is connected to the drain of NMOS transistor NM4. The sources of NMOS transistor NM3 and NMOS transistor NM4 are grounded.
8. The high-precision wide-range current detection circuit according to claim 1, characterized in that: The feedback resistor network includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VCC, and the other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the feedback resistor network. The other end of resistor R2 is connected to the voltage signal HVSS.
Citation Information
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