An interference rejection circuit for AC measurements

Abstract

The application provides an interference suppression circuit for AC measurement, and belongs to the technical field of electric variable measurement, and comprises a current loop and a measurement loop; the current loop comprises a voltage signal source which is used for outputting a voltage signal with a frequency of fa; a first flip-flop circuit which is controlled to output a signal in a set period; and a measured product which is connected between the first flip-flop circuit and a ground end; the measurement loop comprises a second flip-flop circuit which receives a measurement signal between the two ends of the measured product, amplifies the measurement signal, and is controlled to output a signal in a set period according to the frequency fa; a second low-pass filter which is connected with an output end of the second flip-flop circuit; and an analog-to-digital converter which is connected with an output end of the second low-pass filter; the interference suppression circuit for AC measurement can retain useful signals and filter out interference components; in the application, the current flowing through the measured product is constant, the voltage generated on the measured product does not fluctuate any more, and the measured value of the resistance value of the measured product does not fluctuate either.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of measuring electrical variables, and particularly relates to an interference suppression circuit for AC measurement. BACKGROUND

[0002] When testing an AC resistance, the resistance value of the AC resistance to be tested can be measured by passing an AC current of a fixed frequency and a fixed effective value through the AC resistance to be tested and measuring an AC voltage Vin generated on the AC resistance. However, when there is an interference source with a frequency close to the test frequency near the AC resistance test equipment, the voltage signal Ven of the interference will be coupled to the AC voltage Vin, and the interference signal and the useful signal will be amplified by the inverting circuit together. The closer the frequencies of the useful signal and the interference signal, the longer the fluctuation period, and the greater the influence on the stability of the measurement result. SUMMARY

[0003] The present application proposes an interference suppression circuit for AC measurement to solve the technical problem that the existing AC measurement is easily disturbed by interference signals with frequencies close to each other.

[0004] To solve the above technical problem, the present application adopts the following technical scheme:

[0005] An interference suppression circuit for AC measurement, comprising a current loop and a measurement loop.

[0006] The current loop comprises:

[0007] a voltage signal source for outputting a voltage signal with a frequency of fa;

[0008] a first inverting circuit for receiving and amplifying the output signal of the voltage signal source and controlled to invert and output the signal according to a set period;

[0009] a measured product connected between the first inverting circuit and a ground terminal;

[0010] The measurement loop comprises:

[0011] a second inverting circuit for receiving and amplifying a measurement signal across the measured product and controlled to invert and output the signal according to the set period;

[0012] a second low-pass filter connected to the output terminal of the second inverting circuit;

[0013] an analog-to-digital converter connected to the output terminal of the second low-pass filter for analog-to-digital conversion of the signal output by the second low-pass filter and sending the converted signal to a processor.

[0014] Compared with the prior art, the advantages and positive effects of the present application are that: the interference suppression circuit for AC measurement of the present application, the voltage signal source outputs a voltage signal of a specific frequency fa, the current generated by the voltage signal flows through the measured product to generate an AC voltage signal Vin, during the continuous transmission of Vin, an interference signal Ven of a similar frequency is introduced, the present application sets a first flip-flop circuit, which flips the output signal according to a set period, so that the phase of the AC voltage Vin generated when passing through the measured product is also reversed, a second flip-flop circuit is set, which flips the signal inputted according to the frequency of the voltage signal fa of the voltage signal source, flips the signal less than 0 to a positive value, and synchronously converts according to the flip period of the first flip-flop circuit, always keeping the output signal positive. Since the interference signal Ven is an external interference, it is only inverted once by the second flip-flop circuit, therefore, the interference signal outputted by the second flip-flop circuit is positive for one set period and negative for one set period, alternating. If the processor calculates the signal by averaging according to two set periods as a calculation period T, the useful signal is retained and the interference component is eliminated. Therefore, the measurement of the Vin voltage value will no longer fluctuate. The resistance value of the AC resistance is related to the voltage and current thereon, in the present application, the current flowing through the measured product is constant, and the voltage generated thereon no longer fluctuates, so the measured value of the resistance value of the measured product also does not fluctuate.

[0015] Other features and advantages of the present application will become more apparent from the detailed description of the embodiments of the present application in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a principle block diagram of an embodiment of the interference suppression circuit for AC measurement proposed by the present application;

[0017] Figure 2 is a principle diagram of an embodiment of the interference suppression circuit for AC measurement proposed by the present application;

[0018] Figure 3 is an output signal waveform diagram of an embodiment of the interference suppression circuit for AC measurement proposed by the present application. DETAILED DESCRIPTION

[0019] The specific embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0020] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0021] It should be noted that, in the description of the present application, the terms indicating the direction or position relationship of "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like are based on the direction or position relationship shown in the drawings, which is only for the convenience of description, and does not indicate or imply that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0022] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0023] Embodiment one, see Figure 1 As shown in the figure, an interference suppression circuit for AC measurement includes a current loop and a measurement loop.

[0024] The current loop includes a voltage signal source and a first flip-flop circuit, wherein the voltage signal source is used to output a voltage signal with a frequency of fa.

[0025] The first flip-flop circuit is used to receive the output signal of the voltage signal source for amplification, and is controlled to flip the signal output according to the set period.

[0026] The measured product is connected between the first flip-flop circuit and the ground end to form a current loop, and the current in the loop flows through the measured product, and an AC voltage is generated across the measured product.

[0027] The measurement loop includes a second flip-flop circuit, a second low-pass filter and an analog-to-digital converter.

[0028] The second flip circuit receives the voltage signal from both ends of the test object, which is the measurement signal, amplifies it, and controls the signal to flip and output according to a set period.

[0029] The second low-pass filter is connected to the output of the second flip circuit to filter out the interference signal after inversion, while the useful signal can pass through normally.

[0030] The analog-to-digital converter is connected to the output of the second low-pass filter and is used to convert the signal output by the second low-pass filter into an analog-to-digital signal and send it to the processor, which then calculates the resistance value of the tested object.

[0031] This embodiment's interference suppression circuit for AC measurement uses a voltage signal source that outputs a voltage signal at a specific frequency fa. The current generated by this voltage signal flows through the test object, producing an AC voltage signal Vin. As Vin continues to propagate, an interference signal Ven with a similar frequency is introduced. This solution addresses this by using a first flip circuit, which is controlled to flip the output signal according to a set period. Therefore, the phase of the AC voltage Vin generated when passing through the test object is also reversed. A second flip circuit is used, which controls the flipping of the signal based on the frequency of the voltage signal fa from the voltage signal source, flipping signals less than 0 to positive values. It also performs synchronous switching according to the flipping period of the first flip circuit, always maintaining a positive output signal. Since the interference signal Ven is externally introduced, it is only inverted once by the second flip circuit. Therefore, the interference signal output by the second flip circuit alternates between positive and negative values ​​for one set period. If the processor averages the signal according to two set periods as a calculation period T, the useful signal is retained, and the interference component is eliminated. Therefore, the measurement of the Vin voltage value will no longer fluctuate. The resistance value of an AC resistor is related to the voltage and current across it. In this invention, the current flowing through the test object is constant, and the voltage generated on it no longer fluctuates, so the measured value of the resistance of the test object also does not fluctuate.

[0032] The interference suppression circuit of this embodiment is particularly suitable for suppressing interference signals with frequencies similar to or the same as the voltage signal output from the voltage signal source.

[0033] In some embodiments, such as Figure 2 As shown, the first flip circuit includes a second inverter, a second inverter, a second switching switch, and a counter.

[0034] The counter is controlled by the processor. Different states of the control signal CTRL4 enable or disable the counter. When enabled, the counter starts counting based on the information from the signal CTRL6, changing the state of the output signal S29 every half of the processor's calculation cycle. When the counter is disabled, the second changeover switch also has a default state. In the default state, signals S26 and the output pin of the second changeover switch are turned on.

[0035] The input terminals of the second homodyne amplifier and the second inverter are connected with the output terminal of the voltage signal source.

[0036] The second homodyne amplifier receives the voltage signal output by the voltage signal source and outputs the voltage signal after homodyne amplification.

[0037] The second inverter receives the voltage signal output by the voltage signal source and outputs the voltage signal after inverting amplification.

[0038] The second switch has an output terminal as a common terminal, and the two movable terminals of the second switch are connected with the output terminals of the second homodyne amplifier and the second inverter respectively. The second switch is controlled to connect the second homodyne amplifier with the output terminal or to connect the second inverter with the output terminal. Since the second homodyne amplifier and the second inverter output signals with the same frequency and opposite phases, by controlling the output of the second homodyne amplifier or the second inverter at different time, the signal is flipped and output according to the set period.

[0039] The processor outputs a control signal containing information of the calculation period T to the counter, and the counter counts according to the control signal. The state of the output signal is changed once every T / 2, and the output signal of the counter is used to control the gating state of the second switch.

[0040] By controlling the state of the output signal to be changed once every T / 2, since the frequency of the interference signal is close to that of the useful signal, by controlling the state of the second switch, the second inverter is controlled to output for the signal less than 0, and the second homodyne amplifier is controlled to output for the signal greater than 0. The output useful signal becomes a useful direct current signal greater than 0 after the second low-pass filter, and the output interference signal of the second switch becomes a interference direct current signal greater than 0 in the first 0.5T period and a interference direct current signal less than 0 in the second 0.5T period, and the absolute values of the amplitudes are equal. The processor averages the received signal S17 according to the calculation period T, which includes digital quantities related to the interference k*Ven and digital quantities related to the useful signal k*Vin. As described above, the amplitudes of the digital quantities related to the interference in the period from 0T to 0.5T are opposite to those in the period from 0.5T to 1T, while the amplitudes of the digital quantities related to the useful signal are in the same direction in the two periods. Therefore, when the processor averages the signal S17 according to the calculation period T, the useful signal is retained, and the interference component with the same or similar frequency as the useful signal is eliminated. Therefore, the measurement of the Vin voltage value will no longer fluctuate. The resistance of the AC resistance is related to the voltage and current thereon. In the present application, the current flowing through the AC resistance is constant, and the voltage generated thereon no longer fluctuates, so the measured value of the resistance of the AC resistance also does not fluctuate.

[0041] In some embodiments, the interference suppression circuit further comprises a first low-pass filter, which receives the signal output by the second switch and outputs a low-pass filtered signal.

[0042] In some embodiments, the current loop further comprises a power amplifier, which receives the signal output by the first low-pass filter and outputs a current I to the current input terminal C+.

[0043] In some embodiments, the interference suppression circuit further comprises a standard resistor, an operational amplifier circuit, a sampling resistor, and a phase shift compensation circuit.

[0044] One of the two ends of the standard resistor is connected to the current input terminal C+ and the current output terminal C- through a switch, respectively, and the other end is connected to the measurement positive terminal S+ and the measurement negative terminal S- of the measurement loop through a switch, respectively.

[0045] The same direction input terminal of the operational amplifier circuit receives the signal output by the first flip-flop circuit, and the output terminal of the operational amplifier circuit is connected to the input terminal of the power amplifier.

[0046] One end of the sampling resistor is connected to the current output terminal C-, and the other end is connected to the ground terminal.

[0047] The phase shift compensation circuit receives the signal output by the first low-pass filter, performs zero-crossing detection on the signal to generate a square wave signal, and delays the phase of the square wave signal according to the phase control signal, and the delayed signal is used to control the flip-flop output of the second flip-flop circuit.

[0048] In some embodiments, the phase shift compensation circuit comprises a zero-crossing comparator and a phase control circuit.

[0049] The input terminal of the zero-crossing comparator is connected to the output terminal of the first low-pass filter, and the zero-crossing comparator performs zero-crossing detection on the received signal to generate a square wave signal and outputs the square wave signal.

[0050] The phase control circuit receives the square wave signal and the phase control signal, delays the phase of the square wave signal according to the phase control signal, and the output terminal of the phase control circuit is connected to the control terminal of the second flip-flop circuit.

[0051] In some embodiments, the second inverting circuit includes an amplifying circuit, a third homodyne, a third inverter, and a third switch.

[0052] The two inputs of the amplifying circuit are connected to the positive and negative measurement terminals S+ and S- respectively.

[0053] The third homodyne receives the output signal of the amplifying circuit and outputs the homodyne amplified signal.

[0054] The third inverter receives the output signal of the amplifying circuit and outputs the inverted amplified signal.

[0055] The common terminal of the third switch is the output terminal, the two moving points of the third switch are connected to the output terminals of the third homodyne and the third inverter respectively, and the control terminal of the third switch is connected to the output terminal of the phase modulation circuit.

[0056] One of the moving points of the third switch is connected to the output terminal of the third homodyne, the other moving point is connected to the output terminal of the third inverter, and the control terminal of the third switch is connected to the output terminal of the phase modulation circuit.

[0057] The output signal S28 of the second switch is connected to the input terminal of the first low-pass filter. The output signal S30 of the first low-pass filter is an alternating current signal with a frequency of fa. The signal S30 is connected to the input terminal of the zero-crossing comparator and the homodyne input terminal of the operational amplifier circuit. The output signal S32 of the zero-crossing comparator is a square wave signal with high and low voltage amplitudes. The inverted input terminal of the operational amplifier circuit is connected to one end of the sampling resistor, and the output of the operational amplifier circuit is connected to the power amplifier. The current I output by the power amplifier flows through the standard resistor from point A to point C, and then through the sampling resistor to the GND1 network. The frequency of the current I is fa.

[0058] Due to the virtual short concept of the operational amplifier circuit, the voltage on the sampling resistor is equal to the voltage of the signal S30. Since the resistance of the sampling resistor is constant, the current flowing through the sampling resistor is equal to the ratio of the voltage of the signal S30 to the resistance of the sampling resistor. Due to the virtual short of the operational amplifier circuit, the phase of the current I flowing through the sampling resistor is the same as the phase of the signal S30, so the phase of the signal S32 output by the zero-crossing comparator is the same as the phase of the current I. The signal S32 is connected to the input terminal of the high-speed isolator, which outputs the signal S18. The signal S18 is input to the signal input terminal of the phase modulation circuit, and the signal S13 output by the phase modulation circuit is used as the control signal of the switch state control terminal of the third switch. When the signal S13 is high, the third switch conducts the signals S11 and S15. When the signal S13 is low, the third switch conducts the signals S12 and S15.

[0059] The phase of signal S18 is the same as the phase of current I, but the input signal of the amplification circuit has some phase shift when passing through the amplification circuit and the third homodyne or the third reverse. Therefore, the introduced phase shift needs to be compensated by adjusting the phase between signal S18 and signal S13. Otherwise, there will be a phase difference between signal S13 and signal S11 and signal S12. The signal output by the third conversion switch will be incorrect.

[0060] When calculating the above phase difference for the first time, the standard resistance needs to be connected to the measurement loop and the current loop, and the measured product is not connected.

[0061] When the standard resistance is connected to the measurement loop and the current loop, signal Vin is the alternating voltage generated by the current on the standard resistance. If the phase between signal S18 and signal S13 does not match the phase shift introduced by the measurement conditioning circuit, the digital quantity of k*Vin obtained by the processor will be smaller, because there is a phase difference between signal S13 and signal S11 and signal S12. Therefore, when measuring the amplitude of the alternating voltage signal Vin, the processor needs to constantly change the phase delay of the phase modulation circuit until the digital quantity of k*Vin obtained by the processor is the maximum value, at which time the angle between the voltage phase and the current phase is zero. The processor records the phase point corresponding to the phase modulation circuit at this time, and controls the phase modulation circuit to remain at the current phase delay point, and the processor stores the current configuration data of the phase modulation circuit. Because the signal phase shift caused by the conditioning circuit is fixed, the phase modulation circuit only needs to remain at a certain appropriate phase delay point, and the phase shift can be compensated.

[0062] The above adjustment of the phase modulation circuit is only performed when the alternating resistance tester is used for the first time, or manually controlled by the human-computer interaction module according to the user's needs.

[0063] One of the current input terminals C+ is used to connect the input terminal of the measured product through the first switch K1, and the other is connected to the input terminal of the standard resistance through the fifth switch K5.

[0064] The output terminal of the measured product is connected to the current output terminal C- through the third switch K3, and the output terminal of the standard resistance is connected to the current output terminal C- through the seventh switch K7.

[0065] One of the measurement positive terminals S+ is connected to the input terminal of the measured product through the second switch K2, and the other is connected to the input terminal of the standard resistance through the sixth switch K6.

[0066] Switches K1, K2, K3, K4, K5, K6, K7 and K8 are switches controlled by the processor, and have very low on-resistance, which can be ignored. The common connection point of switches K1 and K5 is defined as point A, the common connection point of switches K2 and K6 is defined as point B, the common connection point of switches K3 and K7 is defined as point C, and the common connection point of switches K4 and K8 is defined as point D. Switches K1, K2, K3 and K4 are simultaneously turned on or turned off; switches K5, K6, K7 and K8 are simultaneously turned on or turned off; the standard resistor and the measured product are connected to the system at different times.

[0067] The output end of the measured product is connected to the measurement negative end S- through the fourth switch K4, and the output end of the standard resistor is connected to the measurement negative end S- through the eighth switch K8.

[0068] In the default state, the control switches K1, K2, K3 and K4 are turned on, and the control switches K5, K6, K7 and K8 are turned off.

[0069] When the system measures the measured product, the processor controls the state of the control signal CTRL2, so that the control switches K5, K6, K7 and K8 are kept turned off, and the control switches K1, K2, K3 and K4 are kept turned on. The measured product is connected to points A, B, C and D through the turned-on switches.

[0070] Before the system starts to measure the measured product, the processor controls the switches K1, K2, K3 and K4 to be turned off through the signal CTRL2, and controls the switches K5, K6, K7 and K8 to be turned on. The standard resistor is connected to points A, B, C and D through the turned-on switches.

[0071] When the system is ready to measure the measured product, the processor changes the state of the control signal CTRL2 to control the switches K5, K6, K7 and K8 to be turned off, and controls the switches K1, K2, K3 and K4 to be turned on. The measured product is connected to points A, B, C and D through the turned-on switches.

[0072] In some embodiments, the enable end of the counter is connected to the processor, and the interference suppression circuit further comprises:

[0073] A human-computer interaction module for receiving a user input interference suppression start command and sending it to the processor.

[0074] The processor generates an enable signal to control the start state of the counter according to the interference suppression start command.

[0075] The human-machine interface module receives an interference suppression enable command and transmits the corresponding instruction to the processor via signal S10. The processor changes the state of control signal CTRL3, which generates a corresponding control signal CTRL4 via a high-speed optocoupler. Control signal CTRL4 enables the counter. The processor outputs signal CTRL5 containing information about the calculation period T. Signal CTRL5 generates a corresponding control signal CTRL6 via a high-speed optocoupler, and the counter starts counting based on the calculation period T information contained in signal CTRL6. The state of output signal S29 is changed every half of the processor's calculation period T. That is, the second switching switch changes its state every 0.5T time interval, signal S30 is inverted every 0.5T time interval, and due to the virtual short concept of the operational amplifier circuit, the phase of the current I flowing through the sampling resistor is inverted every 0.5T time interval. At the same time, signal S32 is also inverted every 0.5T time interval along with signal S30.

[0076] Even if the current reverses, there is no need to readjust the phase modulation circuit, because the phase shift caused by the conditioning circuit is fixed.

[0077] When the current I reverses phase, the phase of the AC voltage Vin generated by the current I on the measured object also reverses phase. Since the interference signal Ven is externally introduced interference, when the phase of the system AC voltage Vin reverses phase, the phase of the interference signal Ven does not reverse. Figure 3 As shown, at time 0.5T, the current I reverses phase, and the signals Vin and the third transfer switch control signal S13 also reverse phase. The switching state of the third transfer switch and the phase of the signal Vin both change in opposite directions simultaneously. Therefore, the relationship between the switching state of the third transfer switch and the signal Vin is essentially unchanged. The waveform of the useful signal component output by the third transfer switch (referring to the component related to the useful signal k*Vin) remains unchanged before and after time 0.5T. However, since the phase of the interference signal Ven does not reverse, the interference waveform output by the third transfer switch (referring to the component related to the interference k*Ven) reverses phase before and after time 0.5T. k is the gain of the conditioning circuit. After passing through low-pass filter 2, the useful signal output by the third transfer switch becomes a useful DC signal greater than 0. After passing through low-pass filter 2, the interference signal output by the third transfer switch is a interference DC signal greater than 0 in the first 0.5T period and a interference DC signal less than 0 in the second 0.5T period, with the absolute values ​​of their amplitudes being equal. Signal S16 is the superposition of the useful DC signal and the interference DC signal. Signal S17 is the digital quantity output by the analog-to-digital converter after signal S16 passes through it.

[0078] In some embodiments, the voltage signal source includes a voltage source, a first inverter, a first inverter, a first changeover switch, and a switch control module.

[0079] The voltage source is used to output a voltage signal. The first homodyne amplifier receives the voltage signal output by the voltage source and outputs a homodyne amplified signal. The first inverter receives the voltage signal output by the voltage source and outputs an inverted amplified signal.

[0080] The common terminal of the first switch is an output terminal. The two movable points of the first switch are connected to the output terminals of the first homodyne amplifier and the first inverter, respectively.

[0081] The switch control module is used to output a switch control signal with a frequency of fa to the first switch, so as to control the first switch to switch the gating state according to the frequency fa.

[0082] In some embodiments, the switch control module includes a crystal oscillator and a frequency divider.

[0083] The crystal oscillator has high stability and is used to generate a high-frequency signal S20.

[0084] The frequency divider receives the high-frequency signal S20 and divides the frequency according to the frequency fa, and outputs a control signal with a frequency of fa to the first switch.

[0085] The frequency divider is used to divide the high-frequency signal S20 generated by the crystal oscillator, and the frequency of the output signal S24 of the frequency divider is fa. The signal S24 controls the first switch to switch the switch state according to the frequency fa, and the two input terminals of the first switch are connected to the same output terminal of the first switch in time.

[0086] In some embodiments, the first homodyne amplifier and the first inverter are composed of an operational amplifier circuit.

[0087] The second homodyne amplifier and the second inverter are composed of an operational amplifier circuit.

[0088] The counter has an enable pin. The counter is used to count half of the calculation period of the processor, and the state of the output signal S29 is changed once every half calculation period.

[0089] The switch state of the second switch is controlled by the signal S29. When the signal S29 is in a high impedance state, the second switch has a default conductive state.

[0090] The first low-pass filter is a multi-order filter with a capacitive coupling output.

[0091] The operational amplifier circuit is composed of an operational amplifier, a capacitor and a resistor.

[0092] The zero-crossing comparator is composed of a high-speed comparator.

[0093] The power amplifier is composed of a transistor.

[0094] The sampling resistor is a precision resistor.

[0095] The high-speed isolator has a very high bandwidth, which is sufficient to transmit the signal S32, the signal CTRL3 and the signal CTRL5 with negligible time delay.

[0096] The phase modulation circuit is used to adjust the phase of the signal S18. The phase modulation circuit has a register, which can change the time delay between the input signal and the output signal under the control of the processor, so that a controllable phase difference occurs between the input signal S18 and the output signal S13. The phase difference is used to compensate for the phase shift caused by the conditioning circuit.

[0097] The amplification circuit is composed of a band-pass amplifier, which is used to suppress the interference outside the passband and amplify the to-be-tested signal Vin. The interference voltage signal Ven is also amplified.

[0098] The third homodyne and the third anti-homodyne are composed of the operational amplifier circuit.

[0099] The second low-pass filter is used to realize low-pass filtering, so that the output waveform is smoother.

[0100] The analog-to-digital converter converts the analog signal into a digital signal S17.

[0101] The processor processes the digital signal S17 according to the calculation period. The processor sends the control signal CTRL1, the control signal CTRL2, the control signal CTRL3 and the control signal CTRL5.

[0102] Of course, the above description is not a limitation of the present application, and the present application is not limited to the above examples. Changes, modifications, additions or replacements made by ordinary skilled in the art within the scope of the present application should also be within the protection scope of the present application.

Claims

1. An interference rejection circuit for AC measurements, characterized by The current loop and the measurement loop are included; The current loop includes: a voltage signal source for outputting a voltage signal with a frequency of fa; a first inverter circuit for receiving and amplifying the output signal of the voltage signal source and inverting and outputting the signal according to a set period; the measured product is connected between the first inverter circuit and the ground terminal; The measurement loop includes: a second inverter circuit for receiving and amplifying the measurement signal between the two terminals of the measured product and inverting and outputting the signal according to the frequency fa and the set period; a second low-pass filter connected to the output terminal of the second inverter circuit, the interference signal is an external interference, which is only inverted once by the second inverter circuit, the interference signal output by the second inverter circuit is positive for one set period and negative for one set period, and the processor averages the signal as a calculation period for two set periods, so that the useful signal is retained and the interference component is eliminated; an analog-to-digital converter connected to the output terminal of the second low-pass filter for converting the signal output by the second low-pass filter into digital signal and sending it to the processor; The current loop further includes: a power amplifier for receiving and power amplifying the signal output by the first low-pass filter and outputting a current I to the current input terminal C+, one of the two terminals of the measured product being connected to the current input terminal C+ and the current output terminal C- respectively, and the current output terminal C- being connected to the ground terminal; The interference suppression circuit further includes: a standard resistor, one of the two terminals of the standard resistor being connected to the current input terminal C+ and the current output terminal C- through a switch respectively, and the other terminal being connected to the measurement positive terminal S+ and the measurement negative terminal S- of the measurement loop through a switch respectively, one of the two terminals of the measured product being connected to the current input terminal C+ and the current output terminal C- through a switch respectively, and the other terminal being connected to the measurement positive terminal S+ and the measurement negative terminal S- of the measurement loop through a switch respectively, the on-off state of the switch being controlled by the processor, for connecting the standard resistor to the current loop and the measurement loop, or connecting the measured product to the current loop and the measurement loop, when the standard resistor is connected to the current loop and the measurement loop, the processor generates a phase modulation control signal according to the received signal; an operational amplifier circuit, the same input terminal of the operational amplifier circuit receiving the signal output by the first inverter circuit, the output terminal of the operational amplifier circuit being connected to the input terminal of the power amplifier; a sampling resistor, one terminal of the sampling resistor being connected to the current output terminal C-, and the other terminal being connected to the ground terminal, the sampling resistor outputting a sampling signal to the opposite input terminal of the operational amplifier circuit; a phase shift compensation circuit, receiving the signal output by the first low-pass filter, performing zero-crossing detection on the signal to generate a square wave signal, and delaying the phase of the square wave signal according to the phase modulation control signal, the delayed signal being used to control the inverting and outputting of the second inverter circuit.

2. The interference rejection circuit of claim 1, wherein The first inverter circuit includes: a second same input terminal for receiving and amplifying the voltage signal output by the voltage signal source and outputting the signal in the same direction; a second inverter receiving the voltage signal outputted by the voltage signal source and outputting a signal after inverting amplification; a second switch having an output terminal as a common terminal and having two movable terminals connected to output terminals of the second same-phase amplifier and the second inverting amplifier respectively; a counter receiving a control signal containing information of a calculation period T outputted by the processor and counting according to the control signal, the counter changing the state of an output signal once every T / 2, the output signal of the counter being used to control the gating state of the second switch; the interference suppression circuit further comprises: a first low-pass filter receiving a signal outputted by the second switch and outputting a signal after low-pass filtering.

3. The interference rejection circuit of claim 1, wherein the phase shift compensation circuit comprises: a zero-crossing comparator having an input terminal connected to an output terminal of the first low-pass filter and outputting a square wave signal after zero-crossing detection of the received signal; a phase modulation circuit receiving the square wave signal and a phase modulation control signal, delaying the phase of the square wave signal according to the phase modulation control signal, and having an output terminal connected to a control terminal of the second flip-flop circuit.

4. The interference rejection circuit of claim 3, wherein the second flip-flop circuit comprises: an amplification circuit having two input terminals connected to a measurement positive terminal S+ and a measurement negative terminal S- respectively; a third same-phase amplifier receiving a signal outputted by the amplification circuit and outputting a signal after same-phase amplification; a third inverting amplifier receiving a signal outputted by the amplification circuit and outputting a signal after inverting amplification; a third switch having an output terminal as a common terminal and having two movable terminals connected to output terminals of the third same-phase amplifier and the third inverting amplifier respectively, and having a control terminal connected to an output terminal of the phase modulation circuit.

5. The interference rejection circuit of claim 1, wherein, the voltage signal source comprises: a voltage source for outputting a voltage signal; a first same-phase amplifier receiving a voltage signal outputted by the voltage source and outputting a signal after same-phase amplification; a first inverting amplifier receiving a voltage signal outputted by the voltage source and outputting a signal after inverting amplification; a first switch having an output terminal as a common terminal and having two movable terminals connected to output terminals of the first same-phase amplifier and the first inverting amplifier respectively; a switch control module for outputting a switch control signal with a frequency of fa to the first switch to control the first switch to switch the gating state according to the frequency fa.

6. The interference rejection circuit of claim 5, wherein, the switch control module comprises: a crystal oscillator for generating a high-frequency signal S20; a frequency divider receiving the high-frequency signal S20 and dividing the frequency according to the frequency fa to output a control signal with the frequency of fa to the first switch.

7. The interference rejection circuit of Claim 2, wherein, the counter has an enable terminal connected to the processor, and the interference suppression circuit further comprises: a human-computer interaction module for receiving a user inputted interference suppression start command and sending the interference suppression start command to the processor; the processor generates an enable signal to control the start state of the counter according to the interference suppression start command.

8. The interference suppression circuit according to any one of claims 1-7, wherein one of the current input terminals C+ is connected to an input terminal of a measured product through a first switch K1, and the other is connected to an input terminal of a standard resistor through a fifth switch K5. The output end of the measured product is connected to the current output end C- through the third switch K3, and the output end of the standard resistance is connected to the current output end C- through the seventh switch K7; The positive end S+ is measured, one way of which is connected to the input end of the measured product through the second switch K2, and the other way is connected to the input end of the standard resistance through the sixth switch K6; The output end of the measured product is connected to the negative end S- through the fourth switch K4, and the output end of the standard resistance is connected to the negative end S- through the eighth switch K8.

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