Dimming device and dimming method

Abstract

The invention relates to a dimming apparatus and a dimming method. The dimming device is provided with a dimming layer, a plurality of first electrodes, a plurality of second electrodes, a row driving circuit, a column driving circuit and a control circuit. The dimming layer has a first main surface and a second main surface. The second main surface is disposed on the opposite side from the first main surface. Each of the plurality of first electrodes extends in a row direction. The plurality of first electrodes face the first main surface. Each of the plurality of second electrodes extends in the column direction. The plurality of second electrodes are opposite to the second main surface. The row driving circuit can apply a voltage to the first electrode. The column drive circuit can apply a voltage to the second electrode. The control circuit adjusts the timing of either the voltage applied to the first electrode by the row drive circuit or the voltage applied to the second electrode by the column drive circuit.

Description

Technical Field

[0001] The present disclosure relates to a dimming device and a dimming method. Background Art

[0002] The dimming device can transmit or attenuate external light from the back surface.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-162262 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] The present disclosure provides a dimming device and a dimming method capable of improving dimming performance.

[0008] Solutions for solving problems

[0009] The dimming device disclosed herein comprises a dimming layer, a plurality of first electrodes, a plurality of second electrodes, a row drive circuit, a column drive circuit, and a control circuit. The dimming layer comprises a first main surface and a second main surface. The second main surface is arranged on a side opposite to the first main surface. Each of the plurality of first electrodes extends in a row direction. The plurality of first electrodes face the first main surface. Each of the plurality of second electrodes extends in a column direction. The plurality of second electrodes face the second main surface. The row drive circuit is capable of applying a voltage to the first electrodes. The column drive circuit is capable of applying a voltage to the second electrodes. The control circuit adjusts the timing of applying either the voltage applied by the row drive circuit to the first electrodes or the voltage applied by the column drive circuit to the second electrodes.

[0010] Effects of the Invention

[0011] According to the dimming device and dimming method involved in the present disclosure, the dimming performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram showing a schematic configuration of a light control device according to an embodiment.

[0013] Figure 2 It is a perspective view showing the structure of a dimming panel in an embodiment.

[0014] Figure 3 It is a plan view showing a plurality of areas divided in the dimming panel in the embodiment.

[0015] Figure 4 Graphs showing characteristics of the light-adjusting liquid crystal in the embodiment.

[0016] Figure 5 This is a block diagram showing the configuration of a calculation circuit in the embodiment.

[0017] Figure 6 1 is a diagram showing calculation of load amount in the embodiment.

[0018] Figure 7 It is a diagram showing an estimate of the delay amount in the embodiment.

[0019] Figure 8 This is a block diagram showing the configuration of a column electrode driver circuit (or a row electrode driver circuit) in an embodiment.

[0020] Figure 9 This is a block diagram showing the configuration of a delay amount selection circuit in an embodiment.

[0021] Figure 10 3 is a waveform diagram showing the operation of the delay amount selection circuit in the embodiment.

[0022] Figure 11 3 is a waveform diagram showing changes in the voltage applied to the light-adjusting layer in the embodiment.

[0023] Figure 12 It is a diagram showing an estimate of the delay amount in the first modified example of the embodiment.

[0024] Figure 13 This is a block diagram showing the configuration of a column electrode driver circuit (or a row electrode driver circuit) in a second modified example of the embodiment.

[0025] Figure 14 : is a circuit diagram showing the configuration of a delay amount selection circuit in a second modified example of the embodiment.

[0026] Figure 15 3 is a waveform diagram illustrating the operation of the delay amount selection circuit in the second modified example of the embodiment.

[0027] Figure 16 This is a block diagram showing the configuration of a column electrode driver circuit (or a row electrode driver circuit) in a third modified example of the embodiment.

[0028] Figure 17 3 is a waveform diagram showing the operation of the current detection circuit and the AD conversion circuit in the third modified example of the embodiment. DETAILED DESCRIPTION

[0029] Below, with reference to the attached Figure 1 Embodiments of the dimming device according to the present disclosure will be described.

[0030] (Implementation Method)

[0031] The dimming device according to the embodiment can transmit or attenuate external light from the rear surface, but a method for improving the dimming performance is implemented.

[0032] The dimming device 1 can be used as Figure 1 As shown. Figure 1 2 is a block diagram showing the structure of the dimming device 1 .

[0033] The light control device 1 can perform light control in a two-dimensional manner by transmitting or attenuating external light from the rear surface.

[0034] In this specification, the state in which the dimming device transmits external light is referred to as the "on" state, and the state in which the dimming device attenuates external light is referred to as the "off" state. Attenuating external light can also be referred to as "shielding." Furthermore, when a portion of a dimming device transmits external light, this portion is sometimes referred to as the "on" state, and this portion is referred to as the "transmitting region." Similarly, when a portion of a dimming device attenuates external light, this portion is sometimes referred to as the "off" state, and this portion is referred to as the "shielding region."

[0035] In this specification, “electrically connected” between a first element and a second element includes connection with a third element interposed therebetween within a range that does not hinder the functions of the first element and the second element.

[0036] The dimming device 1 is communicatively connected to an analysis device 201. The analysis device 201 receives dimming-related requests from a higher-level controller. These requests may be, for example, requests for the illumination distribution of external light or requests for the two-dimensional positions of areas to be shielded. The analysis device 201 analyzes the dimming requests, generates a dimming signal based on the analysis results, and supplies the dimming signal to the dimming device 1. The dimming device 1 has multiple areas to be dimmed, and can determine whether each of the multiple areas should be set as a transmissive area or a light-blocking area based on the dimming signal.

[0037] The dimming device 1 includes a dimming panel 2 , a row electrode driving circuit 3 (an example of a row driving circuit), a column electrode driving circuit 4 (an example of a column driving circuit), an arithmetic circuit 5 (an example of a control circuit), a reference voltage generating circuit 6 , and a timing generating circuit 7 .

[0038] like Figure 2 As shown, the dimming panel 2 includes a dimming layer 21 , a plurality of column electrodes EY1 - EY8 (an example of a second electrode), and a plurality of row electrodes EX1 - EX4 (an example of a first electrode). Figure 2 2 is a perspective view showing the structure of the dimming panel 2. Figure 2In FIG, the direction perpendicular to the surface of the dimming panel 2 is set as the Z direction, the long side direction of the dimming panel 2 is set as the X direction, and the direction perpendicular to the X direction and the Z direction is set as the Y direction. Figure 2 In the example, eight column electrodes EY1 to EY8 are shown, but the number of column electrodes EY may be 2 to 7, or may be 9 or more. Figure 2 Although four row electrodes EX1 to EX4 are shown in the example, the number of row electrodes EX may be 2 to 3, or may be 5 or more.

[0039] The dimming layer 21 extends in a roughly plate-like shape in the XY directions. The dimming layer 21 can also be constructed by enclosing a dimming liquid crystal 21b within a box-shaped member 21a. The dimming layer 21 has a front surface on the +Z side and a back surface on the -Z side. The +Z side surface of the box-shaped member 21a can constitute the front surface of the dimming layer 21, while the -Z side surface of the member 21a can constitute the back surface of the dimming layer 21.

[0040] The column electrodes EY1 to EY8 are arranged on the +Z side of the light-adjusting layer 21. Alternatively, the column electrodes EY1 to EY8 may be arranged on a substrate 22, which is arranged on the front surface of the light-adjusting layer 21. The substrate 22 may be bonded to the front surface of the light-adjusting layer 21 using an adhesive or other means. The substrate 22 extends in a plate-like shape in the X and Y directions. Each column electrode EY can be formed from a transparent conductive material such as ITO. The substrate 22 can also be formed from a transparent insulating resin or other material.

[0041] On the substrate 22, the column electrodes EY1 to EY8 are insulated from each other by insulating portions 22a and 22b, and are arranged along the X direction. Consequently, the column electrodes EY1 to EY8 are arranged along the X direction along the front surface of the light-adjusting layer 21. On the substrate 22, each column electrode EY extends along the Y direction. The insulating portion 22a extends along the Y direction between the column electrodes EY1 to EY8. The insulating portion 22b extends along the X direction and connects the +Y-side ends of the insulating portions 22a.

[0042] The plurality of row electrodes EX1 to EX4 are arranged on the -Z side of the dimming layer 21. Alternatively, the plurality of row electrodes EX1 to EX4 can be arranged on a substrate 23, which is arranged on the back side of the dimming layer 21. The plurality of row electrodes EX1 to EX4 face the plurality of column electrodes EY1 to EY8, with the dimming layer 21 positioned between them. The substrate 23 can also be bonded to the back side of the dimming layer 21 using an adhesive or other means. The substrate 23 extends in a plate-like shape in the XY directions. Each row electrode EX can be formed from a transparent conductive material such as ITO. The substrate 23 can be formed from a transparent insulating resin or other material.

[0043] On the substrate 23, the row electrodes EX1 to EX4 are insulated from each other by insulating portions 23a and 23b. The row electrodes EX1 to EX4 are arranged along the Y direction. Consequently, the row electrodes EX1 to EX4 are arranged along the Y direction along the back surface of the light-adjusting layer 21. On the substrate 23, each row electrode EX extends along the X direction. The insulating portion 23a extends along the X direction between the row electrodes EX1 to EX4. The insulating portion 23b extends along the Y direction and connects the +X-side ends of the insulating portions 23a.

[0044] In the dimming layer 21, the plurality of column electrodes EY1 to EY8 and the plurality of row electrodes EX1 to EX4 are divided into Figure 3 As shown, there are multiple regions R(1,1) to region R(8,4). Figure 3 It is a plan view showing a plurality of regions R( 1 , 1 ) to R( 8 , 4 ) divided in the light control panel 2 .

[0045] The light-adjusting layer 21 includes a plurality of regions R(1,1) to R(8,4) divided into a matrix. Each row extends in the X direction, and each column extends in the Y direction. The X direction can also be referred to as the row direction, and the Y direction can be referred to as the column direction.

[0046] Region R(1,1) is formed in the light-adjusting layer 21 at a position where the column electrode EY1 intersects the row electrode EX1 when viewed from the Z direction. A voltage is applied to region R(1,1) from the column electrode EY1 on the +Z side and from the row electrode EX1 on the -Z side.

[0047] Region R(2,1) is formed in the light-adjusting layer 21 at a position where the column electrode EY2 intersects the row electrode EX1 when viewed from the Z direction. A voltage is applied to region R(2,1) from the column electrode EY2 on the +Z side and from the row electrode EX1 on the -Z side.

[0048] Region R(8,4) is formed in the light-adjusting layer 21 at a position where the column electrode EY8 intersects the row electrode EX4 when viewed from the Z direction. A voltage is applied to region R(8,4) from the column electrode EY8 on the +Z side and from the row electrode EX4 on the -Z side.

[0049] The dimming device 1 can control the on / off states of multiple regions R(1,1) to R(8,4). The regions R controlled to be on can also be referred to as transmissive regions. The regions R controlled to be off can also be referred to as light-blocking regions.

[0050] exist Figure 3 In the process, the row electrode driving circuit 3 applies voltages V to the row electrodes EX1, EX2, EX3, and EX4 respectively. A 、VB 、V B 、V A The column electrode driving circuit 4 applies a voltage V to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, EY7, and EY8, respectively. C 、V B 、V B 、V C 、V C 、V B 、V C 、V A Voltage V A 、V B 、V C They can also be different from each other.

[0051] Therefore, the dimming device 1 applies substantially the same voltage to both ends of the Z direction for region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) among the multiple regions R(1,1) to R(8,4). If substantially the same voltage is applied to both ends of the Z direction, then Figure 3 As shown in the example, it is possible to realize a shading pattern by selectively setting region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) in the dimming layer 21 to a closed state.

[0052] For example, a display for displaying images requires high contrast, and STN (Super Twisted Nematic) liquid crystal can be used, which can be used together with a polarizing plate to ensure contrast.

[0053] On the other hand, for the dimming device 1, achieving high transmittance in the on state, which allows external light to pass through, is beneficial. Therefore, the dimming layer 21 of the dimming panel 2 can utilize dimming liquid crystals 21b, which can ensure high transmittance without requiring a polarizer. The dimming liquid crystals 21b include GH (Guest Host) liquid crystals. GH liquid crystals can also be obtained by adding a dichroic dye to a twisted liquid crystal material. Dichroic dyes are pigments with anisotropic absorption properties.

[0054] For example, regarding each of the dimming liquid crystal (eg, GH liquid crystal) 21b and the STN liquid crystal, the transmittance variation characteristics with respect to the applied voltage are as follows: Figure 4 Like that. Figure 4In the figure, the vertical axis represents the magnitude of transmittance, which is the relative value when the transmittance in the on state is equal. The horizontal axis represents the magnitude of the effective voltage applied to the liquid crystal.

[0055] exist Figure 4 In the figure, the solid line shows the change characteristics when the dimming liquid crystal 21b is a GH liquid crystal, and the dotted line shows the change characteristics of an STN liquid crystal as a comparative example. The change characteristics of both the dimming liquid crystal 21b and the STN liquid crystal show an example of a normally black mode in which the transmittance is low when the effective voltage is low.

[0056] The transmittance of the dimming liquid crystal 21b changes more gradually with the applied effective voltage than the STN liquid crystal. For any liquid crystal material, for example, the minimum applied voltage that makes the transmittance almost maximum, that is, the turn-on voltage, is set to voltage V A For STN liquid crystal, the maximum applied voltage that makes the transmittance smaller than the threshold value Tth, that is, the off voltage, is V A Slightly lower voltage V B On the other hand, for GH liquid crystal, the voltage V A Significantly lower voltage V C .

[0057] When the dimming device 1 applies voltages with substantially equal amplitude but shifted timing to both ends of the light shielding regions R in the Z direction of the dimming layer 21, it is possible that a voltage exceeding V C As a result, dimming performance may temporarily deteriorate.

[0058] Therefore, in this embodiment, the dimming device 1 improves the dimming performance by adjusting the timing of either the voltage applied by the row electrode driving circuit 3 to the row electrode EX or the voltage applied by the column electrode driving circuit 4 to the column electrode EY.

[0059] In the dimming device 1, the calculation circuit 5 estimates the respective delay amounts of the row electrode driver circuit 3 and the column electrode driver circuit 4, and adjusts the row control signal and the column control signal based on the estimated delay amounts before supplying them to the row electrode driver circuit 3 and the column electrode driver circuit 4. Thus, the calculation circuit 5 adjusts the timing of either the voltage applied to the row electrode by the row electrode driver circuit 3 or the voltage applied to the column electrode by the column electrode driver circuit 4. The calculation circuit 5 may also delay the timing of the voltage applied to the row electrode by the row electrode driver circuit 3 or the voltage applied to the column electrode by the column electrode driver circuit 4, whichever has a smaller delay relative to the reference timing. The reference timing may also be the edge timing of the timing signal generated by the timing generation circuit 7. The edge timing may be either the timing of a rising edge or the timing of a falling edge.

[0060] The operation circuit 5 can be Figure 5 As shown. Figure 5 : is a block diagram showing the configuration of the arithmetic circuit 5 .

[0061] The arithmetic circuit 5 includes a selection signal generating circuit 51 , a load amount calculating circuit 52 , and a delay amount generating circuit 53 .

[0062] The selection signal generation circuit 51 receives a dimming signal from the analysis device 201. Multiple applied waveform signals are pre-set in the dimming device 1. Alternatively, multiple applied waveform signals may be pre-set in the selection signal generation circuit 51, the row electrode driver circuit 3, and the column electrode driver circuit 4. The dimming signal includes an instruction for specifying which of the multiple applied waveform signals should be supplied to the multiple column electrodes EY1 to EY8, and an instruction for specifying which of the multiple applied waveform signals should be supplied to the multiple row electrodes EX1 to EX4. The selection signal generation circuit 51 generates a column control signal corresponding to the dimming signal in synchronization with a clock signal and supplies the column control signal to the column electrode driver circuit 4. It also generates a row control signal corresponding to the dimming signal and supplies the row control signal to the row electrode driver circuit 3. The column control signal includes an instruction for the voltage waveform to be supplied to each column electrode EY. The row control signal includes an instruction for the voltage waveform to be supplied to each row electrode EX. A signal including the row control signal and the column control signal may also be referred to as an applied waveform selection signal.

[0063] The load calculation circuit 52 receives the dimming signal from the analysis device 201 and the row control signal and the column control signal from the selection signal generation circuit 51. The load calculation circuit 52 determines a light shielding pattern for each time zone based on the dimming signal, the row control signal, and the column control signal, and calculates the load of the voltage supply to each light shielding area R based on the light shielding pattern.

[0064] For example, the load applied by the row electrodes EX to each light-shielding region R is determined by the load generated by the parasitic resistance component of the row electrodes EX and the load generated by the parasitic capacitance component formed between the row electrodes EX and the column electrodes EY. Because a higher voltage is applied between the row electrodes EX and the column electrodes EY in the transmissive regions R than in the light-shielding regions R, the load in the transmissive regions R is considered to be relatively greater. Taking this into account, the load can be generally calculated using the following equation 1. The load is a numerical value used to relatively grasp the magnitude of the load.

[0065] [Load amount generated by row electrode EX] = [Number of transmissive areas of row electrode EX from the input end to the current light-shielding area] + [Number of transmissive areas of row electrode EX from the current light-shielding area to the far end] / 4 ... Formula 1

[0066] exist Figure 3In the shading pattern shown, the equation 1 can be used as Figure 6 As shown in (a), the load of each light-shielding area R generated by the row electrode EX is estimated. Figure 6 1 is a diagram illustrating load calculation. Load calculation circuit 52 calculates the loads generated by row electrodes EX in regions R(8,1), R(2,2), R(3,2), R(6,2), R(2,3), R(3,3), R(6,3), and R(8,4) as 7, 2, 2, 3.5, 2, 2, 3.5, and 7, respectively.

[0067] Similarly, the load applied by the column electrode EY to each light-shielding region R is determined by the load generated by the parasitic resistance component of the column electrode EY and the load generated by the parasitic capacitance component formed between the column electrode EY and the row electrode EX. Because a higher voltage is applied between the column electrode EY and the row electrode EX in the light-shielding region R than in the light-shielding region R, the load in the light-shielding region R is considered to be relatively greater. Taking this into account, the load can be generally calculated using the following equation 2. The load is a numerical value used to relatively grasp the magnitude of the load.

[0068] [Load amount generated by the column electrode EY] = [Number of transmissive areas of the column electrode EY from the input end to the current light-shielding area] + [Number of transmissive areas of the column electrode EY from the current light-shielding area to the far end] / 4 ... Formula 2

[0069] exist Figure 3 In the shading pattern shown, the formula 2 can be used as follows Figure 6 The load amount of each light-shielding region R generated by the column electrode EY is estimated as shown in (b). The load amount calculation circuit 52 calculates the load amounts generated by the column electrode EY in region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) as 0.5, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, and 2, respectively.

[0070] The load difference between both ends of each light-shielding region R in the Z direction can be obtained as the difference between the load generated by the row electrode EX and the load generated by the column electrode EY, as shown in the following formula 3.

[0071] [Load difference at both ends in the Z direction] = [Load generated by the row electrode EX] - [Load generated by the column electrode EY] ... Formula 3

[0072] exist Figure 3 In the shading pattern shown, the equation 3 can be used as follows Figure 6The load difference at both ends in the Z direction is estimated as shown in (c). The load calculation circuit 52 calculates the load difference at both ends in the Z direction of region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) as 6.5, 0.75, 0.75, 2.25, 0.75, 0.75, 2.25, and 5, respectively.

[0073] The load calculation circuit 52 supplies the calculation result of the load difference between both ends in the Z direction to the delay generation circuit 53 as a load signal.

[0074] The delay amount generating circuit 53 receives the load amount signal. The load amount signal includes information corresponding to the row position and column position of the light shielding area R and the load amount difference at both ends in the Z direction for the plurality of light shielding areas R. The load amount signal may also include Figure 6 The delay generation circuit 53 calculates the delay to be added to the voltage supply to each light-shielding region R based on the load signal. The delay generation circuit 53 may also calculate the delay to delay the timing of the voltage applied by the row electrode driver circuit 3 to the row electrode EX or the voltage applied by the column electrode driver circuit 4 to the column electrode EY, whichever has a smaller delay relative to the reference timing.

[0075] exist Figure 3 In the shading pattern shown, if Figure 6 (a) and Figure 6 As compared with (b), for any shading area R, the load generated by the column electrode EY is less than the load generated by the row electrode EX, so it is expected that the delay of the voltage applied by the column electrode driving circuit 4 to the column electrode EY is less than the delay of the voltage applied by the row electrode driving circuit 3 to the row electrode EX.

[0076] Therefore, the delay amount generating circuit 53 delays the column control signal instead of the row control signal so that the load amount difference between both ends in the Z direction approaches zero.

[0077] like Figure 7 As shown in (a), the delay amount generating circuit 53 makes the delay amount added to the voltages applied to the row electrodes EX1, EX2, EX3, and EX4 zero. As a result, the voltages applied to the row electrodes EX1, EX2, EX3, and EX4 are V A 、V B 、V B 、V A .

[0078] like Figure 7As shown in (b), the delay amount generating circuit 53 adds delay amounts of 0, 0.75, 0.75, 0, 0, 2.25, 0, and 6.5 to the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, EY7, and EY8, respectively. As a result, the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, EY7, and EY8 are V C 、V B +0.75, V B +0.75, V C 、V C 、V B +2.25, V C 、V A +6.5.

[0079] Therefore, if Figure 7 As shown in (c), the load difference at both ends of each light-shielding region R in the Z direction is close to zero. The load differences at both ends of region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) in the Z direction are 0, 0, 0, 0, 0, 0, 0, and -1.5, respectively.

[0080] In addition, Figure 6 and Figure 7 In the example, the delay amount is adjusted so that the load difference at both ends of the light shielding region R in the Z direction where the load difference is large is preferentially approached to zero, but the delay amount may be adjusted so that the total value of the load difference is minimized.

[0081] The delay generation circuit 53 generates a row-side delay selection signal indicating the delay to be added to the row control signal, and supplies the row-side delay selection signal to the row electrode driver circuit 3. The delay generation circuit 53 generates a column-side delay selection signal indicating the delay to be added to the column control signal, and supplies the column-side delay selection signal to the column electrode driver circuit 4. A signal including the row-side delay selection signal and the column-side delay selection signal may also be referred to as a delay selection signal.

[0082] The arithmetic circuit 5 may be connected to the column electrode driver circuit 4 and the row electrode driver circuit 3 via serial communication lines. The arithmetic circuit 5 may supply the column control signal and the column-side delay amount selection signal to the column electrode driver circuit 4 in the form of serial signals. The arithmetic circuit 5 may also supply the row control signal and the row-side delay amount selection signal to the row electrode driver circuit 3 in the form of serial signals.

[0083] The column electrode driver circuit 4 receives a column control signal and a column-side delay selection signal from the calculation circuit 5. The column electrode driver circuit 4 is electrically connected to the plurality of column electrodes EY1 to EY8. The column electrode driver circuit 4 drives each of the plurality of column electrodes EY1 to EY8 using a reference voltage in synchronization with a clock signal, with a voltage waveform corresponding to the column control signal and the column-side delay selection signal. The column electrode driver circuit 4 can independently drive the plurality of column electrodes EY1 to EY8.

[0084] The column electrode driving circuit 4 can also be Figure 8 As shown, the delay amount is digitally adjusted. Figure 8 4 is a block diagram showing the structure of the column electrode driving circuit 4 (or the row electrode driving circuit 3). Figure 8 While the structure of the column electrode driver circuit 4 is illustrated, the structure of the row electrode driver circuit 3 is similar. The column electrode driver circuit 4 adjusts the delay amount before performing DA conversion. The column electrode driver circuit 4 includes a serial-parallel conversion circuit 41, an applied waveform generation circuit 42, an applied waveform selection circuit 43, a serial-parallel conversion circuit 44, a delay trigger generation circuit 45, a delay amount selection circuit 46, and a DA conversion circuit 47.

[0085] The serial-parallel conversion circuit 41 receives the application waveform selection signal from the arithmetic circuit 5. The serial-parallel conversion circuit 41 converts the application waveform selection signal from serial format to parallel format and supplies the converted application waveform selection signal to the application waveform selection circuit 43. The application waveform generation circuit 42 generates a plurality of application waveform signals and supplies them to the application waveform selection circuit 43. The application waveform selection circuit 43 selects an application waveform signal to be used from the plurality of application waveform signals based on the application waveform selection signal.

[0086] The serial-parallel conversion circuit 44 receives the delay amount selection signal from the arithmetic circuit 5. The serial-parallel conversion circuit 44 converts the delay amount selection signal from serial format to parallel format and supplies the converted delay amount selection signal to the delay amount selection circuit 46. The delay trigger generation circuit 45 generates a plurality of delay trigger signals and supplies them to the delay amount selection circuit 46. The delay amount selection circuit 46 selects a delay trigger signal to be used from the plurality of delay trigger signals based on the delay amount selection signal.

[0087] The delay amount selection circuit 46 can be as follows Figure 9 As shown. Figure 9 : is a block diagram showing the structure of the delay amount selection circuit 46.

[0088] The delay amount selection circuit 46 includes a selection circuit 461 and a latch circuit 462. The selection circuit 461 receives a plurality of delay trigger signals from the delay trigger generation circuit 45 and receives a delay amount selection signal from the serial-parallel conversion circuit 44.

[0089] Multiple delayed trigger signals can also be Figure 10 As shown, the edge timings of the pulses are different from each other. As for the plurality of delayed trigger signals, the edge timings thereof may each indicate the timing to be delayed. Figure 10 is a waveform diagram showing the operation of the delay amount selection circuit 46. Figure 10 In FIG, four delay trigger signals 0 to 3 are illustrated. The delay amount selection signal is a signal indicating the delay amount to be added. Figure 10 , the case where the delay amount selection signal includes "2" or "1" indicating the delay amount to be added is illustrated.

[0090] Figure 9 The selection circuit 461 shown may also be a multiplexer having a plurality of input nodes corresponding to a plurality of delayed trigger signals and a control node for receiving a delay amount selection signal. The selection circuit 461 selects one of the plurality of delayed trigger signals according to the delay amount selection signal. Figure 10 In the example, the case where the delay amount selection signal includes "2" and the delayed trigger signal 2 is selected from the four delayed trigger signals 0 to 3 is illustrated. Alternatively, the case where the delay amount selection signal includes "1" and the delayed trigger signal 1 is selected from the four delayed trigger signals 0 to 3 is illustrated.

[0091] Figure 9 The selection circuit 461 shown in FIG. 4 supplies the selected delay trigger signal to the latch circuit 462 as a selection trigger signal. Figure 10 , the case where the delayed trigger signal 2 or the delayed trigger signal 1 is supplied to the latch circuit 462 as the selection trigger signal is illustrated.

[0092] Figure 9 The latch circuit 462 shown receives the applied waveform signal from the applied waveform selection circuit 43 and receives the selection trigger signal from the selection circuit 461. The latch circuit 462 delays the timing of the applied waveform signal according to the selection trigger signal. The latch circuit 462 can also be a trigger having a data node D for receiving the applied waveform signal, a clock node CK for receiving the selection trigger signal, and an output node Q. The latch circuit 462 latches the applied waveform signal in synchronization with the rising edge of the selection trigger signal, and outputs the latched applied waveform signal from the output node Q to the DA conversion circuit 47 as a delayed applied waveform signal. Figure 10In the embodiment, the applied waveform signal is a signal that changes synchronously with the timing signal, but the latch circuit 462 latches the applied waveform signal synchronously with the selection trigger signal, thereby resulting in that the change timing of the delayed applied waveform signal is delayed relative to the timing signal.

[0093] thus, Figure 9 The latch circuit 462 shown in FIG. 1 delays the timing of the applied waveform signal to a timing synchronized with the rising edge of the selection trigger signal and outputs it as a delayed applied waveform signal. The DA converter circuit 47 performs DA conversion on the delayed applied waveform signal using a reference voltage to generate an applied analog voltage, which is then applied to the column electrode EY.

[0094] Thus, for example Figure 11 As shown in (b), the variation range ΔV2 of the voltage applied to both ends of the light shielding region R(8,1) in the Z direction can be suppressed to less than Figure 11 The variation range ΔV1 is small when none of the voltages at both ends shown in (a) is delayed. Figure 11 As shown in FIG. 5( b ), the delay time Δt between the edge timing of the voltage applied to the column electrode EY8 and the edge timing of the voltage applied to the row electrode EX1 corresponds to the delay amount 6.5 calculated by the calculation circuit 5 .

[0095] As described above, in this embodiment, the dimming device 1 adjusts the timing of either the voltage applied to the row electrode EX by the row electrode driving circuit 3 or the voltage applied to the column electrode EY by the column electrode driving circuit 4. As a result, the dimming device 1 can stably dim the off region R of the dimming panel 2, thereby improving dimming performance.

[0096] Furthermore, as a first modification of the embodiment, Figure 1 The calculation circuit 5 shown may also advance the timing of the voltage applied to the row electrodes by the row electrode driving circuit 3 or the voltage applied to the column electrodes by the column electrode driving circuit 4 , whichever has a larger delay relative to the reference timing.

[0097] In this case, Figure 5The delay amount generating circuit 53 shown may also have the function of calculating not only the delay amount but also the advance amount. The delay amount generating circuit 53 calculates the delay amount or advance amount to be added to the voltage supplied to each light-shielding region R based on the load amount signal. The delay amount generating circuit 53 may calculate the delay amount to delay the timing of the voltage applied by the row electrode driver circuit 3 to the row electrode EX or the voltage applied by the column electrode driver circuit 4 to the column electrode EY, whichever has a smaller delay relative to the reference timing. It may also calculate the advance amount to advance the timing of the voltage applied by the row electrode driver circuit 3 to the row electrode or the voltage applied by the column electrode driver circuit 4 to the column electrode, whichever has a larger delay relative to the reference timing. It may also calculate both.

[0098] exist Figure 3 In the shading pattern shown, if Figure 6 (a) and Figure 6 , the load generated by the column electrode EY is smaller than the load generated by the row electrode EX in any light-shielding area R. Therefore, the delay amount of the voltage applied to the column electrode EY by the column electrode driver circuit 4 is expected to be smaller than the delay amount of the voltage applied to the row electrode EX by the row electrode driver circuit 3. In other words, the delay amount of the voltage applied to the row electrode EX by the row electrode driver circuit 3 is expected to be greater than the delay amount of the voltage applied to the column electrode EY by the column electrode driver circuit 4.

[0099] Therefore, the delay amount generating circuit 53 advances the row control signal and delays the column control signal so that the load amount difference between both ends in the Z direction approaches zero.

[0100] like Figure 12 As shown in (a), the delay amount generating circuit 53 adds the advance amount to -6.5, 0, 0, and -5 to the voltages applied to the row electrodes EX1, EX2, EX3, and EX4, respectively. A -6.5, V B 、V B 、V A -5.

[0101] like Figure 12 As shown in (b), the delay amount generating circuit 53 adds delay amounts of 0, 0.75, 0.75, 0, 0, 2.25, 0, and 0 to the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, EY7, and EY8, respectively. As a result, the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, EY7, and EY8 are V C 、V B +0.75, V B +0.75, VC 、V C 、V B +2.25, V C 、V A .

[0102] Therefore, if Figure 12 As shown in (c), the difference in load at both ends of each light-shielding region R in the Z direction is close to zero. The total loads of region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) are 0, 0, 0, 0, 0, 0, 0, 0, respectively.

[0103] By combining the delay of the voltage timing with a smaller delay from the reference timing and the advancement of the voltage timing with a larger delay from the reference timing in this manner, the timing adjustment for the dimming panel 2 can be made more accurate.

[0104] Alternatively, as a second variation of the embodiment, the column electrode driving circuit 4i (or the row electrode driving circuit 3i) may also be configured as follows: Figure 13 As shown, the delay amount is adjusted in a simulated manner. Figure 13 : is a block diagram showing the structure of the column electrode driving circuit 4i (or the row electrode driving circuit 3i) in the second modification of the embodiment. Figure 13 In the example, the structure of the column electrode driver circuit 4i is shown, but the structure of the row electrode driver circuit 3i is the same. The column electrode driver circuit 4i (or the row electrode driver circuit 3i) adjusts the delay amount after performing DA conversion.

[0105] The column electrode driving circuit 4i includes a serial-parallel conversion circuit 44i, a delay amount selection circuit 46i, and a DA conversion circuit 47i instead of the serial-parallel conversion circuit 44, the delay amount selection circuit 46, and the DA conversion circuit 47 (see Figure 8 ), and the delayed trigger generating circuit 45 is omitted.

[0106] The DA conversion circuit 47i receives the applied waveform signal from the applied waveform selection circuit 43. The DA conversion circuit 47i performs DA conversion on the applied waveform signal using a reference voltage to generate an applied analog voltage, and supplies the applied analog voltage to the delay amount selection circuit 46i.

[0107] The delay amount selection circuit 46i receives the applied analog voltage from the DA conversion circuit 47i and the delay amount selection signal from the serial-parallel conversion circuit 44i, and adds a delay amount to the applied analog voltage according to the delay amount selection signal.

[0108] The delay amount selection circuit 46i can be as follows Figure 14 As shown. Figure 14 : is a circuit diagram showing the configuration of a delay amount selection circuit 46i in a second modified example of the embodiment.

[0109] Delay selection circuit 46i includes a resistor R1, multiple capacitors C1 to C4, and multiple switches SW1 to SW4. Resistor R1 is electrically connected to signal line SL. Each capacitor C1 to C4 corresponds to a corresponding switch SW1 to SW4. Each capacitor C1 to C4 has one end connected to signal line SL and the other end connected to ground potential via the corresponding switch SW.

[0110] Each switch SW1 to SW4 receives a delay selection signal through a control terminal. Each switch SW1 to SW4 is kept in a closed state to disable the corresponding capacitor element C, thereby reducing the delay of the signal line SL. For example, when all switches SW1 to SW4 are closed, as shown by Figure 15 As shown in the second waveform from the top, a delay amount of zero is added to the applied analog voltage to generate a delayed applied analog voltage, and the delayed applied analog voltage is applied to the column electrode EY. Figure 15 3 is a waveform diagram showing the operation of the delay amount selection circuit 46 i in the second modified example of the embodiment.

[0111] Each switch SW1 to SW4 activates the corresponding capacitor element C by being maintained in the open state, thereby increasing the delay of the signal line SL. For example, when all switches SW1 to SW4 are turned on, as shown by Figure 15 As shown in the third waveform from the top, a desired delay amount is added to the applied analog voltage to generate a delayed applied analog voltage, and the delayed applied analog voltage is applied to the column electrode EY.

[0112] Thus, the delay amount selection circuit 46i can add a delay amount corresponding to the delay amount selection signal to the analog voltage applied via the signal line SL.

[0113] By analogously adjusting the delay amount using the column electrode driving circuit 4 i (or the row electrode driving circuit 3 i ) in this manner, a voltage with a desired delay amount can be applied to each region R of the dimming panel 2 .

[0114] Alternatively, as a third variation of the embodiment, the column electrode driving circuit 4j (or the row electrode driving circuit 3j) may also be configured as follows: Figure 16 As shown, the delay amount selection signal is generated internally. Figure 16 : is a block diagram showing the structure of the column electrode driving circuit 4j (or the row electrode driving circuit 3j) in the third modification of the embodiment. Figure 16While the structure of the column electrode driver circuit 4j is illustrated, the structure of the row electrode driver circuit 3j is also similar. The column electrode driver circuit 4j (or the row electrode driver circuit 3j) performs feedback control by monitoring the current applied to the column electrode EY (or the row electrode EX) and feeding back a delay selection signal based on the monitoring result.

[0115] The column electrode driving circuit 4j further includes a current detection circuit 48j, an AD conversion circuit 49j, and a pulse width counter 50j instead of the components of the column electrode driving circuit 4 (see FIG. Figure 8 ).

[0116] The current detection circuit 48 j monitors the current applied from the DA conversion circuit 47 to the column electrode EY.

[0117] Figure 17 : is a waveform diagram showing the operation of the current detection circuit 48j and the AD conversion circuit 49j in the third modified example of the embodiment. Figure 17 As shown in (a), if the applied current falls between the upper threshold value Ith1 and the lower threshold value Ith2, the current detection circuit 48j generates an excess signal indicating that the applied current exceeds the upper threshold value Ith1 and the lower threshold value Ith2 by zero, and supplies this excess signal to the AD conversion circuit 49j. The AD conversion circuit 49j performs AD conversion on the excess signal to generate an AD conversion circuit output maintained at a zero level, and outputs this AD conversion circuit output to the pulse width counter 50j. The pulse width counter 50j counts zero as the pulse width in the AD conversion circuit output, generates a delay amount selection signal indicating that the delay amount is zero, and supplies this delay amount selection signal to the delay amount selection circuit 46.

[0118] On the other hand, Figure 17As shown in (b), if the applied current does not fall between the upper threshold Ith1 and the lower threshold Ith2, that is, if it exceeds the upper threshold Ith1 and the lower threshold Ith2, the current detection circuit 48j generates an excess signal indicating that the applied current exceeds the upper threshold Ith1 and the lower threshold Ith2 by an amount, and supplies this excess signal to the AD conversion circuit 49j. The excess signal may also be a signal indicating the absolute value of the amount by which the applied current exceeds the upper threshold Ith1 and the lower threshold Ith2. The AD conversion circuit 49j performs A / D conversion on the excess signal to generate an A / D conversion circuit output, which is then output to the pulse width counter 50j. The A / D conversion circuit output includes a pulse having a width corresponding to the time between the applied current exceeding the upper threshold Ith1 and the lower threshold Ith2. The pulse width counter 50j counts the finite value as the pulse width in the A / D conversion circuit output, generates a delay amount selection signal indicating the desired delay amount, and supplies this delay amount selection signal to the delay amount selection circuit 46.

[0119] In this manner, by generating the delay amount selection signal inside the column electrode driving circuit 4 j (or the row electrode driving circuit 3 j ), a voltage to which a desired delay amount is added can be applied to each region R of the dimming panel 2 .

[0120] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are also included within the invention set forth in the claims and their equivalents.

Claims

1. A dimming device comprising: a dimming layer having a first main surface and a second main surface, wherein the second main surface is arranged on a side opposite to the first main surface; a plurality of first electrodes, each of the plurality of first electrodes extending along a row direction and facing the first main surface; a plurality of second electrodes, each of the plurality of second electrodes extending along a column direction and facing the second main surface; a row driving circuit capable of applying a voltage to the first electrode; a column driving circuit capable of applying a voltage to the second electrode; as well as A control circuit adjusts timing of one of a voltage applied by the row driver circuit to the first electrode and a voltage applied by the column driver circuit to the second electrode.

2. The dimming device according to claim 1, wherein: The control circuit delays the timing of the voltage applied by the row driver circuit to the first electrode and the voltage applied by the column driver circuit to the second electrode, the one having a smaller delay amount with respect to a reference timing.

3. The dimming device according to claim 1, wherein: The control circuit advances the timing of the voltage applied by the row driver circuit to the first electrode and the voltage applied by the column driver circuit to the second electrode, the one having a larger delay amount with respect to a reference timing.

4. The dimming device according to claim 2, wherein: The light-adjusting layer has a plurality of regions divided into a matrix according to the voltages of the plurality of first electrodes and the voltages of the plurality of second electrodes. The control circuit determines, for each of the plurality of regions, a voltage applied by the row driving circuit to the first electrode and a voltage applied by the column driving circuit to the second electrode, the voltage having a smaller delay relative to the reference timing, and delays the timing of the determined voltage. The dimming device according to claim 3 , wherein: The light-adjusting layer has a plurality of regions divided into a matrix according to the voltages of the plurality of first electrodes and the voltages of the plurality of second electrodes. The control circuit determines, for each of the multiple areas, the voltage applied by the row driving circuit to the first electrode and the voltage applied by the column driving circuit to the second electrode, the voltage with a larger delay relative to the reference timing, and advances the timing of the determined voltage. The dimming device according to claim 1 , wherein: The light-adjusting layer has a plurality of regions divided into a matrix according to the voltages of the plurality of first electrodes and the voltages of the plurality of second electrodes. The control circuit performs the following processing: receiving a dimming signal including a designation of an applied waveform to be supplied to the first electrode and the second electrode; determining, based on the dimming signal, a pattern of light-shielding areas set to an off state among the plurality of areas, namely, a light-shielding pattern; Calculating a load of voltage supplied to the light-shielding area according to the light-shielding pattern; as well as Based on the load amount, a delay amount to be added to the voltage supply to the light-shielding area is determined.

7. A dimming method performed by a dimming device, the dimming device comprising: a dimming layer having a first main surface and a second main surface, the second main surface being disposed on a side opposite to the first main surface; a plurality of first electrodes, each of the plurality of first electrodes extending in a row direction and facing the first main surface; a plurality of second electrodes, each of the plurality of second electrodes extending along a column direction and facing the second main surface; A row driving circuit capable of applying a voltage to the first electrode; and a column driving circuit capable of applying a voltage to the second electrode. In the dimming method, the following processing is performed: The timing of applying one of the voltage applied by the row driver circuit to the first electrode and the voltage applied by the column driver circuit to the second electrode is adjusted.

8. The dimming method according to claim 7, wherein: The timing adjustment process includes delaying the timing of the voltage applied by the row driver circuit to the first electrode or the voltage applied by the column driver circuit to the second electrode, the one with a smaller delay relative to a reference timing.

9. The dimming method according to claim 7, wherein: The timing adjustment process includes advancing the timing of the voltage applied by the row driver circuit to the first electrode or the voltage applied by the column driver circuit to the second electrode, whichever has a larger delay relative to a reference timing.

10. The dimming method according to claim 8, wherein: The light-adjusting layer has a plurality of regions divided into a matrix according to the voltages of the plurality of first electrodes and the voltages of the plurality of second electrodes. The processing for adjusting the timing includes the following processing: for each of the multiple areas, determining the voltage applied by the row driving circuit to the first electrode and the voltage applied by the column driving circuit to the second electrode, the voltage with a smaller delay relative to the reference timing, and delaying the timing of the determined voltage.

11. The dimming method according to claim 9, wherein: The light-adjusting layer has a plurality of regions divided into a matrix according to the voltages of the plurality of first electrodes and the voltages of the plurality of second electrodes. The processing for adjusting the timing includes the following processing: for each of the multiple areas, determining the voltage applied by the row driving circuit to the first electrode and the voltage applied by the column driving circuit to the second electrode, the voltage with a larger delay relative to the reference timing, and advancing the timing of the determined voltage.

12. The dimming method according to claim 7, wherein: The light-adjusting layer has a plurality of regions divided into a matrix according to the voltages of the plurality of first electrodes and the voltages of the plurality of second electrodes. The process of adjusting the timing includes the following processes: receiving a dimming signal including a designation of an applied waveform to be supplied to the first electrode and the second electrode; determining, based on the dimming signal, a pattern of light-shielding areas set to an off state among the plurality of areas, namely, a light-shielding pattern; Calculating a load of voltage supplied to the light-shielding area according to the light-shielding pattern; as well as Based on the load amount, a delay amount to be added to the voltage supply to the light-shielding area is determined.

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