Hardware architecture of chip and firmware loading method of chip
By integrating the firmware information of the Thunderbolt interface retimer into the firmware of the PD and EC, and storing it in the SPI ROM together with the BIOS, the hardware redundancy problem is solved, the hardware architecture is optimized, the cost and space waste are reduced, and the energy efficiency of the laptop is improved.
Patent Information
- Application Number
- CN202510607396.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-12
- Publication Date
- 2025-09-30
AI Technical Summary
In traditional laptop designs, the Thunderbolt interface retimer firmware occupies a separate megabyte-level ROM, resulting in hardware redundancy, increased cost and wasted board space.
The Thunderbolt interface retimer's firmware information is integrated into the firmware of the power management chip (PD) and stored in the SPI ROM together with the firmware information of the embedded controller (EC). Firmware isolation is achieved through logical address division. The Thunderbolt interface retimer has internal flash memory, and the firmware is loaded from the PD's internal flash memory through the I2C bus. The enable signal of its power switch is controlled by GPIO.
It reduces the use of external ROM, reduces hardware costs, improves circuit board space utilization, avoids ineffective power consumption, and improves the energy efficiency and overall performance of laptops.
Smart Images
Figure CN120723282A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of chip technology, and in particular to a chip hardware architecture and a chip firmware loading method. Background Art
[0002] In traditional laptop circuit design, the power management chip (Power Delivery, PD) and embedded controller (Embedded Controller, EC) each store their firmware (Firmware, FW) in an external read-only memory (ROM). However, with the trend toward thinner and more integrated laptops, mainstream laptop designs now integrate the PD firmware into the EC, and the EC firmware is now included in the Basic Input / Output System (BIOS), sharing the same SPI ROM. Furthermore, the firmware for the Thunderbolt signal retimer (TBT Retimer) also needs to be stored separately on a dedicated external SPI ROM.
[0003] In the existing technical solution, the firmware of the TBT Retimer is about 200KB, but it occupies a megabyte-level ROM alone. This design is wasteful both in terms of cost and circuit board space utilization. Summary of the Invention
[0004] The present disclosure provides a chip hardware architecture and a chip firmware loading method to at least solve the above technical problems existing in the prior art.
[0005] According to a first aspect of the present disclosure, a chip hardware architecture is provided, the hardware architecture comprising: a power management chip PD, an embedded controller EC, a Thunderbolt interface retimer, and a serial peripheral interface read-only memory SPI ROM;
[0006] The firmware information of the Thunderbolt interface retimer is first integrated into the firmware of the PD, and the firmware information of the Thunderbolt interface retimer and the firmware information of the PD are then integrated into the firmware of the EC and stored in the SPIROM;
[0007] The Thunderbolt interface retimer is provided with an internal flash memory and is connected to the PD;
[0008] The enable signal pin for controlling the power switch of the Thunderbolt interface retimer is connected to the basic input and output GPIO of the PD.
[0009] In one possible implementation manner, the EC is used to mirror the firmware information including the EC, PD, and Thunderbolt interface retimer from the SPIROM to its internal flash memory via the SPI bus when the terminal is powered on for the first time.
[0010] In one embodiment, the EC is further configured to transmit firmware information of the PD and the Thunderbolt interface retimer to the PD through a first I2C interface.
[0011] In one possible implementation, the PD is configured to control the power-on of the Thunderbolt interface retimer through the GPIO pin when it is detected that the Thunderbolt interface is connected to an external device.
[0012] In one possible implementation, the Thunderbolt interface retimer is configured to load the firmware information of the Thunderbolt interface retimer from the PD through the second I2C interface after power-on, and store the firmware information into its internal flash memory.
[0013] In one possible implementation manner, the SPI ROM is connected to the EC and CPU respectively via an SPI bus, and stores the EC and BIOS firmware simultaneously.
[0014] According to a second aspect of the present disclosure, a method for loading firmware of a chip is provided, comprising:
[0015] When the terminal is powered on for the first time, the EC copies the firmware information containing the EC, PD, and Thunderbolt interface retimer from the SPI ROM to its internal flash memory via the SPI bus;
[0016] The EC transmits the firmware information of the PD and the Thunderbolt interface retimer to the PD through the first I2C interface;
[0017] When the PD detects that the Thunderbolt interface is connected to an external device, it controls the Thunderbolt interface retimer to power on through the GPIO pin, and triggers the Thunderbolt interface retimer to load the firmware information of the Thunderbolt interface retimer from the PD to its internal flash memory.
[0018] In one possible implementation, when the terminal is not powered on for the first time, the EC directly transmits the firmware information of the PD and the Thunderbolt interface retimer to the PD through the first I2C interface.
[0019] In one embodiment, the PD detects whether the Thunderbolt interface is connected to an external device, including:
[0020] The PD detects the status of the lightning interface by configuring the channel pin to determine whether an external device is connected;
[0021] If access is detected, the level of the GPIO pin is pulled high to start the power supply of the Thunderbolt interface retimer.
[0022] In one possible implementation manner, triggering the Thunderbolt interface retimer to load the firmware information of the Thunderbolt interface retimer from the PD includes:
[0023] Reading the firmware information of the Thunderbolt interface retimer in the internal flash memory of the PD through the second I2C interface;
[0024] The firmware information is written into the internal flash memory of the Thunderbolt interface retimer.
[0025] The present disclosure provides a chip hardware architecture and a chip firmware loading method, including PD, EC, Thunderbolt interface retimer and SPI ROM. The firmware information of the Thunderbolt interface retimer is first integrated into the firmware of the PD, and the firmware information of the Thunderbolt interface retimer and the firmware information of the PD are then integrated into the firmware of the EC, and are stored in the SPIROM together with the BIOS, and firmware isolation is achieved through logical address division. The Thunderbolt interface retimer is provided with an internal flash memory and is connected to the PD. The firmware is loaded from the internal flash memory of the PD to its own internal flash memory through the I2C bus to complete initialization. At the same time, the enable signal pin that controls the power switch of the Thunderbolt interface retimer is connected to the GPIO of the PD, and the PD controls the level state of the pin through firmware logic to achieve on-demand power supply. This solution effectively solves the problem of hardware redundancy in the prior art. In traditional designs, the Thunderbolt retimer's firmware is stored in a separate ROM, resulting in a waste of cost and circuit board space. Therefore, this solution integrates the Thunderbolt retimer's firmware information into the PD's firmware first. The Thunderbolt retimer's firmware information and the PD's firmware information are then integrated into the EC's firmware. Both the Thunderbolt retimer's firmware information and the PD's firmware information are stored in a shared SPIROM with the BIOS. This reduces the use of external ROM, lowers hardware costs, and improves circuit board space utilization. Furthermore, by controlling the Thunderbolt retimer's power switch via the PD, on-demand power supply is achieved, avoiding inefficient power consumption and further improving the laptop's energy efficiency. This integrated design conforms to the trend toward thinner and more integrated notebooks, optimizes the hardware architecture, and enhances the product's overall performance and competitiveness.
[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:
[0028] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.
[0029] Figure 1 A schematic diagram of the hardware architecture of a chip according to an embodiment of the present disclosure is shown;
[0030] Figure 2 A schematic diagram of the implementation flow of the firmware loading method for the chip according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0031] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.
[0032] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.
[0034] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.
[0035] Power Delivery (PD) chips are key to implementing charging interfaces and managing power transmission. Widely used in devices like mobile phones and laptops, they adjust voltage and current output based on device requirements, ensuring efficient and safe charging.
[0036] An embedded controller (EC) is a microcontroller integrated into the motherboard. It operates independently of the CPU and is responsible for managing the system's underlying hardware, power management, system wakeup, and other functions. It interacts with the BIOS and operating system to ensure stable system operation.
[0037] A Thunderbolt retimer (TBT Retimer) is used in a Thunderbolt system to retiming high-speed Thunderbolt signals, eliminating jitter and attenuation during signal transmission and ensuring data integrity.
[0038] Serial Peripheral Interface Read-Only Memory (SPIROM) is a memory chip that uses the SPI (Serial Peripheral Interface) communication protocol. It is a non-volatile memory accessed through the SPI bus and is used to store firmware code (such as EC, PD, and Thunderbolt retimer firmware).
[0039] The present disclosure provides a hardware architecture of a chip, such as Figure 1 As shown, the hardware architecture includes: power management chip PD, embedded controller EC, Thunderbolt interface retimer and serial peripheral interface read-only memory SPIROM;
[0040] The firmware information of the Thunderbolt interface retimer is first integrated into the firmware of the PD, and the firmware information of the Thunderbolt interface retimer and the firmware information of the PD are then integrated into the firmware of the EC and stored in the SPI ROM.
[0041] In this example, in traditional designs, the PD and Thunderbolt retimer firmware are stored in separate ROMs, resulting in hardware redundancy. The disclosed solution integrates the Thunderbolt retimer firmware information into the PD firmware, which in turn integrates the PD firmware information, including the Thunderbolt retimer firmware information, into the EC firmware. Both are stored in a shared SPIROM, achieving firmware isolation through logical address partitioning, such as segmented storage of the EC firmware, PD firmware, and Thunderbolt retimer firmware.
[0042] The Thunderbolt interface retimer is provided with an internal flash memory and is connected to the PD.
[0043] In this example, the Thunderbolt retimer connects to the PD via the I2C bus. When the PD detects a Thunderbolt device, it outputs an enable signal via a GPIO pin to power on the Thunderbolt retimer. After the Thunderbolt retimer is powered on, it loads the firmware from the PD's internal flash memory to its own via the I2C bus, completing initialization.
[0044] The enable signal pin for controlling the power switch of the Thunderbolt interface retimer is connected to the basic input and output GPIO of the PD.
[0045] In this example, the enable signal pin is a hardware pin that controls the power switch. It triggers the Thunderbolt interface retimer to power on or off via high or low level signals. This enable signal pin is directly connected to the PD's GPIO pin. The PD uses firmware logic to control the pin's level, enabling on-demand power delivery and avoiding inefficient power consumption.
[0046] The present disclosure provides a hardware architecture of a chip and a firmware loading method for a chip, including PD, EC, Thunderbolt interface retimer and SPI ROM. The firmware information of the Thunderbolt interface retimer is first integrated into the firmware of the PD, and the firmware information of the Thunderbolt interface retimer and the firmware information of the PD are then integrated into the firmware of the EC, and are stored in the SPIROM together with the BIOS, and firmware isolation is achieved through logical address division. The Thunderbolt interface retimer is provided with an internal flash memory and is connected to the PD. The firmware is loaded from the internal flash memory of the PD to its own internal flash memory through the I2C bus to complete initialization. At the same time, the enable signal pin that controls the power switch of the Thunderbolt interface retimer is connected to the GPIO of the PD. The PD controls the level state of the pin through firmware logic to achieve power supply on demand.
[0047] This solution effectively solves the problem of hardware redundancy in existing technologies. In traditional designs, the firmware of the Thunderbolt interface retimer is stored in a separate ROM, resulting in a waste of cost and circuit board space. Therefore, this solution first integrates the firmware information of the Thunderbolt interface retimer into the firmware of the PD, and then integrates the firmware information of the Thunderbolt interface retimer and the PD into the firmware of the EC. The firmware information is then stored in a shared SPI ROM with the BIOS, which reduces the use of external ROM, reduces hardware costs, and improves circuit board space utilization. In addition, by controlling the power switch of the Thunderbolt interface retimer through the PD, power supply is realized on demand, which avoids ineffective power consumption and further improves the energy efficiency of the laptop. This integrated design conforms to the development trend of thinner and more integrated laptops, optimizes the hardware architecture, and improves the overall performance and competitiveness of the product.
[0048] In one example, the EC is used to mirror the firmware information including the EC, PD, and Thunderbolt interface retimer from the SPIROM to its internal flash memory via the SPI bus when the terminal is powered on for the first time.
[0049] In this example, after assembly is complete, such as SMT placement, the terminal device is powered on for the first time. All hardware components must be initialized and basic firmware loaded for the initial power-up of the terminal. The EC, acting as the master controller, accesses the shared SPIROM via the SPI bus, reads the firmware information for the EC itself, the PD, and the Thunderbolt retimer from the SPIROM, and then copies the firmware information of the EC, PD, and Thunderbolt retimer to the EC's internal flash memory, which serves as the firmware source for subsequent operations.
[0050] After the image is completed at the first power-on, the EC can subsequently read the firmware directly from the internal flash memory without repeatedly accessing the external SPIROM, reducing bus occupancy and latency. The image process is automatically triggered by the EC hardware without the need for external intervention, ensuring the reliability of the boot process.
[0051] In one example, the EC is further configured to transmit firmware information of the PD and the Thunderbolt interface retimer to the PD through a first I2C interface.
[0052] In this example, the first I2C interface is a dedicated I2C communication channel between the EC and the PD, distinct from other I2C communication interfaces. After mirroring and storing the firmware information, the EC sends the firmware information integrating the PD and the Thunderbolt interface retimer to the PD via the first I2C interface. The PD receives the firmware and stores it in its internal flash memory.
[0053] Because the PD and Thunderbolt retimer firmware are integrated into the EC's firmware package, the EC can distribute both firmware via a single I2C interface, eliminating the need to access multiple storage sources. The PD, acting as an intermediate node, not only stores its own firmware but also temporarily caches the Thunderbolt retimer firmware, triggering subsequent loading when a device is connected.
[0054] In one example, the PD is used to control the power-on of the Thunderbolt interface retimer through the GPIO pin when it is detected that the Thunderbolt interface is connected to an external device.
[0055] In this example, the PD determines whether an external device (such as a display or storage device) is plugged in based on the level of the Thunderbolt interface's configuration channel. The general-purpose input / output pin, configured in output mode, transmits high / low signals to control the Thunderbolt retimer's power. If a device is detected, the PD's firmware logic generates a power-enable signal and outputs a high level to the Thunderbolt retimer's power control pin via a GPIO pin. Pulling the GPIO pin high triggers the Thunderbolt retimer's power circuitry to start operating.
[0056] In one example, the Thunderbolt interface retimer is configured to load the firmware information of the Thunderbolt interface retimer from the PD through the second I2C interface after power-on, and store the firmware information in its internal flash memory.
[0057] In this example, the second I2C interface serves as a dedicated communication channel between the Thunderbolt retimer and the PD, independent of the first I2C interface between the EC and the PD. After powering on, the Thunderbolt retimer sends a firmware information request signal to the PD via the second I2C interface. Upon receiving the request, the PD reads the pre-stored Thunderbolt retimer firmware from its internal flash memory and transmits it to the retimer via the second I2C interface. The Thunderbolt retimer writes the received firmware data piece by piece to its internal flash memory and performs a checksum upon completion to ensure data integrity.
[0058] In one example, the SPI ROM is connected to the EC and CPU respectively through an SPI bus, and stores the EC and BIOS firmware simultaneously.
[0059] In this example, the EC, acting as the SPI bus master, directly accesses the SPI ROM via the SPI bus to read its own firmware and the integrated PD and Thunderbolt interface retimer firmware. The CPU, acting as the other master, accesses the same SPI ROM via independent chip select signals to read the BIOS firmware for system boot. The EC and CPU can time-share the SPI bus, or adopt multi-master mode to ensure independent data access, eliminating the need for a separate BIOS ROM chip and reducing PCB area and bill of materials costs.
[0060] The CPU also connects to the PD via the System Management Bus (SMBus). The SMBus (System Management Bus) is a low-speed communication bus based on the I2C protocol, specifically for system management tasks. In this example, the CPU sends global power management commands to the PD via the SMBus; the PD provides real-time power status feedback to the CPU via the SMBus. During firmware upgrades, the CPU transmits update commands or verification results to the PD via the SMBus.
[0061] The present disclosure also provides a method for loading firmware of a chip, such as Figure 2 As shown, including:
[0062] Step 201: When the terminal is powered on for the first time, the EC mirrors the firmware information including the EC, PD, and Thunderbolt interface retimer from the SPI ROM to its internal flash memory via the SPI bus.
[0063] In this example, when the terminal is first powered on, the EC boots up first as the main controller, accessing the shared SPI ROM via the SPI bus. It then reads the integrated firmware package (containing the code corresponding to the firmware information for the EC itself, the PD, and the Thunderbolt interface retimer) from the SPI ROM. The EC copies the integrated firmware package to the internal flash memory, ensuring that subsequent operations do not require repeated access to the external SPI ROM.
[0064] Step 202: The EC transmits the firmware information of the PD and the Thunderbolt interface retimer to the PD through the first I2C interface.
[0065] In this example, after completing its own firmware image, the EC actively initiates transmission through the first I2C interface; the PD firmware (for the PD itself to run) and the Thunderbolt interface retimer firmware (temporarily stored in the PD's internal flash memory) contained in the integrated firmware package are integrated; after the PD receives the data, it stores its own firmware and the Thunderbolt interface retimer firmware information in the internal running memory for subsequent on-demand calls.
[0066] The integrated firmware package read by EC from the SPI ROM already contains the code for PD and Thunderbolt interface retimer, and is distributed through a single transmission operation without multiple accesses to different storage sources. As a firmware transfer node, PD not only stores its own running code but also provides firmware cache for the Thunderbolt interface retimer, simplifying the latter's loading logic.
[0067] Step 203: When the PD detects that the Thunderbolt interface is connected to an external device, it controls the Thunderbolt interface retimer to power on through the GPIO pin, and triggers the Thunderbolt interface retimer to load the firmware information of the Thunderbolt interface retimer from the PD to its internal flash memory.
[0068] In this example, the PD monitors the pin status of the Thunderbolt interface in real time. When a device is detected, the firmware logic generates a power enable signal. It outputs a high level to the enable signal pin of the Thunderbolt interface retimer through the GPIO pin to start its power circuit.
[0069] After the Thunderbolt interface retimer is powered on, the PD reads the pre-stored Thunderbolt interface retimer firmware information from the internal flash memory and transmits it to the retimer; the Thunderbolt interface retimer writes the received firmware into the internal flash memory and starts running after verification is completed.
[0070] In one example, when the terminal is not powered on for the first time, the EC directly transmits the firmware information of the PD and the Thunderbolt interface retimer to the PD through the first I2C interface.
[0071] In this example, the EC determines whether it is not the first power-on by detecting the integrity flag of the firmware in the internal flash memory. If the flag is valid, based on the fact that a complete firmware package is already stored in the EC's internal flash memory, the firmware can be directly transferred to the PD through the first I2C interface, skipping the mirroring step, thereby eliminating the SPI bus access and mirroring operations, shortening the startup time, and directly using the firmware data in the internal flash memory to ensure that the firmware versions of the PD and the Thunderbolt interface retimer are completely consistent with the first power-on, avoiding potential compatibility issues.
[0072] In one example, the PD detects whether the Thunderbolt interface is connected to an external device, including: the PD detects the Thunderbolt interface status by configuring the channel pin to determine whether an external device is connected; if connection is detected, the level of the GPIO pin is pulled high to start the power supply of the Thunderbolt interface retimer.
[0073] In this example, the PD's firmware reads the configuration channel pin level of the Thunderbolt interface at a fixed frequency. If the level changes from low to high, it determines that a device is connected; if the level changes from high to low, it determines that the device is disconnected. When a device is detected, the PD outputs a high-level signal through the GPIO pin, triggering the power supply of the Thunderbolt interface retimer. When a device is detected as disconnected, the PD pulls the GPIO level low to shut down the retimer.
[0074] In one example, triggering the Thunderbolt interface retimer to load the firmware information of the Thunderbolt interface retimer from the PD includes: reading the firmware information of the Thunderbolt interface retimer in the internal flash memory of the PD through a second I2C interface; and writing the firmware information into the internal flash memory of the Thunderbolt interface retimer.
[0075] In this example, after the Thunderbolt retimer is powered on (power is controlled by the PD via GPIO), it automatically sends a firmware request signal to the PD via the second I2C interface. Upon receiving the request, the PD reads the pre-stored Thunderbolt retimer firmware data from its internal flash memory. The PD transmits the firmware data in segments to the Thunderbolt retimer via the second I2C interface. The Thunderbolt retimer writes the received data segment by segment to its internal flash memory and performs a checksum after completion to ensure data integrity. If the checksum passes, the retimer loads the firmware from the internal flash memory, initializes, and begins performing signal timing adjustment functions.
[0076] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.
[0077] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.
[0078] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.
Claims
1. A chip hardware architecture, characterized in that: The hardware architecture includes: power management chip PD, embedded controller EC, Thunderbolt interface retimer and serial peripheral interface read-only memory SPIROM; The firmware information of the Thunderbolt interface retimer is first integrated into the firmware of the PD, and the firmware information of the Thunderbolt interface retimer and the firmware information of the PD are then integrated into the firmware of the EC and stored in the SPIROM; The Thunderbolt interface retimer is provided with an internal flash memory and is connected to the PD; The enable signal pin for controlling the power switch of the Thunderbolt interface retimer is connected to the basic input and output GPIO of the PD.
2. The hardware architecture according to claim 1, wherein: The EC is used to mirror the firmware information including EC, PD and Thunderbolt interface retimer from the SPIROM to its internal flash memory via the SPI bus when the terminal is powered on for the first time.
3. The hardware architecture according to claim 2, characterized in that: The EC is further configured to transmit firmware information of the PD and the Thunderbolt interface retimer to the PD via a first I2C interface.
4. The hardware architecture according to claim 1, wherein: The PD is used to control the power-on of the Thunderbolt interface retimer through the GPIO pin when it is detected that the Thunderbolt interface is connected to an external device.
5. The hardware architecture according to claim 1, wherein: The Thunderbolt interface retimer is used to load the firmware information of the Thunderbolt interface retimer from the PD through the second I2C interface after power-on, and store it in its internal flash memory.
6. The hardware architecture according to claim 1, wherein: The SPIROM is connected to the EC and CPU respectively through the SPI bus, and stores the EC and BIOS firmware simultaneously.
7. A method for loading firmware into a chip, characterized in that: include: When the terminal is powered on for the first time, the EC copies the firmware information containing the EC, PD, and Thunderbolt interface retimer from the SPI ROM to its internal flash memory via the SPI bus; The EC transmits the firmware information of the PD and the Thunderbolt interface retimer to the PD through the first I2C interface; When the PD detects that the Thunderbolt interface is connected to an external device, it controls the Thunderbolt interface retimer to power on through the GPIO pin, and triggers the Thunderbolt interface retimer to load the firmware information of the Thunderbolt interface retimer from the PD to its internal flash memory.
8. The method according to claim 7, characterized in that When the terminal is not powered on for the first time, the EC directly transmits the firmware information of the PD and the Thunderbolt interface retimer to the PD through the first I2C interface.
9. The method according to claim 7, characterized in that The PD detects whether the lightning interface is connected to an external device, including: The PD detects the status of the lightning interface by configuring the channel pin to determine whether an external device is connected; If access is detected, the level of the GPIO pin is pulled high to start the power supply of the Thunderbolt interface retimer.
10. The method according to claim 7, characterized in that The triggering the Thunderbolt interface retimer to load the firmware information of the Thunderbolt interface retimer from the PD includes: Reading the firmware information of the Thunderbolt interface retimer in the internal flash memory of the PD through the second I2C interface; The firmware information is written into the internal flash memory of the Thunderbolt interface retimer.