A chip trimming system and method

Abstract

The application provides a chip trimming system and method, and relates to the technical field of chip trimming. The system comprises a test mode pin, a selection circuit, a core circuit and a physical trimming circuit. When the test mode pin is enabled, the selection circuit sends a test mode instruction to the core circuit through a first output end. When the core circuit enters the test mode, a test input pin inputs a plurality of different signals to the selection circuit. The selection circuit processes the plurality of different signals to obtain a plurality of different first trimming code combinations, and sends the plurality of different first trimming code combinations to the core circuit through a second output end. The core circuit responds to the plurality of different first trimming code combinations to determine a target trimming code combination. The physical trimming circuit configures encapsulation-level rewire connection of a trimming pad of a chip layer according to the target trimming code combination. The chip trimming system can reduce the time and cost of chip production while ensuring trimming accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip trimming, in particular to a chip trimming system and method. BACKGROUND

[0002] In the design and manufacturing process of analog circuits, in order to ensure that the performance indicators and functional accuracy of the circuit meet the design requirements, chip trimming is usually performed in the late production. This trimming operation can be implemented at the wafer level or completed at the package level, depending on the trimming method used.

[0003] However, existing analog circuit trimming techniques usually require special process options, back-end metal layer mask changes, and complex test methods / equipment. These requirements will increase the time to market and cost of the chip.

[0004] In summary, how to reduce the time and cost of chip production while ensuring trimming accuracy is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a chip trimming system and method to reduce the time and cost of chip production while ensuring trimming accuracy.

[0006] To achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0007] On the one hand, the embodiments of the present application provide a chip trimming system, which comprises a trimming test circuit and a physical trimming circuit; the trimming test circuit comprises a test mode pin, a selection circuit and a core circuit;

[0008] The first input end, the second input end and the third input end of the selection circuit are connected with the test mode pin, the test input pin of the chip and the trimming pad respectively; the first output end and the second output end of the selection circuit are connected with the first input end and the second input end of the core circuit respectively; the physical trimming circuit is connected with the trimming pad;

[0009] When the test mode pin is enabled, the selection circuit is used to send a test mode instruction to the core circuit through the first output end, so that the core circuit enters the test mode;

[0010] When the core circuit enters the test mode, the test input pin is used to input a plurality of different signals to the selection circuit; the selection circuit is further used to process the plurality of different signals to obtain a plurality of different first trimming code combinations, and send the plurality of different first trimming code combinations to the core circuit through the second output end; the core circuit is used to respond to the plurality of different first trimming code combinations to determine a target trimming code combination;

[0011] The physical trimming circuit is used to configure the package level rewire connection of the trimming pad of the chip layer according to the target trimming code combination.

[0012] Further, when the test mode pin is not enabled, the selection circuit is used to send a normal working mode instruction to the core circuit through the first output end, so that the core circuit enters the normal working mode;

[0013] When the core circuit enters the normal working mode, the selection circuit is used to select the second trimming code combination input by the trimming pad as an output, and send the second trimming code combination to the core circuit through the second output end; the core circuit is used to normally work according to the received second trimming code combination.

[0014] Further, the selection circuit comprises a trimming selection module and a mode selection module;

[0015] The first input end, the second input end and the third input end of the trimming selection module are connected with the test mode pin, the test input pin and the trimming pad respectively; the first output end and the second output end of the trimming selection module are connected with the first input end of the mode selection module and the second input end of the core circuit respectively; the second input end of the mode selection module is connected with the test mode pin, and the output end of the mode selection module is connected with the first input end of the core circuit;

[0016] When the test mode pin is enabled, the mode selection module is used to output a test mode instruction to the core circuit according to the signals received by the first input end and the second input end and the test mode default value; the trimming selection module is used to process a plurality of different signals output by the test input pin in the test mode to obtain a plurality of different first trimming code combinations, and send the plurality of different first trimming code combinations to the core circuit through the second output end;

[0017] When the test mode pin is not enabled, the trimming selection module is configured to process a signal output by the test input pin in a normal working mode and send the processed signal to a first input of the mode selection module through a first output; the mode selection module is configured to output a normal working mode instruction to the core circuit according to signals received by the first input and a second input and a test mode default value; and the trimming selection module is further configured to select a second trimming code combination input by the trimming pad as an output and send the second trimming code combination to the core circuit through a second output.

[0018] Further, the trimming selection module comprises a signal processor, an analog-to-digital converter, a switch and a multiplexer.

[0019] The test input pin is connected to an input of the signal processor and one end of the switch, respectively; an output of the signal processor is connected to a first input of the mode selection module; the other end of the switch is connected to an input of the analog-to-digital converter; an output of the analog-to-digital converter is connected to a first data input of the multiplexer; the trimming pad is connected to a second data input of the multiplexer; and an output of the multiplexer is connected to a second input of the core circuit; the test mode pin is connected to a control end of the switch, a control end of the signal processor, a control end of the multiplexer and a second input of the mode selection module, respectively.

[0020] When the test mode pin is enabled, the signal processor is disabled, and the switch is closed; the mode selection module is configured to send a test mode instruction to the first input of the core circuit; the analog-to-digital converter is configured to convert a plurality of different analog signals output by the test input pin in a test mode into digital signals respectively, to obtain a plurality of different first trimming code combinations; and the multiplexer is configured to send the plurality of different first trimming code combinations received by the first data input as an output to the second input of the core circuit.

[0021] When the test mode pin is not enabled, the switch is open, and the signal processor is configured to process a signal output by the test input pin in a normal working mode and send the processed signal to the first input of the mode selection module; the mode selection module is configured to send a normal working mode instruction to the first input of the core circuit; and the multiplexer is configured to send a second trimming code combination input by the trimming pad as an output to the second input of the core circuit.

[0022] Further, the physical trimming circuit is configured to connect the trimming pad of the chip layer to a power pad or a ground pad of the package layer through a package-level redistribution according to a combination of a trimming default value and the target trimming code.

[0023] Further, the physical trimming circuit comprises a pull-down resistor; when the trimming default value is 0, a chip-layer ground pad is connected to a package-layer ground pad through a first redistribution layer, and one end of the pull-down resistor is connected to the trimming pad, and the other end of the pull-down resistor is connected to the chip-layer ground pad, and the pull-down resistor is configured to pull down a trimming bit of the trimming pad to 0.

[0024] Further, when the trimming default value is 0 and a corresponding target trimming value in the target trimming code combination is 1, the trimming pad is connected to a package-layer power pad through a second redistribution layer;

[0025] When the trimming default value is 0 and a corresponding target trimming value in the target trimming code combination is 0, the trimming pad is connected to a package-layer ground pad through the second redistribution layer, or the trimming pad is connected to the package-layer ground pad through the pull-down resistor and the first redistribution layer.

[0026] Further, the physical trimming circuit comprises a pull-up resistor; when the trimming default value is 1, a chip-layer power pad is connected to a package-layer power pad through a third redistribution layer, and one end of the pull-up resistor is connected to the trimming pad, and the other end of the pull-up resistor is connected to the chip-layer power pad, and the pull-up resistor is configured to pull up a trimming bit of the trimming pad to 1.

[0027] Further, when the trimming default value is 1 and a corresponding target trimming value in the target trimming code combination is 0, the trimming pad is connected to a package-layer ground pad through a fourth redistribution layer;

[0028] When the trimming default value is 1 and a corresponding target trimming value in the target trimming code combination is 1, the trimming pad is connected to a package-layer power pad through the fourth redistribution layer, or the trimming pad is connected to the package-layer power pad through the pull-up resistor and the third redistribution layer.

[0029] In another aspect, the embodiments of the present application also provide a chip trimming method, which is applied to the chip trimming system as described in any of the preceding embodiments, and the method comprises:

[0030] When the test mode pin is enabled, the selection circuit sends a test mode instruction to the core circuit through a first output end, so as to make the core circuit enter a test mode.

[0031] When the core circuit enters the test mode, the test input pin inputs a plurality of different signals to the selection circuit; the selection circuit processes the plurality of different signals to obtain a plurality of different first trimming code combinations, and sends the plurality of different first trimming code combinations to the core circuit through the second output end; the core circuit responds to the plurality of different first trimming code combinations to determine a target trimming code combination;

[0032] The physical trimming circuit performs package-level rewire connection configuration on the trimming pads of the chip layer according to the target trimming code combination.

[0033] Compared with the prior art, the present application has the following beneficial effects:

[0034] The present application provides a chip trimming system and method, which comprises a trimming test circuit and a physical trimming circuit. The trimming test circuit comprises a test mode pin, a selection circuit and a core circuit. The first input end, the second input end and the third input end of the selection circuit are connected with the test mode pin, the test input pin of the chip and the trimming pad respectively; the first output end and the second output end of the selection circuit are connected with the first input end and the second input end of the core circuit respectively; the physical trimming circuit is connected with the trimming pad. When the test mode pin is enabled, the selection circuit is used to send a test mode instruction to the core circuit through the first output end, so that the core circuit enters the test mode. When the core circuit enters the test mode, the test input pin is used to input a plurality of different signals to the selection circuit; the selection circuit is also used to process the plurality of different signals to obtain a plurality of different first trimming code combinations, and send the plurality of different first trimming code combinations to the core circuit through the second output end; the core circuit is used to respond to the plurality of different first trimming code combinations to determine a target trimming code combination. The physical trimming circuit is used to perform package-level rewire connection configuration on the trimming pads of the chip layer according to the target trimming code combination.

[0035] The present application introduces a test mode in the circuit, only needs to add a test mode pin and reuse the existing test input pin of the chip, and can test the influence of all possible trimming code combinations on the circuit performance without modifying the wafer or the package structure and with extremely low hardware cost, so as to find the target trimming code combination. The target trimming code combination determined in the test mode process will be applied to the chip packaging stage. The trimming pads on the wafer are connected and configured according to the target trimming code combination through the package-level rewire layer to set the required control level, and finally the discrete trimming of the chip is realized. The present application does not depend on any specific process option, can test all possible trimming code combinations before performing the final trimming, and realizes the reduction of the time and cost of chip production under the premise of ensuring the trimming accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0036] The technical solutions and advantages of the embodiments of the present application will be clearer in the following description of the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0037] Figure 1 A structural schematic diagram of a chip trimming system provided by an embodiment of the present application;

[0038] Figure 2 A structural schematic diagram of a trimming test circuit provided by an embodiment of the present application;

[0039] Figure 3 A structural schematic diagram of a trimming test circuit provided by an embodiment of the present application;

[0040] Figure 4 A structural schematic diagram of a physical trimming circuit provided by an embodiment of the present application;

[0041] Figure 5 A structural schematic diagram of a physical trimming circuit provided by an embodiment of the present application;

[0042] Figure 6 A flowchart of a chip trimming method provided by an embodiment of the present application.

[0043] Figure: 10-chip trimming system; 100-trimming test circuit; 110-test mode pin; 120-selection circuit; 121-trimming selection module; 1211-signal processor; 1212-analog-to-digital converter; 1213-multiplexer; 122-mode selection module; 130-core circuit; 200-physical trimming circuit; 20-test input pin; 30-trimming pad; K-switch; Rpd-pull-down resistor; Rpu-pull-up resistor; RDL VIA1-first redistribution connection layer; RDL VIA2-second redistribution connection layer; RDL VIA3-third redistribution connection layer; RDL VIA4-fourth redistribution connection layer; GND1-chip layer ground pad; VDD1-chip layer power supply pad; GND2-package layer ground pad; VDD2-package layer power supply pad. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0045] It should be noted that the relational terms such as "first" and "second" and the like are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or apparatus that includes a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0046] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0047] As described in the background, the existing analog circuit trimming techniques mainly have the following five kinds:

[0048] (1) Metal-fix: Metal-fix can connect or disconnect certain circuit elements by changing the mask of the back-end-of-line (BEOL). However, each change of the mask layer will increase the time and cost of wafer production.

[0049] (2) Laser Trim: Laser Trim requires the use of thin-film resistors. However, not all semiconductor processes support thin-film resistors, and some may require additional mask costs even if they do. In addition, cutting on thin-film resistors also requires special instruments and increases test time, thereby increasing test costs.

[0050] (3) Zener Zapping: Zener Zapping is a method of applying a high voltage to the base-emitter junction of a transistor to create a short, thereby completing the trimming. However, Zener Zapping is not supported by all processes. Moreover, Zener Zapping requires multiple additional pins or probe pads to apply the voltage to the trimmed element, and the breakdown current, voltage, and duration must be properly coordinated to result in a very low resistance for the zapped element. This process not only increases the complexity of the test interface, but also requires high-precision voltage / current sources and timing control circuits, resulting in increased cost of test equipment and longer production flow, which ultimately increases the overall manufacturing cost.

[0051] (4) Link / Fuse trim: Link / Fuse trim is a method of creating an open circuit in the circuit by laser cutting or passing a large current to melt a metal or polysilicon fuse, thereby completing the trimming. This method does not require special processes, but the trimmed element can be optimized for fuse applications. For example, if laser cutting is used, no additional pins are required, but in-package trimming is not possible. If large current melting is used, probe pads are required for wafer-level trimming, and multiple additional pins are required for post-packaging trimming, resulting in increased cost.

[0052] (5) EEPROM or OTP trim: EEPROM or OTP trim is a discrete trimming method that uses a special non-volatile memory to store trimming data, which is converted to analog through circuits such as D / A converters to adjust the device parameters. However, this method requires special processes to manufacture the memory unit, and multiple additional pins are required to program the OTP, increasing the cost of chip production.

[0053] As can be seen, existing analog circuit trimming techniques usually require special process options, back-end metal layer mask changes, and complex test methods / equipment. These requirements will increase the time to market and cost of chips. Therefore, how to reduce the time and cost of chip production while ensuring trimming accuracy is a technical problem that needs to be solved by those skilled in the art.

[0054] To solve the above technical problems, the chip trimming system provided by the embodiments of the present application is suitable for integrated circuits and has cost-effectiveness. The chip trimming system is integrated in a chip. By introducing a "test mode (or engineering mode)" in the circuit, the influence of different trim code combinations on the performance of the circuit can be tested without modifying the wafer or the package itself, with minimal hardware overhead and without affecting the normal application of the chip, so as to determine the target trim code combination (i.e., the optimal trim code combination). Finally, according to the target trim code combination, physical trimming is realized by using the package-level metal connection.

[0055] It should be noted that the chip trimming system provided by the embodiments of the present application is only suitable for packaging types using package-level redistribution layers (RDL), such as ball grid array packaging (BGA), chip scale package (CSP), and the like.

[0056] The present application uses package-level redistribution for trimming, mainly based on its significant cost advantage. Specifically, the test mode of the present application is performed after the chip is taped out (both the front-end process and the back-end process have been completed) but before it is packaged. At this time, the function of the die on the wafer is complete, and the target trim code combination is quickly determined through the test mode. Subsequently, physical connection is realized by RDL wiring during the packaging stage, and trimming is completed. Compared with the traditional wafer-level trimming scheme, this method avoids additional photolithography or metal layer modification steps, greatly reducing the trimming cost and production cycle.

[0057] For better understanding, the chip trimming system provided by the embodiments of the present application is described in detail below.

[0058] As shown in Figure 1 The chip trimming system 10 provided by the embodiments of the present application includes a trimming test circuit 100 and a physical trimming circuit 200. The trimming test circuit 100 includes a test mode pin 110, a selection circuit 120, and a core circuit 130.

[0059] The first input end, the second input end, and the third input end of the selection circuit 120 are connected with the test mode pin 110, the test input pin 20 of the chip, and the trimming pad (also called probe pad) 30, respectively. The first output end and the second output end of the selection circuit 120 are connected with the first input end and the second input end of the core circuit 130, respectively. The physical trimming circuit 200 is connected with the trimming pad 30.

[0060] When the test mode pin 110 is enabled (for example, the test mode pin 110 is high 1), the selection circuit 120 sends the test mode instruction to the first input end of the core circuit 130 through the first output end, so that the core circuit 130 enters the test mode.

[0061] When the core circuit 130 enters the test mode, the test input pin 20 inputs a plurality of different signals to the selection circuit 120. The selection circuit 120 processes the plurality of different signals to obtain a plurality of different first trimming code combinations (i.e. all possible trimming code combinations), and sends the plurality of different first trimming code combinations to the second input end of the core circuit 130 through the second output end. The core circuit 130 responds to the plurality of different first trimming code combinations and finally determines one of the plurality of first trimming code combinations as a target trimming code combination (i.e. the best trimming code combination) through performance analysis.

[0062] The physical trimming circuit 200 configures the package-level redistribution layer connection of the trimming pad 30 on the chip layer according to the target trimming code combination, so as to realize the discrete trimming of the chip.

[0063] Based on the above design, the existing wafer-level trimming method for analog chips usually increases the production cost and cycle of the device. The present application proposes a discrete chip trimming system 10 with lower cost, which is suitable for integrated circuit packaging types using a package-level redistribution layer. By introducing a test mode (Test Mode) in the circuit, only one test mode pin 110 and the existing test input pin 20 of the chip need to be reused, so that the influence of all possible trimming code combinations on the circuit performance can be tested without modifying the wafer or packaging structure, and the hardware cost is very low, so that the target trimming code combination can be found. The target trimming code combination determined during the test mode process will be applied to the chip packaging stage. The trimming pads 30 on the wafer are connected and configured according to the target trimming code combination through the package-level redistribution layer to set the required control level, and finally the discrete trimming of the chip is realized. The present application does not depend on any specific process option, test or trimming technology (such as large current, high voltage or laser cutting), and can test all trimming code combinations before performing the final trimming, so that the time and cost of chip production are reduced under the premise of ensuring trimming accuracy.

[0064] It should be noted that the test input pin 20 not only supports the input of original signals in the normal working mode, but also can receive a plurality of different configuration voltages in the test mode and send them to the selection circuit 120, so as to generate the corresponding first trimming code combination through the selection circuit 120, and finally screen out the target trimming code combination. That is, the test input pin 20 in the present application adopts a multiplexing design and can flexibly support two working modes, which not only effectively reduces the cost of the chip, but also realizes the mutual non-interference between the chip trimming function and the normal working mode.

[0065] Specifically, when the test mode pin 110 is not enabled (for example, the test mode pin 110 is at a low level 0), the first output of the selection circuit 120 sends a normal operation mode command to the first input of the core circuit 130 so that the core circuit 130 enters the normal operation mode.

[0066] When the core circuit 130 enters normal operating mode, the test input pin 20 sends the original input signal to the selection circuit 120. The selection circuit 120 selects the second trimming code combination input from the trimming pad 30 as the output, and sends the second trimming code combination to the second input terminal of the core circuit 130 through its second output terminal. The core circuit 130 then operates normally based on the received second trimming code combination.

[0067] To better understand, the following will be combined with... Figure 2 and Figure 3 The trimming and testing circuit 100 provided in the embodiments of this application will be described in detail first.

[0068] like Figure 2 As shown, in one optional embodiment, the selection circuit 120 includes a trimming selection module 121 and a mode selection module 122. The first, second, and third input terminals of the trimming selection module 121 are connected to the test mode pin 110, the test input pin 20, and the trimming pad 30, respectively. The first and second output terminals of the trimming selection module 121 are connected to the first input terminal of the mode selection module 122 and the second input terminal of the core circuit 130, respectively. The second input terminal of the mode selection module 122 is connected to the test mode pin 110, and the output terminal of the mode selection module 122 is connected to the first input terminal of the core circuit 130.

[0069] When test mode pin 110 is enabled (i.e., test mode), mode selection module 122 outputs a test mode command to core circuit 130 based on the signals received from the first and second input terminals and the default test mode value, so that core circuit 130 enters test mode. Trimming selection module 121 processes the various signals output from test input pin 20 in test mode to obtain various combinations of first trimming codes, and sends these combinations to core circuit 130 through the second output terminal, thereby filtering for target trimming code combinations.

[0070] When the test mode pin 110 is not enabled (i.e. normal working mode), the trimming selection module 121 processes the signal output by the test input pin 20 in the normal working mode and sends the processed signal to the first input end of the mode selection module 122 through the first output end. The mode selection module 122 outputs a normal working mode instruction to the core circuit 130 according to the signals received by the first input end and the second input end and the test mode default value, so that the core circuit 130 enters the normal working mode. The trimming selection module 121 selects the second trimming code combination input by the trimming pad 30 as the output and sends the second trimming code combination to the core circuit 130 through the second output end, so as to work normally.

[0071] It should be noted that the test mode instruction or the normal working mode instruction output by the mode selection module 122 is obtained by comprehensive determination according to the signal received by the first input end, the signal received by the second input end and the test mode default value, and is used to instruct the core circuit 130 to enter the corresponding working state.

[0072] Further, please refer to Figure 3 In another optional embodiment, the trimming selection module 121 comprises a signal processor 1211, an analog-digital converter 1212, a switch K and a multiplexer 1213.

[0073] The test input pin 20 is connected with the input end of the signal processor 1211 and one end of the switch K respectively, the output end of the signal processor 1211 is connected with the first input end of the mode selection module 122, the other end of the switch K is connected with the input end of the analog-digital converter 1212, the output end of the analog-digital converter 1212 is connected with the first data input end of the multiplexer 1213. The trimming pad 30 is connected with the second data input end of the multiplexer 1213, the output end of the multiplexer 1213 is connected with the second input end of the core circuit 130. The test mode pin 110 is connected with the control end of the switch K, the control end OE of the signal processor 1211, the control end of the multiplexer 1213 and the second input end of the mode selection module 122 respectively.

[0074] When the test mode pin 110 is enabled (i.e. the test mode pin 110 is high 1), the signal processor 1211 is disabled, the switch K is closed, and the mode selection module 122 sends a test mode instruction to the first input end of the core circuit 130, so that the core circuit 130 enters the test mode. The analog-to-digital converter 1212 converts the plurality of different analog voltage signals output by the test input pin 20 in the test mode into digital signals respectively, to obtain a plurality of different first trimming code combinations. The multiplexer 1213 receives the plurality of different first trimming code combinations received by the first data input end as output under the control of the test mode pin 110, and sends them to the second input end of the core circuit 130, so as to screen the target trimming code combination.

[0075] When the test mode pin 110 is not enabled (i.e. the test mode pin 110 is low 0), the switch K is opened, the signal processor 1211 processes the signal output by the test input pin 20 in the normal working mode, and sends the processed signal to the first input end of the mode selection module 122. The mode selection module 122 sends a normal working mode instruction to the first input end of the core circuit 130, so that the core circuit 130 enters the normal working mode. The multiplexer 1213 receives the second trimming code combination input by the trimming pad 30 as output under the control of the test mode pin 110, and sends it to the second input end of the core circuit 130, so that the chip works normally.

[0076] It can be understood that in the normal working mode, the signal output by the test input pin 20 can be an analog signal or a digital signal. In the test mode, the test input pin 20 is multiplexed as the input end of the analog-to-digital converter 1212 to output a plurality of different analog signals. After conversion by the analog-to-digital converter 1212, a plurality of different multi-bit first trimming code combinations (i.e. digital signals) are generated. This design ensures that all possible trimming bit configurations (i.e. a plurality of different first trimming code combinations) can be comprehensively tested before the final trimming (i.e. package-level re-distribution) is performed, so as to determine the target trimming code combination.

[0077] For example, in the normal working mode, the test input pin 20 can be used as an external bias voltage pin of the mode selection module 122. After entering the test mode, the mode selection module 122 switches to internal bias, at which time the test input pin 20 is no longer used for external bias, and therefore the test input pin 20 can be multiplexed as the input signal end of the analog-to-digital converter 1212. This multiplexing design optimizes the utilization rate of the pins, improves the test flexibility, and reduces the trimming cost of the chip.

[0078] After the target trim code combination is determined, the chip packaging stage is entered. In the chip packaging process, the physical trim circuit 200 connects the trim pads 30 of the chip layer to the power supply pads or the ground pads of the packaging layer through the packaging-level redistribution according to the trim default value and the target trim code combination, so that the discrete trim of the chip is realized.

[0079] For better understanding, the following will be described in combination with Figure 4 and Figure 5 The physical trim circuit 200 will be described in detail.

[0080] In the embodiment of the present application, each trim bit in the target trim code combination is programmed through the metal connection of the packaging-level redistribution. In the chip layer, all the trim pads 30 are connected to the power supply pads or the ground pads of the packaging layer through the pull-up resistor Rpu or the pull-down resistor Rpd according to the corresponding trim default value (the trim default value can be 0 or 1).

[0081] In an alternative embodiment, referring to Figure 4 , the physical trim circuit 200 includes the pull-down resistor Rpd. When the trim default value is 0, the chip layer ground pad GND1 is connected to the packaging layer ground pad GND2 through the first redistribution connection layer RDL VIA1, and one end of the pull-down resistor Rpd is connected to the corresponding trim pad 30, and the other end of the pull-down resistor Rpd is connected to the chip layer ground pad GND1. The pull-down resistor Rpd is used to pull down the trim bit of the trim pad 30 to 0.

[0082] Further, when the trim default value is 0 and the corresponding target trim value in the target trim code combination is 1, the trim pad 30 is connected to the packaging layer power supply pad VDD2 through the second redistribution connection layer RDL VIA2, so as to realize the modification of the trim bit from 0 to 1.

[0083] When the trim default value is 0 and the corresponding target trim value in the target trim code combination is 0, the present application provides two trim methods. The first trim method is that the trim pad 30 is still connected to the packaging layer ground pad GND2 through the pull-down resistor Rpd and the first redistribution connection layer RDL VIA1. The second trim method is that the trim pad 30 is connected to the packaging layer ground pad GND2 through the second redistribution connection layer RDL VIA2.

[0084] It should be noted that, compared with the first trimming method, the trimming pad 30 in the second trimming method is double-grounded (equivalent to connecting two "0" potential points), thereby reducing the impedance and enhancing the electrical stability. This design not only avoids the risk of electromagnetic interference or static accumulation caused by the hanging pin, but also improves the reliability of the package through the redundant grounding path. Therefore, the second trimming method not only ensures the full connection of the package pin, but also provides higher safety and noise suppression capability, especially suitable for high-frequency or high-sensitivity application scenarios.

[0085] In another alternative embodiment, referring to Figure 5 , the physical trimming circuit 200 includes a pull-up resistor Rpu. When the trimming default value is 1, the chip layer power supply pad VDD1 is connected with the package layer power supply pad VDD2 through the third redistribution layer connection RDL VIA3, and one end of the pull-up resistor Rpu is connected with the corresponding trimming pad 30, and the other end of the pull-up resistor Rpu is connected with the chip layer power supply pad VDD1. The pull-up resistor Rpu is used to pull up the trimming bit of the trimming pad 30 to 1.

[0086] Further, when the trimming default value is 1 and the corresponding target trimming value in the target trimming code combination is 0, the trimming pad 30 is connected with the package layer ground pad GND2 through the fourth redistribution layer connection RDL VIA4, thereby realizing the modification of the trimming bit from 1 to 0.

[0087] When the trimming default value is 1 and the corresponding target trimming value in the target trimming code combination is 1, the present embodiment provides two trimming methods. One is that the trimming pad 30 is still connected with the package layer power supply pad VDD2 through the pull-up resistor Rpu and the third redistribution layer connection RDL VIA3. The other is that the trimming pad 30 is connected with the package layer power supply pad VDD2 through the fourth redistribution layer connection RDL VIA4.

[0088] Based on the above circuit design, in the form of a bare die configuration or a package (such as DIP, etc.), the trimming pad 30 needs to be connected to the power supply pad or the ground pad of the package layer through wire-bonding to set the required control level. The trimmed trimming pad 30 sends the corresponding signal to the core circuit 130 through the input buffer, thereby ensuring the normal work of the chip. The present application allows different trimming code chip versions to be realized only by changing the package level RDL mask, and the programming of the trimming bit can be completed without any modification at the wafer level, without modifying the front-end mask design, thereby significantly reducing the chip development and manufacturing cost.

[0089] In addition, in terms of time cost of the present application: (1) if wafer-level testing is performed, the time cost mainly comes from the testing time for determining the target trim code combination. Physical trimming does not increase additional time cost because the trimming is completed in the chip packaging process. (2) If package-level testing is performed, the time cost includes the sum of the testing time for determining the target trim code combination and the packaging time of the new chip.

[0090] That is, compared with the existing analog circuit trimming technology, the chip trimming system 10 provided by the embodiments of the present application can significantly reduce the time and cost of chip production while ensuring trimming accuracy.

[0091] Further, referring to Figure 6 The embodiments of the present application also provide a chip trimming method, which is applied to the chip trimming system 10 as described in any of the preceding embodiments, and the method comprises the following steps:

[0092] Step S100: When the test mode pin is enabled, the selection circuit sends a test mode instruction to the core circuit through the first output end, so that the core circuit enters the test mode.

[0093] Step S200: When the core circuit enters the test mode, the test input pin inputs a plurality of different signals to the selection circuit; the selection circuit processes the plurality of different signals to obtain a plurality of different first trim code combinations, and sends the plurality of different first trim code combinations to the core circuit through the second output end; the core circuit responds to the plurality of different first trim code combinations to evaluate and determine a target trim code combination.

[0094] Step S300: The physical trimming circuit configures the package-level rewire connection of the trimming pads on the chip layer according to the target trim code combination.

[0095] In summary, the embodiment of the present application provides a chip trimming system and method. The system comprises a trimming test circuit and a physical trimming circuit. The trimming test circuit comprises a test mode pin, a selection circuit and a core circuit. The present application introduces a test mode in the circuit. Only one test mode pin and the existing test input pin of the chip are needed to test the influence of all possible trimming code combinations on the circuit performance without modifying the wafer or packaging structure and with low hardware cost, so as to find the target trimming code combination. The target trimming code combination determined in the test mode process will be applied to the chip packaging stage. The trimming pads on the wafer are connected and configured according to the target trimming code combination through the packaging level redistribution layer to set the required control level, so as to finally realize the discrete trimming of the chip. The present application does not depend on any specific process option, test or trimming technology (such as large current, high voltage or laser cutting), and can test all trimming code combinations before performing the final trimming, thereby realizing the reduction of the time and cost of chip production under the premise of ensuring the trimming accuracy.

[0096] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0097] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, but can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims.

Claims

1. A chip trimming system, characterized in that, include: Repair and test circuits and physically repair circuits; The trimming test circuit includes test mode pins, a selection circuit, and a core circuit. The first, second, and third input terminals of the selection circuit are respectively connected to the test mode pin, the chip's test input pin, and the trimming pad; the first and second output terminals of the selection circuit are respectively connected to the first and second input terminals of the core circuit; and the physical trimming circuit is connected to the trimming pad. When the test mode pin is enabled, the selection circuit is used to send a test mode command to the core circuit through the first output terminal so that the core circuit enters the test mode. When the core circuit enters the test mode, the test input pin is used to input multiple different signals to the selection circuit; the selection circuit is also used to process the multiple different signals to obtain multiple different first trimming code combinations, and send the multiple different first trimming code combinations to the core circuit through the second output terminal; the core circuit is used to evaluate the response of the multiple different first trimming code combinations to determine the target trimming code combination; The physical trimming circuit is used to configure package-level rewiring connections for the trimming pads of the chip layer according to the target trimming code combination.

2. The chip trimming system according to claim 1, characterized in that, When the test mode pin is not enabled, the selection circuit is used to send a normal operation mode command to the core circuit through the first output terminal so that the core circuit enters the normal operation mode. When the core circuit enters normal operating mode, the selection circuit is used to select the second trimming code combination input by the trimming pad as the output, and send the second trimming code combination to the core circuit through the second output terminal; the core circuit is used to perform normal operation according to the received second trimming code combination.

3. The chip trimming system according to claim 1, characterized in that, The selection circuit includes a trimming selection module and a mode selection module; The first, second, and third input terminals of the trimming selection module are respectively connected to the test mode pin, the test input pin, and the trimming pad; the first and second output terminals of the trimming selection module are respectively connected to the first input terminal of the mode selection module and the second input terminal of the core circuit; the second input terminal of the mode selection module is connected to the test mode pin, and the output terminal of the mode selection module is connected to the first input terminal of the core circuit. When the test mode pin is enabled, the mode selection module is used to output a test mode command to the core circuit according to the signals received by the first input terminal and the second input terminal and the default value of the test mode; the trimming selection module is used to process the various signals output by the test input pin in the test mode to obtain various different combinations of first trimming codes, and send the various different combinations of first trimming codes to the core circuit through the second output terminal. When the test mode pin is not enabled, the trimming selection module processes the signal output by the test input pin in normal working mode and sends the processed signal to the first input of the mode selection module through the first output terminal; the mode selection module outputs a normal working mode command to the core circuit according to the signals received by the first and second input terminals and the default test mode value; the trimming selection module is also used to select the second trimming code combination input by the trimming pad as the output and send the second trimming code combination to the core circuit through the second output terminal.

4. The chip trimming system according to claim 3, characterized in that, The trimming selection module includes a signal processor, an analog-to-digital converter, a switch, and a multiplexer; The test input pins are connected to the input terminal of the signal processor and one end of the switch, respectively. The output terminal of the signal processor is connected to the first input terminal of the mode selection module. The other end of the switch is connected to the input terminal of the analog-to-digital converter (ADC). The output terminal of the ADC is connected to the first data input terminal of the multiplexer. The trimming pad is connected to the second data input terminal of the multiplexer. The output terminal of the multiplexer is connected to the second input terminal of the core circuit. The test mode pins are connected to the control terminal of the switch, the control terminal of the signal processor, the control terminal of the multiplexer, and the second input terminal of the mode selection module, respectively. When the test mode pin is enabled, the signal processor is disabled, the switch is closed, and the mode selection module is used to send a test mode command to the first input terminal of the core circuit. The analog-to-digital converter is used to convert the various analog signals output by the test input pin in test mode into digital signals to obtain various different combinations of first trimming codes. The multiplexer is used to take the various different combinations of first trimming codes received by the first data input terminal as outputs and send them to the second input terminal of the core circuit. When the test mode pin is not enabled, the switch is turned off, the signal processor processes the signal output by the test input pin in normal working mode, and sends the processed signal to the first input terminal of the mode selection module; the mode selection module sends a normal working mode command to the first input terminal of the core circuit; the multiplexer combines the second trimming code input by the trimming pad as output and sends it to the second input terminal of the core circuit.

5. The chip trimming system according to claim 1, characterized in that, The physical trimming circuit is used to connect the trimming pads of the chip layer to the power pads or ground pads of the package layer through package-level rewiring, based on the trimming default value and the target trimming code combination.

6. The chip trimming system according to claim 5, characterized in that, The physical trimming circuit includes a pull-down resistor; when the trimming default value is 0, the chip layer ground pad is connected to the package layer ground pad through the first rewiring connection layer, and one end of the pull-down resistor is connected to the trimming pad, and the other end of the pull-down resistor is connected to the chip layer ground pad. The pull-down resistor is used to pull down the trimming position of the trimming pad to 0.

7. The chip trimming system according to claim 6, characterized in that, When the trimming default value is 0 and the target trimming value corresponding to the target trimming code combination is 1, the trimming pad is connected to the package layer power pad through the second wiring connection layer. When the trimming default value is 0 and the target trimming value corresponding to the target trimming code combination is 0, the trimming pad is connected to the package layer ground pad through the second rewiring connection layer, or the trimming pad is connected to the package layer ground pad through the pull-down resistor and the first rewiring connection layer.

8. The chip trimming system according to claim 5, characterized in that, The physical trimming circuit includes a pull-up resistor; when the trimming default value is 1, the chip layer power pad is connected to the package layer power pad through the third wiring connection layer, and one end of the pull-up resistor is connected to the trimming pad, and the other end of the pull-up resistor is connected to the chip layer power pad. The pull-up resistor is used to pull up the trimming position of the trimming pad to 1.

9. The chip trimming system according to claim 8, characterized in that, When the trimming default value is 1 and the target trimming value corresponding to the target trimming code combination is 0, the trimming pad is connected to the encapsulation layer ground pad through the fourth wiring connection layer. When the trimming default value is 1 and the target trimming value corresponding to the target trimming code combination is 1, the trimming pad is connected to the package layer power pad through the fourth routing connection layer, or the trimming pad is connected to the package layer power pad through the pull-up resistor and the third routing connection layer.

10. A chip trimming method, characterized in that, The chip trimming method is applied to the chip trimming system as described in any one of claims 1-9, the method comprising: When the test mode pin is enabled, the selection circuit sends a test mode command to the core circuit through the first output terminal, so that the core circuit enters the test mode. When the core circuit enters the test mode, the test input pin inputs multiple different signals to the selection circuit; the selection circuit processes the multiple different signals to obtain multiple different first trimming code combinations, and sends the multiple different first trimming code combinations to the core circuit through the second output terminal; the core circuit evaluates the response of the multiple different first trimming code combinations to determine the target trimming code combination; The physical trimming circuit configures the package-level rewiring connection of the trimming pads on the chip layer according to the target trimming code combination.

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