An improved automatic detection of transmission direction level shifting circuit

Abstract

The application discloses an improved automatic detection transmission direction level conversion circuit, and relates to the technical field of chip power supply. The structure of the level conversion circuit is two groups of transmission circuits which are symmetrically arranged. The two groups of transmission circuits can realize bidirectional transmission of signals. The first transmission circuit comprises a port. The port sends signals to the second transmission circuit through a level converter and receives signals of the second transmission circuit through an impedance driver and an edge acceleration control module. The level converter converts input signals into signals of corresponding level domains. A high-impedance path is arranged in the impedance driver. A low-impedance path is arranged in the edge acceleration control module, so that the matching problem of different levels of a main control chip and an interface chip is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip power supply, and particularly to an improved level conversion circuit capable of automatically detecting transmission direction. BACKGROUND

[0002] The development of modern electronic technology leads to the gradual reduction of the supply voltage and core voltage of CPU / MCU and other main control chips. However, in the conventional application environment, the signals of the main control chip are generally not directly used, but different interface chips are used to meet the corresponding application environment. In this case, there is a problem of matching different levels of the main control chip and the interface chip.

[0003] At the same time, due to the promotion of the intelligentization of equipment, the number of IOs of the main control chip is also relatively tight. SUMMARY

[0004] Therefore, the present application provides an improved level conversion circuit capable of automatically detecting transmission direction to solve the problem of matching different levels of the main control chip and the interface chip.

[0005] The present application provides an improved level conversion circuit capable of automatically detecting transmission direction, which comprises two groups of transmission circuits symmetrically arranged, and the two groups of transmission circuits can perform bidirectional transmission of signals. The port of the first transmission circuit is set as an A end, the A end sends signals to the second transmission circuit through a level converter A, and receives signals of the second transmission circuit through an impedance driver A and an edge acceleration control module A. The port of the second transmission circuit is set as a B end, the B end sends signals to the first transmission circuit through a level converter B, and receives signals of the first transmission circuit through an impedance driver B and an edge acceleration control module B. Wherein, the level converter A and the level converter B are the same devices, which can convert the input signals into signals of corresponding level domains; the impedance driver A and the impedance driver B are the same devices, which set a high-impedance path and provide static driving capability for the output signals; and the edge acceleration control module A and the edge acceleration control module B are the same devices, which set a low-impedance path and are closed after the signal conversion is completed.

[0006] For example, in the level conversion circuit provided by at least one embodiment of the present disclosure, the edge acceleration control module A includes two signal input ends and two signal output ends; the first signal input end receives a signal of the A end, and the second signal input end receives a signal of the B end; the first signal output end sends a signal to the A end through a MOS tube PM1, and the second signal output end sends a signal to the A end through a MOS tube NM1; the edge acceleration control module B includes two signal input ends and two signal output ends; the first signal input end receives a signal of the B end, and the second signal input end receives a signal of the A end; the first signal output end sends a signal to the B end through a MOS tube PM2, and the second signal output end sends a signal to the B end through a MOS tube NM2.

[0007] For example, in the level conversion circuit provided by at least one embodiment of the present disclosure, the MOS tube PM1 is configured to have the gate connected to the first signal output end of the edge acceleration control module A, the source connected to a power supply VCC1, and the drain connected to the drain of the MOS tube NM1; the MOS tube NM1 is configured to have the gate connected to the second signal output end of the edge acceleration control module A and the source grounded; and the common end of the drains of the MOS tube PM1 and the MOS tube NM1 is connected to the A end.

[0008] For example, in the level conversion circuit provided by at least one embodiment of the present disclosure, the MOS tube PM2 is configured to have the gate connected to the first signal output end of the edge acceleration control module B, the source connected to a power supply VCC2, and the drain connected to the drain of the MOS tube NM2; the MOS tube NM2 is configured to have the gate connected to the second signal output end of the edge acceleration control module B and the source grounded; and the common end of the drains of the MOS tube PM2 and the MOS tube NM2 is connected to the B end.

[0009] For example, in the level conversion circuit provided by at least one embodiment of the present disclosure, the level converter A includes one signal input end and two signal output ends; the signal input end receives a signal of the A end; the first signal output end sends a processed signal to the edge acceleration control module B, and the second signal output end sends a processed signal to the impedance driver B; and the level converter B includes one signal input end and two signal output ends; the signal input end receives a signal of the B end; the first signal output end sends a processed signal to the edge acceleration control module A, and the second signal output end sends a processed signal to the impedance driver A.

[0010] For example, in the level conversion circuit provided by at least one embodiment of the present disclosure, the level converter A is connected to the power supply VCC2 in the second transmission circuit; and the level converter B is connected to the power supply VCC1 in the first transmission circuit. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on the provided drawings.

[0012] Figure 1 is a schematic diagram of a level conversion circuit provided by at least one embodiment of the present disclosure;

[0013] Figure 2 is a circuit diagram of a level shifter provided by at least one embodiment of the present disclosure;

[0014] Figure 3 is a circuit diagram of an impedance driver provided by at least one embodiment of the present disclosure;

[0015] Figure 4 is a circuit diagram of an edge acceleration control module provided by at least one embodiment of the present disclosure;

[0016] Figure 5 is a N_SPDUP signal waveform diagram provided by at least one embodiment of the present disclosure;

[0017] Figure 6 is a P_SPDUP signal waveform diagram provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.

[0019] In the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0020] Embodiment

[0021] The matching problem of different levels of main control chips and interface chips in the prior art is mainly handled by the scheme disclosed in CN118100905A, a level conversion circuit for automatically detecting transmission direction. However, the main problem of this structure is the possibility of burning the chip or increasing system power consumption.

[0022] In the newly designed circuit of the present disclosure, there are mainly impedance drivers, level converters, and edge acceleration control modules. The main function of the level converter is to convert the input signal into a signal corresponding to the corresponding level domain. The main function of the impedance driver is to provide a high impedance path to facilitate the conversion of the input signal to high and low levels without generating additional power consumption or burning the chip, and to provide static driving capability for the output signal. The main function of the edge acceleration control module is to provide a low impedance path during the conversion process of the signal from low to high or from high to low to accelerate signal conversion, and to be closed after the signal conversion is completed to avoid conflict with the input signal.

[0023] Since the circuit structure is symmetrical, the working process inside the chip is similar whether the signal is transmitted from the A end to the B end or from the B end to the A end. Therefore, the present disclosure analyzes the case of A end as input signal, and the case of B end as input can be obtained by mirroring.

[0024] The change of the signal can be divided into two types, one is the conversion from low level to high level, and the other is the conversion from high level to low level. In a complete process, it can be divided into four stages, which are defined as PHASE1, PHASE2, PHASE3, and PHASE4. PHASE1 is defined as the stage before conversion, A end low level, B end low level, PHASE2 is defined as the stage during conversion, A end high level, B end low level, PHASE3 is defined as the stage after conversion, A end high level, B end high level, and PHASE4 is defined as the stage during conversion, A end low level, B end high level. By defining the above four stages, the signal will always be in these four states.

[0025] The first stage PHASE1 of the first round:

[0026] As Figure 1When the A terminal accesses a signal source and is at a low level, the input signal is converted to a signal in a corresponding level domain by the level conversion module A, i.e., a logic noninversion signal A2 corresponding to a power supply VCC2 and a logic inversion signal A2_n are generated. The logic inversion signal A2_n drives the impedance driver B to set the B terminal to a low level. When the B terminal is set to a low level, the same level conversion module B generates a logic noninversion signal B1 corresponding to a power supply VCC1 and a logic inversion signal B1_n. The logic inversion signal B1_n drives the impedance driver A to keep the A terminal at a low level. In this process, since the internal resistance of the two impedance drivers A is much greater than the internal resistance of the signal source, the signal at the A terminal is always at a low level, and the power consumption is not increased.

[0027] Preferably, Figure 4 is a circuit diagram of an edge acceleration control module provided by at least one embodiment of the present disclosure. Since the edge acceleration control module A and the edge acceleration control module B are the same device, the present disclosure uses one Figure 4 to represent both of them.

[0028] It should be noted that: Figure 4 The power supply VCC is a general representation. If Figure 4 represents the edge acceleration control module A, the value of the power supply VCC is the power supply VCC1, and vice versa. If Figure 4 represents the edge acceleration control module B, the value of the power supply VCC is the power supply VCC2.

[0029] Similarly, the power supply VCC appears in other circuit diagrams, and the same explanation applies.

[0030] The more important signal states in the edge acceleration control module B are as follows: NET1 is 1, NET2 is 0, NET3 is 0, NET4 is 1, NET5 is 0, and NET6 is 0.

[0031] NET1 is 1, causing the output P_SPDUP of the OR gate to be high, and NET6 is 0, causing the output N_SPDUP of the AND gate to be low. Since the edge acceleration control module uses the same power supply VCC1 and VCC2, the input logic is also the same.

[0032] Therefore, in the level conversion circuit as shown in Figure 1 , the output N_SPDUP of the AND gate, which is the second signal output terminal of the edge acceleration control module A and the edge acceleration control module B, is low, and is represented by N_SPDUP_A and N_SPDUP_B respectively; the output P_SPDUP of the OR gate, which is the first signal output terminal of the edge acceleration control module A and the edge acceleration control module B, is high, and is represented by P_SPDUP_A and P_SPDUP_B respectively, so that the MOS tubes PM1, NM1, PM2, and NM2 are closed.

[0033] The second phase of the first round PHASE2:

[0034] When the A-side signal is converted from low to high, the level shifter A generates a logic inverse signal A2_n, which is converted from high to low, so that the impedance driver B outputs are converted from low to high. However, due to the insufficient driving capability of the impedance driver B, the signal speed is not fast enough, so there is a state where the A-side level is high and the B-side level is low. At this time, the edge acceleration control module B needs to drive the MOS tube PM2 to accelerate the edge of the B-side signal and improve the conversion speed of the signal.

[0035] The working process of the edge acceleration control module B is as follows:

[0036] In this case, the state of each signal is as follows: NET1 becomes 0, NET2 becomes 1 after delay, NET3 becomes 1 after delay, NET4 remains 1, NET5 remains 0, and NET6 remains 0.

[0037] As shown in Figure 4 Based on the above signal conditions, since NET1 changes from 1 to 0, NET3 is NET1, and changes from 0 to 1 after a delay t1 of MOS tube PM1, resistor R1, inverter INV1, and INV2, the input of OR gate is 0 during the t1 time period, resulting in P_SPDUP output of 0, thereby opening the MOS tube PM2 to accelerate the rising of the B-side signal. After the t1 time period, NET3 changes to 1, resulting in the output P_SPDUP of the OR gate changing to 1, thereby automatically turning off the MOS tube PM2. The same situation occurs at the A-side, but the signal at the A-side has already changed to high, and the opening of the MOS tube PM1 does not affect the signal at the A-side.

[0038] During this process, NET6 remains 0, so that the output N_SPDUP of the AND gate is still low. Since the acceleration modules at the A-side and the B-side have the same logic, N_SPDUP_A and N_SPDUP_B are low, ensuring that the MOS tubes NM1 and NM2 remain closed.

[0039] The third phase of the first round PHASE3:

[0040] After the B-side signal goes through the PHASE1 and PHASE2 stages, the low-to-high conversion is completed, and the impedance driver B is responsible for maintaining the high-level state.

[0041] In the edge acceleration control module B, the signal changes as follows: NET1 remains 0, NET2 remains 1, NET3 remains 1, NET4 changes to 0, NET5 changes to 1, and NET6 changes to 1 after delay.

[0042] NET3 is 1, resulting in the output P_SPDUP of the OR gate being maintained at 1, and since the logic of the acceleration module at the A end and the B end is the same, P_SPDUP_A and P_SPDUP_B are high, causing MOS transistors PM1 and PM2 to be in the off state.

[0043] After NET4 becomes 0, NET6 is generated by NET4 after being delayed by MOS transistor PM2, inverter INV3 and inverter INV4 for t2, so there can be a time when NET4 and NET6 are both 1, but this can be avoided by adjusting the width-length ratio of MOS transistor PM2 to increase the speed of the rising edge of NET5 as much as possible, to avoid the output of the AND gate generating a high-level spike pulse and to avoid false conversion of the signal. By this adjustment, the output N_SPDUP of the AND gate can still be maintained at 0. Since the logic of the acceleration module at the A end and the B end is the same, N_SPDUP_A and N_SPDUP_B are low, causing MOS transistors NM1 and NM2 to be in the off state.

[0044] The fourth phase PHASE4 of the first round:

[0045] When the A end signal is converted from high to low, the level shifter A generates the logic inverse signal A2_n, which is converted from low to high, so the output of the impedance driver B is converted from high to low. However, due to the insufficient driving capability of the impedance driver B, the signal speed is not fast enough, so there is a state where the A end level is low and the B end level is high. At this time, the edge acceleration control module B needs to drive MOS transistor NM2 to accelerate the edge of the B end signal and improve the conversion speed of the signal.

[0046] The working process of the edge acceleration control module B is as follows:

[0047] In this case, the states of various signals are as follows: NET1 remains 0, NET2 remains 1, NET3 remains 1, NET4 becomes 1, NET5 becomes 0 after being delayed, and NET6 becomes 0 after being delayed.

[0048] As Figure 4As shown, based on the above signal conditions, since NET4 changes from 0 to 1, NET6 is NET4, and changes from 1 to 0 only after a delay t3 of MOS transistor NM2, resistor R2, inverter INV3 and inverter INV4, so the input of the AND gate is 1 in the t3 time period, resulting in the output of N_SPDUP being 1, thereby opening the MOS transistor NM2, so that the signal at the B end is accelerated to drop. After the t3 time period, NET6 changes to 0, resulting in the output N_SPDUP of the AND gate changing to 0, thereby automatically turning off the MOS transistor NM2. The same situation occurs at the A end, but the signal at the A end has already changed to low, and the opening of the MOS transistor NM1 does not affect the signal at the A end.

[0049] The output signal P_SPDUP of the OR gate remains 1 due to NET3 remaining 1, and since the acceleration module at the A end and the B end is logically the same, P_SPDUP_A and P_SPDUP_B being high causes the MOS transistors PM1 and PM2 to be in the off state.

[0050] The first phase PHASE1 of the second round:

[0051] When the signal at the B end goes through the PHASE3 and PHASE4 stages, the high-to-low conversion is completed, and the impedance driver B is responsible for maintaining the low level state.

[0052] In the edge acceleration control module B, the signal changes as follows: NET1 changes to 1, NET2 changes to 0 after a delay, NET3 changes to 0 after a delay, NET4 remains 0, NET5 remains 1, and NET6 remains 1.

[0053] NET4 being 0 causes the output N_SPDUP of AND1 to remain 0, and since the acceleration module at the A end and the B end is logically the same, N_SPDUP_A and N_SPDUP_B being low causes the MOS transistors NM1 and NM2 to be in the off state.

[0054] After NET1 changes to 1, NET3 is generated from NET1 after a delay t4 of NM1, inverter INV1 and inverter INV2, so there may be a time when NET1 and NET3 are both 0, but here the width-length ratio of the MOS transistor NM1 can be adjusted to increase the speed of the falling edge of NET2 as much as possible, to avoid the output of the OR gate generating a low-level spike pulse and to avoid signal errors. By this adjustment, the output P_SPDUP of the OR gate can still remain 1. Since the acceleration module at the A end and the B end is logically the same, P_SPDUP_A and P_SPDUP_B being low causes the MOS transistors PM1 and PM2 to be in the off state.

[0055] In combination Figure 5is a N_SPDUP signal waveform chart provided by at least one embodiment of the present disclosure; Figure 6 is a P_SPDUP signal waveform chart provided by at least one embodiment of the present disclosure; it can be seen that no matter the signal is converted from low level to high level or from high level to low level, the working state of the circuit is always in the four states of PHASE1, PHASE2, PHASE3 and PHASE4. And since the circuit is symmetrical, the structure transmission from A to B or from B to A actually has no effect on the above analysis process of the input signal, so the automatic conversion of the signal can be completely realized. In the level conversion circuit provided by at least one embodiment of the present disclosure, the circuit of the edge acceleration control module A or the edge acceleration control module B is configured as: the first signal input end is connected with the first input end of the NOR gate and the first input end of the NAND gate, and the second signal input end is connected with the second input end of the NOR gate and the second input end of the NAND gate; the output end of the NOR gate is connected with the second input end of the OR gate, the gate of the MOS tube NM3 and the MOS tube PM3, and the output end of the OR gate is connected with the first signal output end; the MOS tube PM3 is configured as: the source electrode is connected with the power supply VCC, the drain electrode is connected with the source electrode of the MOS tube NM3 through the resistor R1, and the drain electrode of the MOS tube NM3 is grounded; and the common end of the source electrode of the MOS tube NM3 and the resistor R1 is sequentially connected with the inverter INV1 and the inverter INV2; the output end of the inverter IVN2 is connected with the first input end of the OR gate; the output end of the NAND gate is connected with the first input end of the AND gate, the gate of the MOS tube NM4 and the MOS tube PM4, and the output end of the AND gate is connected with the second signal output end; the MOS tube PM4 is configured as: the source electrode is connected with the power supply VCC, the drain electrode is connected with the source electrode of the MOS tube NM4 through the resistor R2, and the drain electrode of the MOS tube NM4 is grounded; and the common end of the drain electrode of the MOS tube PM4 and the resistor R2 is sequentially connected with the inverter INV3 and the inverter INV4; the output end of the inverter INV4 is connected with the second input end of the AND gate.

[0056] In the level conversion circuit provided by at least one embodiment of the present disclosure, as shown in Figure 2 Figure 2 is a circuit diagram of a level converter provided by at least one embodiment of the present disclosure;

[0057] ​The circuit of the level converter A or the level converter B is configured as follows: the signal input end IN is connected to the input end of an inverter INV5 and the gate of a MOS transistor NM6; the output end of the inverter INV5 is connected to the gate of a MOS transistor NM5; the MOS transistor NM5 is configured as follows: the drain is connected to ground, the source is connected to the first signal output end OUT in sequence, the drain of a MOS transistor PM5, and the common end of the first signal output end OUT and the drain of the MOS transistor PM5 is connected to the gate of a MOS transistor PM6; the MOS transistor NM6 is configured as follows: the drain is connected to ground, the source is connected to the second signal output end OUT_n in sequence, the drain of the MOS transistor PM6, and the common end of the second signal output end OUT_n and the drain of the MOS transistor PM6 is connected to the gate of the MOS transistor PM5; the sources of the MOS transistors PM5 and PM6 are both connected to a power supply VCC.

[0058] In the level conversion circuit provided by at least one embodiment of the present disclosure, as shown in Figure 3 Figure 3 is a circuit diagram of an impedance driver provided by at least one embodiment of the present disclosure;

[0059] The circuit of the impedance driver is configured as follows: including MOS transistors PM7 and NM7, wherein the gates of the MOS transistors PM7 and NM7 are interconnected, and the common end of the gates is connected to a signal input end IN; wherein the drains of the MOS transistors PM7 and NM7 are interconnected, and the common end of the drains is connected to a signal output end OUT through a resistor R3; the source of the MOS transistor PM7 is connected to a power supply VCC

[0060] , and the source of the MOS transistor NM7 is connected to ground. The resistance value of the resistor R3 is greater than the internal resistance of a signal source;

[0061] The above process can clearly show the beneficial effects of the present scheme. The present circuit does not need to use an additional control pin to control the transmission direction of the signal, and can realize automatic detection and transmission of the signal. Professionals can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computing software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical scheme. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0062] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.​

[0063] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. An improved automatic direction of transmission detection level shifting circuit, characterized by, The level conversion circuit comprises two groups of transmission circuits symmetrically arranged, and the two groups of transmission circuits can perform bidirectional transmission of signals. The port of the first transmission circuit is set as an A end, the A end transmits signals to the second transmission circuit through a level converter A, and receives signals of the second transmission circuit through an impedance driver A and an edge acceleration control module A; The port of the second transmission circuit is set as a B end, the B end transmits signals to the first transmission circuit through a level converter B, and receives signals of the first transmission circuit through an impedance driver B and an edge acceleration control module B; wherein: The level converter A and the level converter B are the same devices, and can convert input signals into signals in a corresponding level domain; The impedance driver A and the impedance driver B are the same devices, and set a high-impedance path and provide static driving capability for output signals; The edge acceleration control module A and the edge acceleration control module B are the same devices, and set a low-impedance path and are closed after signal conversion is completed; The edge acceleration control module A comprises two signal input ends and two signal output ends; the first signal input end receives signals of the A end, and the second signal input end receives signals of the B end; the first signal output end transmits signals to the A end through a MOS tube PM1, and the second signal output end transmits signals to the A end through a MOS tube NM1; The edge acceleration control module B comprises two signal input ends and two signal output ends; the first signal input end receives signals of the B end, and the second signal input end receives signals of the A end; the first signal output end transmits signals to the B end through a MOS tube PM2, and the second signal output end transmits signals to the B end through a MOS tube NM2; The circuit of the edge acceleration control module A or the edge acceleration control module B is set as: The first signal input end is connected to a first input end of a NOR gate and a first input end of a NAND gate, and the second signal input end is connected to a second input end of the NOR gate and a second input end of the NAND gate; An output end of the NOR gate is connected to a second input end of an OR gate, a gate of a MOS tube NM3 and a MOS tube PM3, and an output end of the OR gate is connected to the first signal output end; The MOS tube PM3 is configured such that a source electrode is connected to a power supply VCC, a drain electrode is connected to a source electrode of the MOS tube NM3 through a resistor R1, and a drain electrode of the MOS tube NM3 is connected to ground; and a common end of the source electrode of the MOS tube NM3 and the resistor R1 is sequentially connected to an inverter INV1 and an inverter INV2; and an output end of the inverter INV2 is connected to a first input end of the OR gate; An output end of the NAND gate is connected to a first input end of an AND gate, a gate of a MOS tube NM4 and a MOS tube PM4, and an output end of the AND gate is connected to the second signal output end; The MOS tube PM4 is configured such that a source electrode is connected to the power supply VCC, a drain electrode is connected to a source electrode of the MOS tube NM4 through a resistor R2, and a drain electrode of the MOS tube NM4 is connected to ground; and a common end of the drain electrode of the MOS tube PM4 and the resistor R2 is sequentially connected to an inverter INV3 and an inverter INV4; and an output end of the inverter INV4 is connected to a second input end of the AND gate.

2. The improved automatic detection transmission direction level conversion circuit according to claim 1, wherein the MOS PM1 is configured with the gate connected to the first signal output end of the edge acceleration control module A, the source connected to the power supply VCC1, and the drain connected to the drain of the MOS NM1. The MOS NM1 is configured with the gate connected to the second signal output end of the edge acceleration control module A, and the source connected to the ground. The common end of the drains of the MOS PM1 and the MOS NM1 is connected to the A end.

3. The improved automatic detection transmission direction level conversion circuit according to claim 1, wherein the MOS PM2 is configured with the gate connected to the first signal output end of the edge acceleration control module B, the source connected to the power supply VCC2, and the drain connected to the drain of the MOS NM2. The MOS NM2 is configured with the gate connected to the second signal output end of the edge acceleration control module B, and the source connected to the ground. The common end of the drains of the MOS PM2 and the MOS NM2 is connected to the B end.

4. The improved automatic detection transmission direction level conversion circuit according to claim 1, wherein the level converter A comprises one signal input end and two signal output ends; the signal input end receives the A end signal; the first signal output end sends the processed transmission signal to the edge acceleration control module B, and the second signal output end sends the processed signal to the impedance driver B. The level converter B comprises one signal input end and two signal output ends; the signal input end receives the B end signal; the first signal output end sends the processed transmission signal to the edge acceleration control module A, and the second signal output end sends the processed signal to the impedance driver A.

5. The improved automatic detection transmission direction level conversion circuit according to claim 4, wherein the level converter A is connected to the power supply VCC2 in the second transmission circuit. The level converter B is connected to the power supply VCC1 in the first transmission circuit. The circuit of the level converter A or the level converter B is configured as follows: The signal input end IN is connected to the input end of the inverter INV5 and the gate of the MOS NM6; the output end of the inverter INV5 is connected to the gate of the MOS NM5. The MOS NM5 is configured with the drain connected to the ground, the source connected to the first signal output end OUT in sequence, the drain of the MOS PM5, and the common end of the first signal output end OUT and the drain of the MOS PM5 connected to the gate of the MOS PM6. The MOS NM6 is configured with the drain connected to the ground, the source connected to the second signal output end OUT_n in sequence, the drain of the MOS PM6, and the common end of the second signal output end OUT_n and the drain of the MOS PM6 connected to the gate of the MOS PM5; the sources of the MOS PM5 and PM6 are both connected to the power supply VCC.

6. An improved automatic detection of transmission direction level shifting circuit as claimed in claim 5, wherein, The circuit of the impedance driver is configured as follows: ​ ​ ​ 7. The improved automatic detection of transmission direction level shifting circuit according to claim 1, wherein, ​ The MOS PM7 and NM7 are connected at the gate, and the gate is connected to the signal input IN; the drain of the MOS PM7 and NM7 is connected, and the drain is connected to the signal output OUT through the resistance R3; the source of the MOS PM7 is connected to the power supply VCC, and the source of the MOS NM7 is connected to the ground.

8. The improved automatic detection of transmission direction level shifting circuit according to claim 7, wherein, The resistance R3 has a resistance value greater than the internal resistance of the signal source.

Images