Level conversion circuit and chip

Abstract

The application discloses a level conversion circuit and a chip. In the level conversion circuit, a signal receiving module is used for transmitting the first signal to the level conversion module; an enable control module is used for closing the enable function when the control signal is in a first state, and turning on the second power voltage when the control signal is in a second state, so that the input end of the first inverter is high, and the output end of the first inverter is low; and the level conversion module is used for performing level conversion on the first signal when the enable function of the enable control module is closed, so as to output the second signal adapted to the second power domain. The application can improve the function of the level conversion circuit and improve the application flexibility of the level conversion circuit.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a level conversion circuit and chip. Background Technology

[0002] In low-power chip design, signal communication across power domains is often required. Level conversion circuits are needed for this, allowing electrical signals from one power domain to be processed and output to adapt to the other. When the low-power design requires a power domain to be powered off, this level conversion circuit also needs to provide a fixed clamping value to the normally open power domain to ensure signal stability, correct function, and normal power consumption. Traditional solutions can achieve this level conversion function using two types of circuits: one is a traditional level conversion circuit with an output clamping value placed in the normally open power domain. This type of circuit is limited to the normally open power domain due to power supply constraints, which significantly restricts backend design implementation and physical integration. Figure 1a As shown, module A is a power-off module, and module B is a normally-on module in another power domain. Signals from module A to module B must be converted using a level-shifting circuit with clamping values. Figure 1a As shown in the ELS diagram, all ELS either must be placed within module B, or a separate physical area needs to be allocated within module A to set up the level shifting circuit; another type of circuit is a level shifting circuit with output clamping value that can be placed in the power-off area (i.e., module A), for example, reference... Figure 1b As shown, this circuit currently only clamps the output to "1" and does not have an output of "0". When a chip design encounters a more complex low-power design scheme, such as two functional modules that are completely independently powered on and off and communicate directly, the traditional level conversion circuit described above not only encounters limitations and troubles in the physical implementation process, such as defining independent power domains, but also encounters the problem of not being able to clamp the output to 0 when the power is off according to the functional design requirements. It can be seen that traditional level conversion circuits have limitations in application. Summary of the Invention

[0003] In view of this, this application provides a level conversion circuit and chip to solve the problem of limitations of traditional level conversion circuits in application.

[0004] This application provides a level conversion circuit, which includes a signal receiving module, an enable control module, a level conversion module, and a first inverter;

[0005] The first terminal of the signal receiving module is used to receive a first signal corresponding to the first power domain, and the second terminal is connected to the first terminal of the level conversion module; the first terminal of the enable control module is used to receive a control signal, the second terminal is used to receive a second power voltage corresponding to the second power domain, and the third terminal is connected to the second terminal of the level conversion module and the input terminal of the first inverter respectively; the third terminal of the level conversion module is grounded; the control signal is characterized as a first state when the first signal is in a stable state, and as a second state when the first signal is in a power-off state;

[0006] The signal receiving module is used to transmit the first signal to the level conversion module;

[0007] The enable control module is used to disable the enable function when the control signal is in the first state, and to turn on the second power supply voltage when the control signal is in the second state, so that the input terminal of the first inverter is at a high level and the output terminal of the first inverter is at a low level.

[0008] The level conversion module is used to perform level conversion on the first signal when the enable function of the enable control module is turned off, so as to output a second signal adapted to the second power domain.

[0009] Optionally, the second state includes a low level; the enable control module includes a buffer and a first transistor; the input terminal of the buffer serves as the first terminal of the enable control module, the output terminal is connected to the gate of the first transistor, the source of the first transistor serves as the second terminal of the enable control module, and the drain serves as the third terminal of the enable control module; the buffer is used to transmit the control signal to the gate of the first transistor; the first transistor is used to turn on when the control signal is low level to connect the second power supply voltage.

[0010] Optionally, the buffer includes an even number of inverters connected in series.

[0011] Optionally, the signal receiving module includes a second inverter and a third inverter; the input terminal of the second inverter serves as the first terminal of the signal receiving module, and the output terminal is connected to the input terminal of the third inverter; the output terminal of the third inverter serves as the second terminal of the signal receiving module.

[0012] Optionally, the level conversion module includes a signal conversion unit and at least one signal transmission unit; each of the signal transmission units is respectively disposed between each signal transmission point in the level conversion module, and is used to buffer the signal change state corresponding to each signal transmission point; the signal conversion unit is used to convert the first signal so that the converted signal is adapted to the second power domain.

[0013] Optionally, the signal conversion unit includes at least one second transistor connected in parallel; the drain of each second transistor serves as the first terminal of the signal conversion unit for receiving the first signal, the gate is used to receive the control signal, and the source is grounded.

[0014] Optionally, the at least one signal transmission unit includes a first signal transmission unit and a second signal transmission unit; the first end of the first signal transmission unit serves as the first end of the level conversion module, the second end serves as the second end of the level conversion module, the third end is used to connect to the second power supply voltage, and the fourth end is connected to the first end of the second signal transmission unit and the first end of the signal conversion unit respectively; the second end of the second signal transmission unit is connected to the output end of the second inverter, and the third end is used to connect to the second power supply voltage.

[0015] Optionally, each of the signal transmission units includes a multi-stage transistor connected in sequence.

[0016] Optionally, the level conversion circuit is located within the first power domain.

[0017] This application also provides a chip, which includes any of the above-described level conversion circuits.

[0018] The level conversion circuit and chip described in this application, by disabling the enable function when the control signal is in the first state, perform level conversion on the first signal and output a second signal adapted to the second power domain. This allows the level conversion circuit to stably perform level conversion between the first and second power domains when the first power domain is powered on. When the control signal is in the second state, the second power supply voltage is turned on, so that the input terminal of the first inverter is at a high level and the output terminal of the first inverter is at a low level. This level conversion circuit can stably output a low level when the first power domain is powered off. It can supplement the traditional low-power design circuit unit library with a level conversion circuit that can be placed in the power off region and has a low output clamp value. It solves the limitation that the original level conversion circuit unit with a low clamp value can only be placed in the normally open power region when a signal with a fixed low output is required in the power off region. It can improve the function of the level conversion circuit and enhance its application flexibility. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1aand Figure 1b This is a schematic diagram of the level conversion circuit setup during the research process of this application;

[0021] Figure 2 This is a schematic diagram of a level conversion circuit structure according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the level conversion circuit configuration in one embodiment of this application;

[0023] Figure 4 This is a schematic diagram of a level conversion circuit structure according to another embodiment of this application. Detailed Implementation

[0024] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0025] The first aspect of this application provides a level conversion circuit, which can be disposed within a chip having multiple power domains, and where signal conversion is required between the various power domains. (Reference) Figure 2 As shown, the level conversion circuit includes a signal receiving module 100, an enable control module 200, a level conversion module 300, and a first inverter N1.

[0026] The first terminal of the signal receiving module 100 is used to connect to the first signal I corresponding to the first power domain, and the second terminal of the signal receiving module 100 is connected to the first terminal of the level conversion module 300. The first terminal of the enable control module 200 is used to connect to the control signal NSLEEP, the second terminal of the enable control module 200 is used to connect to the second power supply voltage VDDS corresponding to the second power domain, and the third terminal of the enable control module 200 is connected to the second terminal of the level conversion module 300 and the input terminal of the first inverter N1. The third terminal of the level conversion module 300 is grounded. Figure 2 (Not shown in the diagram). The first inverter N1 may further include an output terminal and a power supply terminal. The output terminal can be used to output the second signal Z, and the power supply terminal can be used to connect to the second power supply voltage VDDS. Optionally, the control signal NSLEEP can follow the change of the first signal I. For example, the control signal NSLEEP can represent a first state when the first signal I is in a stable state (e.g., the power-on state of the first power domain), and a second state when the first signal I is in a power-off state (i.e., the power-off state of the first power domain).

[0027] The signal receiving module 100 is used to transmit the first signal I to the level conversion module 300 to ensure that the first signal I can be stably received and processed by the level conversion module 300, and to avoid the instability of the first signal I, such as sudden changes, affecting the stability of the level conversion operation.

[0028] The enable control module 200 is used to disable the enable function when the control signal NSLEEP is in the first state, and to connect the second power supply voltage VDDS when the control signal NSLEEP is in the second state, i.e., the first power domain is in a power-off state, so that the input terminal of the first inverter N1 is at a high level. At this time, the output terminal of the first inverter N1 is at a low level. This level conversion circuit can stably output a low level (i.e., 0 level) when the first power domain is in a power-off state.

[0029] The level conversion module 300 is used to perform level conversion on the first signal I when the enable function of the enable control module 200 is turned off, that is, when the first power domain is in the power-on state, so as to output a second signal Z adapted to the second power domain, thereby enabling the level conversion circuit to stably perform the level conversion work between the first power domain and the second power domain when the first power domain is in the power-on state.

[0030] The aforementioned level conversion circuit can be located within the first power domain, for example, reference... Figure 3 As shown, by simply connecting the normally open second power supply voltage VDDS to the enable control module 200, the level conversion between the first power domain and the second power domain can be performed when the first power domain is in the power-on state, and a low level can be stably output when the first power domain is in the power-off state. This can improve the level conversion function of the level conversion circuit and make the level conversion circuit have high stability in all states of the first power domain.

[0031] In some embodiments, the second state includes a low level (i.e., 0), and correspondingly, the first state includes a high level (i.e., 1). Reference Figure 4 As shown, the enable control module 200 includes a buffer B1 and a first transistor M22. The first transistor M22 can be a PMOS transistor.

[0032] The input terminal of buffer B1 serves as the first terminal of the enable control module 200, used to receive the control signal. The output terminal of buffer B1 is connected to the gate of the first transistor M22. Buffer B1 may also include a power supply terminal, which can be used to connect to the second power supply voltage VDDS corresponding to the second power domain. The source of the first transistor M22 serves as the second terminal of the enable control module 200, used to receive the second power supply voltage VDDS. The drain of the first transistor M22 serves as the third terminal of the enable control module 200, connected to the second terminal of the level conversion module 300 and the input terminal of the first inverter N1, respectively.

[0033] The buffer B1 is used to transmit the control signal NSLEEP to the gate of the first crystal M22 transistor, so as to buffer the control signal NSLEEP during the transmission process, making the output control signal NSLEEP more stable and reliable.

[0034] The first transistor M22 is turned on when the control signal NSLEEP is low to connect the second power supply voltage VDDS. Specifically, when NSLEEP=0, the first transistor M22 is turned on, and the second signal Z output by the first inverter N1 is 0, so that the level conversion circuit can clamp the output to 0 when the first power domain is powered down. When NSLEEP=1, the first transistor M22 is turned off, and the second signal Z output by the first inverter N1 is k*I, so that the level conversion circuit can stably perform the level conversion between the first power domain and the second power domain when the first power domain is powered on. Here, k represents the level conversion coefficient of the level conversion module 300. The level conversion coefficient k can be determined according to the level requirements between the first power domain and the second power domain. For example, the level conversion coefficient k can be 1.

[0035] Optionally, buffer B1 includes an even number of inverters connected in series, wherein the specific number of inverters can be set according to the signal buffering requirements of the enable control module 200. Optionally, the inverters here can be implemented using MOSFETs.

[0036] In some embodiments, such as Figure 4 As shown, the signal receiving module 100 includes a second inverter N2 and a third inverter N3. The input terminal of the second inverter N2 serves as the first terminal of the signal receiving module 100, used to receive the first signal I. The output terminal of the second inverter N2 is connected to the input terminal of the third inverter N3. The output terminal of the third inverter N3 serves as the second terminal of the signal receiving module 100, connected to the first terminal of the level conversion module 300. Both the second inverter N2 and the third inverter N3 may include power supply terminals, which can be used to receive the first power supply voltage VDD corresponding to the first power domain.

[0037] In this embodiment, the signal receiving module 100 uses a second inverter N2 and a third inverter N3 to transmit the first signal I, which makes the first signal I transmitted to the first terminal of the signal receiving module 100 more stable. Optionally, the second inverter N2 and the third inverter N3 can be implemented using MOSFETs.

[0038] In some embodiments, such as Figure 4 As shown, the level conversion module 300 includes a signal conversion unit 310 and at least one signal transmission unit ( Figure 4 (No symbols are shown in the text).

[0039] Each signal transmission unit is respectively set between each signal transmission point in the level conversion module 300 to buffer the signal change state corresponding to each signal transmission point, so that the signal conversion unit 310 can perform conversion processing on more reliable signals, thereby improving the reliability of the conversion processing work.

[0040] Optionally, the signal transmission points include signal input points (such as the first terminal of the level conversion module 300), voltage input points (such as the terminal in the level conversion module 300 where the second power supply voltage VDDS is connected), and / or signal output points (such as the second terminal of the level conversion module 300), so as to perform buffering and other processing on the signals input and / or output by the level conversion module 300, so that the signal conversion unit 310 can perform more stable level conversion (or switching) on ​​the corresponding signals.

[0041] The signal conversion unit 310 is used to convert the first signal I so that the converted signal is adapted to the second power domain.

[0042] In some examples, at least one signal transmission unit includes a first signal transmission unit and a second signal transmission unit. The first terminal of the first signal transmission unit serves as the first terminal of the level conversion module 300 and is connected to the second terminal of the signal receiving module 100. The second terminal of the first signal transmission unit serves as the second terminal of the level conversion module 300 and is connected to the third terminal of the enable control module 200 (i.e., the drain of the first transistor M22) and the input terminal of the first inverter N1, respectively. The third terminal of the first signal transmission unit is used to connect to the second power supply voltage VDDS. The fourth terminal of the first signal transmission unit is connected to the first terminal of the second signal transmission unit and the first terminal of the signal conversion unit 310, respectively. The second terminal of the second signal transmission unit is connected to the output terminal of the second inverter N2, and the third terminal of the second signal transmission unit is used to connect to the second power supply voltage VDDS. Further, the second terminal of the signal conversion unit 310 is connected to the output terminal of the buffer B1, and the third terminal of the signal conversion unit 310 serves as the third terminal of the level conversion module 300 and is connected to ground.

[0043] Specifically, each signal transmission unit may include multiple stages of transistors connected in sequence. These transistors may be pure digital CMOS transistors, and a level conversion circuit may be designed and built using pure digital CMOS transistors. This level conversion circuit may be made into a standard unit library, which will facilitate the flexible use of automated design tools.

[0044] Specifically, such as Figure 4 As shown, the first signal transmission unit includes a third transistor M2, a fourth transistor M3, and a fifth transistor M4; wherein the third transistor M2 and the fourth transistor M3 can constitute a first-stage transistor, and the fifth transistor M4 can constitute a second-stage transistor; the third transistor M2 and the fifth transistor M4 can be PMOS transistors, and the fourth transistor M3 can be an NMOS transistor. The second signal transmission unit includes a sixth transistor M5, a seventh transistor M6, and an eighth transistor M1; wherein the sixth transistor M5 and the seventh transistor M6 can constitute a first-stage transistor, and the eighth transistor M1 can constitute a second-stage transistor; the sixth transistor M5 and the eighth transistor M1 can be PMOS transistors, and the seventh transistor M6 can be an NMOS transistor.

[0045] The gate of the third transistor M2 serves as the first terminal of the first signal transmission unit, connected to the second terminal of the signal receiving module 100 and the gate of the fourth transistor M3. The source of the third transistor M2 can serve as the fifth terminal of the first signal transmission unit, connected to the drain of the eighth transistor M1 (which can be considered the fourth terminal of the second signal transmission unit). The drain of the third transistor M2 serves as the second terminal of the first signal transmission unit, connected to the drain of the first transistor M22, the input terminal of the first inverter N1, the drain of the fourth transistor M3, and the gate of the fifth transistor M4. The source of the fourth transistor M3 can serve as the fourth terminal of the first signal transmission unit, connected to the source of the seventh transistor M6 and the first terminal of the signal conversion unit 310. The source of the fifth transistor M4 can serve as the third terminal of the first signal transmission unit, used to connect to the second power supply voltage VDDS, and connected to the source of the eighth transistor M1 and the source of the first transistor M22. The drain of the fifth transistor M4 can serve as the sixth terminal of the first signal transmission unit, connected to the source of the sixth transistor M5 (which can be considered the fifth terminal of the second signal transmission unit). The gate of the sixth transistor M5 serves as the second terminal of the second signal transmission unit, and is connected to the output terminal of the second inverter N2 and the gate of the seventh transistor M6, respectively. The drain of the sixth transistor M5 is connected to the drain of the seventh transistor M6 and the gate of the eighth transistor M1, respectively.

[0046] In some examples, the signal conversion unit 310 includes at least one second transistor connected in parallel, such as a reference transistor. Figure 4 As shown, Figure 4The signal conversion unit shown includes a second transistor M11, which is an NMOS transistor. The drain of each second transistor can serve as the first terminal of the signal conversion unit 310, used to connect to the first signal I (or the first signal I after buffering by the signal transmission unit). The gate of each second transistor can serve as the second terminal of the signal conversion unit 310, used to connect to the control signal NSLEEP (or the control signal NSLEEP after buffering by buffer B1). The source of each second transistor can serve as the third terminal of the signal conversion unit 310, connected to ground. The number and size of the second transistors in the signal conversion unit 310 can be determined through simulation testing and other methods to ensure that the signal conversion parameters of the signal conversion unit 310 match the signal conversion requirements between the first and second power domains.

[0047] Optionally, the signal conversion function performed by the level conversion module 300 can also be called a level conversion function, which involves converting the first signal I output from the first power domain to output a second signal Z adapted to the second power domain. Specifically, when the control signal NSLEEP=1, the first transistor M22 is turned off. At this time, the two-stage inverter of the signal receiving module 100 can assist the level conversion module 300 through positive feedback to form a complete level conversion circuit, converting the first signal I into the second signal Z. The signal conversion unit 310 and other components in the level conversion module 300 use pure digital transistors to implement the level conversion function. Therefore, connecting signal transmission units between its various signal transmission points can make the signal level switching more stable, and can also eliminate the transient signal jump caused by the uncertain state of the transistor signal at the moment of power-off, thereby improving the reliability of the level conversion module 300 when performing the level conversion function.

[0048] The inventor Figure 4 The level conversion circuit shown was simulated and analyzed. The simulation analysis shows that when NSLEEP=1, the second signal Z can follow the change of the first signal I, and Z=k*I; when NSLEEP=0, the output of the level conversion circuit can be clamped to 0, that is, Z=0. The inventors further verified the electrical performance of the above level conversion circuit. During the verification process, the level conversion circuit can perform accurate and stable level conversion in the range of 0.65V to 0.9V. It can be seen that the above level conversion circuit can perform mutual conversion between different voltage values ​​and can also meet the requirements of cross-power domain design for level conversion circuits with clamping values. The above simulation analysis shows that... Figure 4The level conversion circuit shown can be used for level conversion between two independent power domains. When one power source (e.g., the first power source VDD of the first power domain) is de-energized, it can output a constant value "0" as needed. This level conversion circuit can be placed directly within the power-off region (i.e., the first power domain), without requiring a dedicated physical area for an external power domain in the current design. When both power sources are operating normally, this level conversion circuit can be used as a level conversion circuit (Z = k*I). When the power source of the current power domain (e.g., the first power source VDD of the first power domain) is de-energized while the external target power domain is powered on and operating normally, this level conversion circuit is unaffected by the power outage of the current power domain and directly uses the external power source (e.g., the first power source VDDS of the second power domain) to output a constant value "0" to the normally powered module, thus ensuring the correct functioning of the entire system.

[0049] Furthermore, the signal receiving module 100, enable control module 200, level conversion module 300, and first inverter N1 in the aforementioned level conversion circuit can all be designed and built using pure digital CMOS transistors, and can be made into corresponding standard cell libraries for easy use by automated design tools. Specifically, for the aforementioned level conversion circuit, a corresponding layout can be drawn, physical parasitic parameters can be extracted, and a standard .lib file can be generated using timing and power consumption information characterization extraction tools for standardized use in digital chip design.

[0050] In the above level conversion circuit, when the control signal NSLEEP is in the first state (i.e., the first power domain is powered on), the enable function is disabled, and the first signal I is level-converted to output a second signal Z adapted to the second power domain. This allows the level conversion circuit to stably perform level conversion between the first and second power domains when the first power domain is powered on. When the control signal NSLEEP is in the second state (i.e., the first power domain is powered off), the second power supply voltage VDDS is connected, making the input of the first inverter N1 high and the output of the first inverter N1 low. This level conversion circuit can stably output a low level when the first power domain is powered off. It adds a level conversion circuit with an output clamp value of 0 (i.e., low level) that can be placed in the power off region to the traditional low-power design circuit unit library. This solves the limitation that the original level conversion circuit unit with a clamp value of 0 can only be placed in the normally open power region when the power off region needs to have a fixed output of 0. It can improve the function of the level conversion circuit and enhance its application flexibility.

[0051] A second aspect of this application provides a chip that may include a low-power chip requiring cross-power domain signal communication delivery. The chip includes the level conversion circuit described in any of the above embodiments.

[0052] The chip described above includes the level conversion circuit described in any of the above embodiments, and has all the beneficial effects of the level conversion circuit described in any of the above embodiments, which will not be repeated here.

[0053] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0054] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0055] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0056] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A level conversion circuit, characterized in that, The level conversion circuit includes a signal receiving module, an enable control module, a level conversion module, and a first inverter; The first terminal of the signal receiving module is used to receive a first signal corresponding to the first power domain, and the second terminal is connected to the first terminal of the level conversion module; the first terminal of the enable control module is used to receive a control signal, the second terminal is used to receive a second power voltage corresponding to the second power domain, and the third terminal is connected to the second terminal of the level conversion module and the input terminal of the first inverter respectively; the third terminal of the level conversion module is grounded; the control signal is characterized as a first state when the first signal is in a stable state, and as a second state when the first signal is in a power-off state; The signal receiving module is used to transmit the first signal to the level conversion module; The enable control module is used to disable the enable function when the control signal is in the first state, and to turn on the second power supply voltage when the control signal is in the second state, so that the input terminal of the first inverter is at a high level and the output terminal of the first inverter is at a low level. The level conversion module is used to perform level conversion on the first signal when the enable function of the enable control module is turned off, so as to output a second signal adapted to the second power domain.

2. The level conversion circuit according to claim 1, characterized in that, The second state includes a low level; the enable control module includes a buffer and a first transistor; The input terminal of the buffer serves as the first terminal of the enable control module, the output terminal is connected to the gate of the first transistor, the source of the first transistor serves as the second terminal of the enable control module, and the drain of the first transistor serves as the third terminal of the enable control module. The buffer is used to transmit the control signal to the gate of the first transistor; The first transistor is configured to turn on when the control signal is low, so as to connect the second power supply voltage.

3. The level conversion circuit according to claim 2, characterized in that, The buffer comprises an even number of inverters connected in series.

4. The level conversion circuit according to claim 2, characterized in that, The signal receiving module includes a second inverter and a third inverter; The input terminal of the second inverter serves as the first terminal of the signal receiving module, and its output terminal is connected to the input terminal of the third inverter; the output terminal of the third inverter serves as the second terminal of the signal receiving module.

5. The level conversion circuit according to claim 4, characterized in that, The level conversion module includes a signal conversion unit and at least one signal transmission unit; Each of the signal transmission units is respectively disposed between each signal transmission point in the level conversion module, and is used to buffer the signal change state corresponding to each signal transmission point; The signal conversion unit is used to convert the first signal so that the converted signal is adapted to the second power domain.

6. The level conversion circuit according to claim 5, characterized in that, The signal conversion unit includes at least one second transistor connected in parallel; The drain of each of the second transistors serves as the first terminal of the signal conversion unit, used to receive the first signal; the gate is used to receive the control signal; and the source is grounded.

7. The level conversion circuit according to claim 5, characterized in that, The at least one signal transmission unit includes a first signal transmission unit and a second signal transmission unit; the first end of the first signal transmission unit serves as the first end of the level conversion module, the second end serves as the second end of the level conversion module, the third end is used to connect to the second power supply voltage, and the fourth end is connected to the first end of the second signal transmission unit and the first end of the signal conversion unit respectively; the second end of the second signal transmission unit is connected to the output end of the second inverter, and the third end is used to connect to the second power supply voltage.

8. The level conversion circuit according to claim 7, characterized in that, Each of the signal transmission units includes multiple stages of transistors connected in sequence.

9. The level conversion circuit according to claim 1, characterized in that, The level conversion circuit is located inside the first power domain.

10. A chip, characterized in that, The chip includes a level conversion circuit as described in any one of claims 1 to 9.

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