Bit selection method and device in LDPC rate matching, computer equipment and storage medium

Abstract

The embodiment of the invention provides a bit selection method and device in LDPC rate matching, computer equipment and a storage medium. The method comprises the steps that an input bit sequence used for rate matching is sequentially divided into a first segment bit sequence, a first 1-byte bit sequence, a filling bit sequence, a second 1-byte bit sequence and a second segment bit sequence; respectively extracting a first information bit sequence and a second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence; splicing the first segment of bit sequence, the first information bit sequence, the second information bit sequence and the second segment of bit sequence to obtain a target bit sequence; the new bit selection position and the preset rate matching output length are determined according to the filling bit position, the rate matching output sequence is generated according to the target bit sequence, bits are used as operation granularity, the running time is shortened, memory resources are saved, corresponding data movement does not need to be selected according to multiple scenes, and logic complexity is reduced.

Description

Technical Field

[0001] This application relates to the technical field of data processing in communications. Specifically, it relates to a method, apparatus, computer device, and storage medium for bit selection in LDPC rate matching. Background Technique

[0002] LDPC (Low-Density Parity-Check Code) rate matching is that the bits (the length of the encoded data) on the transmission channel are retransmitted or punctured to match the carrying capacity of the physical channel, and the bit rate required by the transmission format is achieved during channel mapping. Among them, the bit selection for rate matching is to retransmit or puncture the encoded output result to match the carrying capacity of the physical channel, and the carrying capacity is represented by the rate matching output length E. Starting from the starting position K0 (calculated according to the 3GPP 38.212 protocol) of the information bit stream after channel encoding, information bits are taken, Null bits (padding bits) are skipped, and information bit data with a length of E is taken.

[0003] In the related art, the encoded information bit stream is converted into a byte type, and then the size of E and N - Null_Len (N is the total bit length of the encoded information bit stream, and Null_Len is the number of padding bits) is judged to select whether to truncate or puncture and repeat. For example, Figure 1 (N - Nulllen) ≥ E, and Figure 2 (N - Nulllen) < E, as shown. Then, according to the parameters K0 and Null_Pos (Null_Pos is the specific position of the padding bit in the encoded information bit stream), the specific data selection method is selected, the Null bits in the data are skipped, and continuous reading starts from the starting position until the output target value is reached, and data with a length of E is processed.

[0004] However, converting the encoded information bit stream into a byte type for processing, although this makes it convenient to not consider the problem that K0 and the starting position of the Null bits are not whole bytes during subsequent implementation, due to the large scale of the LDPC code, converting to a byte type for processing will increase a large part of the time consumption, and converting bits to bytes will increase the cache space by eight times, thus increasing the consumption of memory space. When performing bit selection, there are two branch cases of puncturing and truncating. According to the situation of the K0 position and the starting position of the Null bits, there will be multiple branches to move the corresponding information data, and various possible scenarios need to be listed. The logic is complex, the data movement process is cumbersome, and due to the operation granularity being the byte type, the time consumption will be increased.

[0005] Therefore, the related technology still has the following problems: the rate matching process includes operations such as puncturing and truncation, which requires the selection and processing of the encoded bit sequence. When selecting the bit positions for puncturing or truncation, calculations and judgments must be made based on certain criteria, which increases the computational complexity. The operation of skipping padding bits in the LDPC rate matching bit selection requires real-time hardware judgment, which disrupts the continuity of pipeline processing and leads to a decrease in processing efficiency. The implementation of LDPC rate matching requires additional processing units and a large amount of memory. LDPC codes are large in scale, have a wide rate range, and have an irregular interconnection pattern. Hardware implementation faces high interconnection complexity and resource consumption. Summary of the Invention

[0006] Embodiments of the present application provide a method, apparatus, computer device, and storage medium for bit selection in LDPC rate matching.

[0007] A first aspect of an embodiment of the present application provides a bit selection method in LDPC rate matching, comprising:

[0008] Sequentially dividing an input bit sequence for rate matching into a first bit sequence segment, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second bit sequence segment, wherein both the first 1-byte bit sequence and the second 1-byte bit sequence include a padding sequence and an information bit sequence;

[0009] extracting a first information bit sequence and a second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence respectively;

[0010] concatenating the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence;

[0011] A new bit selection position is determined according to the initial bit selection position index and the starting position and ending position of the padding bit, and a rate matching output sequence is generated according to the target bit sequence according to the new bit selection position and the preset rate matching output length.

[0012] In an optional embodiment of the present application, dividing the input bit sequence for rate matching into a first segment bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second segment bit sequence in sequence includes:

[0013] In the input bit sequence used for rate matching, the whole-byte information bit sequence preceding the padding bit sequence is taken as the first bit sequence segment, the first byte bit sequence following the first bit sequence segment is taken as the first 1-byte bit sequence, the whole-byte padding bit sequence following the first 1-byte bit sequence is taken as the padding bit sequence, the first byte bit sequence following the padding bit sequence is taken as the second 1-byte bit sequence, and the information bit sequence following the second 1-byte bit sequence is taken as the second bit sequence segment.

[0014] In an optional embodiment of the present application, extracting the first information bit sequence and the second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence, respectively, includes:

[0015] Determine an end position index of the padding bit sequence in the second 1-byte bit sequence according to the starting position of the padding bit sequence and the length of the padding bit sequence, perform a logical AND of 7 on the end position index, and determine a second information bit sequence in the second 1-byte bit sequence;

[0016] Perform a logical AND operation with 7 on the starting position of the padding bit sequence to determine the first information bit sequence in the first 1-byte bit sequence.

[0017] In an optional embodiment of the present application, the step of concatenating the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain the target bit sequence includes:

[0018] Using the number of the second information bit sequence as a first shift value for concatenating and shifting the second information bit sequence and the second segment bit sequence, and concatenating the second information bit sequence and the second segment bit sequence according to the first shift value to obtain a third segment bit sequence;

[0019] Using the number of the first information bit sequence as a second shift value for concatenating and shifting the first information bit sequence and the third bit sequence, and concatenating the first information bit sequence and the third bit sequence according to the second shift value to obtain a fourth bit sequence;

[0020] The first bit sequence and the fourth bit sequence are concatenated to obtain a target bit sequence.

[0021] In an optional embodiment of the present application, determining a new bit selection position according to the initial bit selection position index and the starting position and ending position of the padding bits includes:

[0022] When the initial bit selection position index is before the starting position of the padding bits or between the starting position and the ending position of the padding bits, the new bit selection position is before the initial bit selection position and the distance between the new bit selection position and the initial bit selection position is the padding bit sequence length;

[0023] In the case where the initial bit selection position index is arranged after the end position of the padding bits, the new bit selection position is the initial bit selection position.

[0024] In an optional embodiment of the present application, generating a rate matching output sequence according to a target bit sequence according to a new bit selection position and a preset rate matching output length includes:

[0025] Perform logical AND 7 on the target bit sequence;

[0026] When the target bit sequence is a whole-byte bit sequence, comparing the target bit sequence length with a preset rate matching output length;

[0027] When the target bit sequence length is greater than the preset rate matching output length, the target bit sequence is shortened so that the length of the shortened target bit sequence is the same as the preset rate matching output length, and the shortened target bit sequence is used as the rate matching output sequence;

[0028] In a case where the length of the target bit sequence is less than the preset rate matching output length, the number of repetitions of the target bit sequence is determined according to the target bit sequence length and the preset rate matching output length, the target bit sequence is repeated according to the number of repetitions so that the length of the target bit sequence after the repetition is greater than or equal to the preset rate matching output length, and in a case where the length of the target bit sequence after the repetition is equal to the preset rate matching output length, the repeated target bit sequence is used as the rate matching output sequence, and in a case where the length of the target bit sequence after the repetition is greater than the preset rate matching output length, the repeated target bit sequence is truncated so that the length of the truncated target bit sequence is the same as the preset rate matching output length, and the truncated target bit sequence is used as the rate matching output sequence;

[0029] When the target bit sequence length is equal to the preset rate matching output length, the target bit sequence is used as the rate matching output sequence.

[0030] If the target bit sequence is not a full-byte bit sequence, adjust the valid bits of the last byte of the target bit sequence to the front of the target bit sequence to generate a new target bit sequence, and compare the length of the new target bit sequence with the preset rate matching output length;

[0031] When the length of the new target bit sequence is greater than the preset rate matching output length, the new target bit sequence is shortened so that the length of the shortened bit sequence is the same as the preset rate matching output length, and the shortened bit sequence is used as the rate matching output sequence;

[0032] In a case where the length of the new target bit sequence is less than the preset rate matching output length, determining the number of repetitions of the new target bit sequence based on the new target bit sequence length and the preset rate matching output length, repeating the new target bit sequence according to the number of repetitions so that the length of the repeated bit sequence is greater than or equal to the preset rate matching output length, and in a case where the length of the repeated bit sequence is equal to the preset rate matching output length, using the repeated bit sequence as the rate matching output sequence; and in a case where the length of the repeated bit sequence is greater than the preset rate matching output length, truncating the repeated bit sequence so that the length of the truncated bit sequence is the same as the preset rate matching output length, and using the truncated bit sequence as the rate matching output sequence;

[0033] When the length of the new target bit sequence is equal to the preset rate matching output length, the new target bit sequence is used as the rate matching output sequence.

[0034] In an optional embodiment of the present application, determining the number of repetitions of the new target bit sequence according to the new target bit sequence length and the preset rate matching output length, and repeating the new target bit sequence according to the number of repetitions includes:

[0035] The number of repetitions of the new target bit sequence is determined according to the new target bit sequence length and the preset rate matching output length using the following expression:

[0036] N+b*(CN)≥M

[0037] Where C is the new target bit sequence length, N is the number of valid bits in the last byte of the target bit sequence, b is the number of repetitions, and M is the preset rate matching output length.

[0038] When the new target bit sequence is repeated according to the repetition number b, bits other than the first N bits in the new target bit sequence are repeated.

[0039] A second aspect of the embodiments of the present application provides a bit selection device for LDPC rate matching, comprising:

[0040] a dividing module, configured to divide an input bit sequence for rate matching into a first segment bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second segment bit sequence, wherein the first 1-byte bit sequence and the second 1-byte bit sequence both include a padding sequence and an information bit sequence;

[0041] An extraction module is used to extract a first information bit sequence and a second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence respectively;

[0042] a splicing module, configured to splice the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence;

[0043] The generation module is used to determine a new bit selection position according to the initial bit selection position index and the starting position and ending position of the padding bit, and generate a rate matching output sequence according to the target bit sequence according to the new bit selection position and the preset rate matching output length.

[0044] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of any of the above-mentioned bit selection methods in LDPC rate matching are implemented.

[0045] According to a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the bit selection method in LDPC rate matching as described in any one of the above items are implemented.

[0046] The above technical solutions provided by the embodiments of the present application have at least some or all of the following advantages compared to the prior art:

[0047] The bit selection method for LDPC rate matching described in an embodiment of the present application sequentially divides an input bit sequence for rate matching into a first bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second bit sequence, wherein the first 1-byte bit sequence and the second 1-byte bit sequence both include a padding sequence and an information bit sequence; extracts a first information bit sequence and a second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence, respectively; concatenates the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence; determines a new bit selection position based on an initial bit selection position index and the starting and ending positions of the padding bits, and generates a rate matching output sequence based on the target bit sequence according to the new bit selection position and a preset rate matching output length. The present application divides the input bit sequence for rate matching into multiple sequences and rearranges and concatenates them all at the bit-based operation granularity, significantly improving processing runtime. The bitstream saves memory resources and simplifies the processing flow for selecting corresponding data movement based on multiple scenarios, reducing logical complexity and thereby improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0049] Figure 1 Schematic diagram of the bits that need to be truncated in the bit selection provided for the related art;

[0050] Figure 2 A schematic diagram of the need for puncturing and repetition in bit selection provided for related technologies;

[0051] Figure 3 A flowchart of a bit selection method in LDPC rate matching provided in one embodiment of the present application;

[0052] Figure 4 A schematic diagram of dividing an input bit sequence for rate matching into a first bit sequence segment, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second bit sequence segment, provided in accordance with an embodiment of the present application;

[0053] Figure 5 A schematic diagram of splicing a first bit sequence, a first information bit sequence, a second information bit sequence, and a second bit sequence, provided in one embodiment of the present application;

[0054] Figure 6A schematic diagram of splicing non-integer byte data provided in one embodiment of the present application;

[0055] Figure 7 A schematic diagram of repeating non-integer byte data provided in one embodiment of the present application;

[0056] Figure 8 A schematic diagram of the structure of a bit selection device in LDPC rate matching provided by one embodiment of the present application;

[0057] Figure 9 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0058] In the process of implementing the present application, the inventors discovered that the current bit selection method in LDPC rate matching is poor in terms of memory resource usage and logic complexity.

[0059] To address the above problems, embodiments of the present application provide a method, apparatus, computer device, and storage medium for bit selection in LDPC rate matching to reduce memory resource usage and logical complexity.

[0060] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0061] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0062] See Figure 3 The bit selection method in LDPC rate matching provided in the embodiment of the present application includes the following steps S100 to S400:

[0063] S100, dividing the input bit sequence for rate matching into a first segment bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second segment bit sequence, such as Figure 4As shown, the bit sequence of rate matching input length N is divided into A, B, Null_len and 2 bytes, that is, N = A + 1 byte + Null_len + 1 byte + B, wherein the first 1-byte bit sequence and the second 1-byte bit sequence both include a padding sequence and an information bit sequence, the starting position of the padding bit may not be divisible by 8, and the first 1-byte bit sequence includes information bits and padding bits. Similarly, the ending position of the padding bit may not be divisible by 8, and the second 1-byte bit sequence includes information bits and padding bits.

[0064] S200, extracting a first information bit sequence and a second information bit sequence from a 1-byte bit sequence and a second 1-byte bit sequence respectively;

[0065] S300, concatenating the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence;

[0066] S400, determining a new bit selection position according to the initial bit selection position index and the starting position and ending position of the padding bit, and generating a rate matching output sequence according to the target bit sequence according to the new bit selection position and the preset rate matching output length.

[0067] The bit selection method in LDPC rate matching of the present application divides the input bit sequence used for rate matching into multiple sequences, and the rearrangement and splicing process is all based on the bit as the operation granularity, which greatly improves the processing running time. In addition, since it is a bit stream, memory resources are saved, and the processing flow of selecting corresponding data movement based on judging multiple scenarios is simplified, thereby reducing the complexity of logic and improving efficiency.

[0068] In an optional embodiment of the present application, in step S100, the step of sequentially dividing the input bit sequence for rate matching into a first bit sequence segment, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second bit sequence segment includes:

[0069] In the input bit sequence used for rate matching, the whole-byte information bit sequence preceding the padding bit sequence is taken as the first bit sequence segment, the first byte bit sequence following the first bit sequence segment is taken as the first 1-byte bit sequence, the whole-byte padding bit sequence following the first 1-byte bit sequence is taken as the padding bit sequence, the first byte bit sequence following the padding bit sequence is taken as the second 1-byte bit sequence, and the information bit sequence following the second 1-byte bit sequence is taken as the second bit sequence segment.

[0070] The bit selection method in LDPC rate matching of the present application separates the 1-byte bit sequence between the first bit sequence of the whole byte and the padding bit sequence, and the 1-byte bit sequence between the second bit sequence of the whole byte and the padding bit sequence from the input bit sequence, so as to extract the valid bits in the two 1-byte bit sequences and splice them with the whole byte sequence, remove the padding bits in the two 1-byte bit sequences, and complete the splicing and shifting of non-whole byte data.

[0071] In an optional embodiment of the present application, in step S200, extracting the first information bit sequence and the second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence, respectively, includes:

[0072] Determine an end position index of the padding bit sequence in the second 1-byte bit sequence according to the starting position of the padding bit sequence and the length of the padding bit sequence, perform a logical AND of 7 on the end position index, and determine a second information bit sequence in the second 1-byte bit sequence;

[0073] Perform a logical AND operation with 7 on the starting position of the padding bit sequence to determine the first information bit sequence in the first 1-byte bit sequence.

[0074] The bit selection method in LDPC rate matching of the present application extracts the valid bits from two 1-byte bit sequences and splices them with the whole byte sequence, removes the padding bits in the two 1-byte bit sequences, reduces a large number of logical judgment branches, simplifies the logic, operates at a bit granularity, improves efficiency and greatly saves memory resources.

[0075] In an optional embodiment of the present application, in step S300, the step of concatenating the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain the target bit sequence includes:

[0076] Using the number of the second information bit sequence as a first shift value for concatenating and shifting the second information bit sequence and the second segment bit sequence, and concatenating the second information bit sequence and the second segment bit sequence according to the first shift value to obtain a third segment bit sequence;

[0077] Using the number of the first information bit sequence as a second shift value for concatenating and shifting the first information bit sequence and the third bit sequence, and concatenating the first information bit sequence and the third bit sequence according to the second shift value to obtain a fourth bit sequence;

[0078] The first bit sequence and the fourth bit sequence are concatenated to obtain a target bit sequence.

[0079] In an optional embodiment of the present application, Figure 5 As shown, the information bits of the entire byte of part A are extracted. The known starting position of Null_pos and null_len indicate the position index of the end of the padding bits. A logical AND of 7 is then performed to determine the number of information bits in the byte at the end of the padding bits. This is used as the shift value for the subsequent splicing and shifting. The byte after Null_len is spliced ​​and shifted with part B to obtain a new B1, ensuring that there are no padding bits in the entire B1 bit sequence. A logical AND of 7 is performed at the starting position of Null_pos to determine the number of information bits in the byte after A. This is used as the shift value for the subsequent splicing and shifting. The byte after A is spliced ​​and shifted with B1 to obtain B2. Finally, C = N - Null_len = A + B2, which is the bit sequence after skipping the padding bits in the rate matching input bit sequence N.

[0080] The bit selection method in the LDPC rate matching of the present application is divided into truncation and repetition according to the description in the 5G communication protocol, and there are multiple options according to the position of K0. The present application uses one mode to skip the padding bits and select the bit information sequence of data length E according to the position of the K0 index in all cases.

[0081] In an optional embodiment of the present application, in step S400, determining a new bit selection position according to the initial bit selection position index and the starting position and ending position of the padding bits includes:

[0082] When the initial bit selection position index is before the starting position of the padding bits or between the starting position and the ending position of the padding bits, the new bit selection position is before the initial bit selection position and the distance between the new bit selection position and the initial bit selection position is the padding bit sequence length;

[0083] In the case where the initial bit selection position index is arranged after the end position of the padding bits, the new bit selection position is the initial bit selection position.

[0084] The bit selection method in the LDPC rate matching of the present application places the bit selection position after the padding bits in order to reduce the padding bits in the bit selection. This can reduce the amount of data of the information bit stream remaining after removing the padding bits and arranging them tightly, thereby improving the bit selection efficiency.

[0085] In an optional embodiment of the present application, in step S400, generating a rate matching output sequence according to a target bit sequence according to a new bit selection position and a preset rate matching output length includes:

[0086] Perform logical AND 7 on the target bit sequence;

[0087] When the target bit sequence is a whole-byte bit sequence, comparing the target bit sequence length with a preset rate matching output length;

[0088] When the target bit sequence length is greater than the preset rate matching output length, the target bit sequence is shortened so that the length of the shortened target bit sequence is the same as the preset rate matching output length, and the shortened target bit sequence is used as the rate matching output sequence;

[0089] In a case where the length of the target bit sequence is less than the preset rate matching output length, the number of repetitions of the target bit sequence is determined according to the target bit sequence length and the preset rate matching output length, the target bit sequence is repeated according to the number of repetitions so that the length of the target bit sequence after the repetition is greater than or equal to the preset rate matching output length, and in a case where the length of the target bit sequence after the repetition is equal to the preset rate matching output length, the repeated target bit sequence is used as the rate matching output sequence, and in a case where the length of the target bit sequence after the repetition is greater than the preset rate matching output length, the repeated target bit sequence is truncated so that the length of the truncated target bit sequence is the same as the preset rate matching output length, and the truncated target bit sequence is used as the rate matching output sequence;

[0090] When the target bit sequence length is equal to the preset rate matching output length, the target bit sequence is used as the rate matching output sequence.

[0091] If the target bit sequence is not a full-byte bit sequence, adjust the valid bits of the last byte of the target bit sequence to the front of the target bit sequence to generate a new target bit sequence, and compare the length of the new target bit sequence with the preset rate matching output length;

[0092] When the length of the new target bit sequence is greater than the preset rate matching output length, the new target bit sequence is shortened so that the length of the shortened bit sequence is the same as the preset rate matching output length, and the shortened bit sequence is used as the rate matching output sequence;

[0093] In a case where the length of the new target bit sequence is less than the preset rate matching output length, determining the number of repetitions of the new target bit sequence based on the new target bit sequence length and the preset rate matching output length, repeating the new target bit sequence according to the number of repetitions so that the length of the repeated bit sequence is greater than or equal to the preset rate matching output length, and in a case where the length of the repeated bit sequence is equal to the preset rate matching output length, using the repeated bit sequence as the rate matching output sequence; and in a case where the length of the repeated bit sequence is greater than the preset rate matching output length, truncating the repeated bit sequence so that the length of the truncated bit sequence is the same as the preset rate matching output length, and using the truncated bit sequence as the rate matching output sequence;

[0094] When the length of the new target bit sequence is equal to the preset rate matching output length, the new target bit sequence is used as the rate matching output sequence.

[0095] The bit selection method in LDPC rate matching of the present application determines the number of times the remaining bit information is copied based on the length of the rate matching output sequence E and N-null_len, and then starts continuous reading from the K0 position to reach the output target value. In the process of processing data of length E, the whole byte data and the non-whole byte data are copied separately to ensure efficient and accurate copying of the non-whole byte data.

[0096] In an optional embodiment of the present application, determining the number of repetitions of the new target bit sequence according to the new target bit sequence length and the preset rate matching output length, and repeating the new target bit sequence according to the number of repetitions includes:

[0097] The number of repetitions of the new target bit sequence is determined according to the new target bit sequence length and the preset rate matching output length using the following expression:

[0098] N+b*(CN)≥M

[0099] Where C is the new target bit sequence length, N is the number of valid bits in the last byte of the target bit sequence, b is the number of repetitions, and M is the preset rate matching output length.

[0100] When the new target bit sequence is repeated according to the repetition number b, bits other than the first N bits in the new target bit sequence are repeated.

[0101] like Figure 6 and Figure 7As shown, the length C = N - null_len may not be an integer multiple of 8, so it is necessary to perform a logical AND 7 on the last byte at the end, place the last byte of the non-integer byte in front of A, and then place the bit information sequence A + B3 after B3 for splicing and shifting to form a bit information sequence of length 2*C. The resulting bit information sequence of length 2*C is determined based on the K0 position index and the starting and ending positions of the padding bits. If k0 > = (Null_pos + null_len), the new position index is new_K0 = K0 - null_len. If k0 < (Null_pos + null_len), the K0 value remains unchanged. In the case of truncation, the rate matching length E may be obtained in the sequence of the bit information sequence of length 2*C based on K0 and E. For the repetition case, similarly, place the bit information sequence A+B3 after 2*C and concatenate and shift it with 2*C to obtain information bits of length 4*C. The specific number of repetitions is determined by performing the above repetition operation based on the actual E, and then taking out the data length E in sequence according to K0.

[0102] In an optional embodiment of the present application, an input bit sequence for rate matching is obtained by the following steps:

[0103] Preprocess the rate check matrices of each DVB-S2 / S2X protocol, generate and store the basic shift matrix and its index of the system part;

[0104] Divide the check bits into q segments to obtain check bits after primary segmentation, divide each check bit after primary segmentation into u segments to obtain check bits after secondary segmentation, use the length of the check bits after secondary segmentation as the table lookup parallelism, and generate and store a lookup table based on the table lookup parallelism;

[0105] Determine a table lookup index value according to the basic shift matrix of the system part and its index, and perform a lookup in the lookup table according to the table lookup index value;

[0106] The target check bit is determined according to the found check bit value, and the target check bit is extracted and interleaved and rearranged at intervals of preset length to obtain a check sequence, which is output to the end of the system bit as an input bit sequence for rate matching.

[0107] In an optional embodiment of the present application, preprocessing each rate check matrix under the DVB-S2 / S2X protocol to generate and store basic shift coefficients includes:

[0108] Split the check matrix H to obtain submatrix H s and H p And the verification formula H s *s=H p*p, where s and p are systematic bits and parity bits respectively, and the submatrix H s and H p The dimensions are [nk, k] and [nk, nk], k is the number of information symbols, and n is the total number of symbols;

[0109] For each submatrix H s and H p Extract and rearrange rows at intervals of q to obtain the matrix and

[0110] Pair Matrix Extract and rearrange the columns at intervals of q to obtain the matrix

[0111] Extract and rearrange the check bits p at intervals of q rows to obtain the matrix p shift ;

[0112] Extract matrices separately and The cyclic shift values ​​corresponding to the elements in the matrix are replaced by -1 to obtain the basic shift matrices of the system part and the check part, and store them, where the elements of the basic shift matrix are basic shift coefficients.

[0113] In an optional embodiment of the present application, the method of using the length of the check bits after secondary segmentation as the table lookup parallelism, and generating and storing the lookup table according to the table lookup parallelism, includes:

[0114] Lookup Table LUT_TRI V and LUT_O v They are matrices TRI of dimension v×v respectively V and O v :

[0115]

[0116] Wherein, v is the length of the check bit after secondary segmentation.

[0117] In an optional embodiment of the present application, determining the table lookup index value according to the basic shift matrix of the system part and its index includes:

[0118] Check bits after solving the second segment of segment i In the case of and λ(i*v+(0:v-1)) as the lookup table LUT_TRI V and LUT_O v The table index value, where i is any value from 1 to u, and v is the length of the check bit after the secondary segmentation.

[0119]

[0120] Where l is the number of segments of the system bit s, q and l are both positive integers greater than or equal to 1, and k q-1，l-1 The basic shift matrix elements for the system part The index of The basic shift matrix elements for the system part For a subcode block s of systematic bits s l-1 The cyclic shift matrix of .

[0121] In an optional embodiment of the present application, a cyclic shift matrix of the basic shift matrix elements of the systematic part for the subcode block of the systematic bit s is obtained by the following steps:

[0122] The subcode block of systematic bits s is divided into u segments by the following expression:

[0123]

[0124] v=M / u

[0125] M=(nk) / q

[0126] Among them, s j is a subcode block of systematic bits s, M is the length of the subcode block,

[0127] The basic shift matrix elements of the system part are divided by the following expression:

[0128]

[0129] in, is the basic shift matrix element of the system part, h ceil The value of the element is rounded up, h floor The value of the element is rounded down, h mod Modulo value for the element,

[0130] The following expressions are used to round the element up and down to the subcode block after segmentation: Perform a circular shift:

[0131]

[0132]

[0133] in, and are the intermediate shift results of cyclic shifting the subcode block of the systematic bit s by the element-rounded-up value and the element-rounded-down value, respectively,

[0134] The shifted intermediate results are concatenated using the following expression, the concatenated matrix is ​​shifted according to the element modulus value, and the low v bits of the shifted matrix are taken:

[0135]

[0136] in, Segmented subcode block The corresponding cyclic shift vector, Subcode block s j The corresponding cyclic shift matrix.

[0137] In an optional embodiment of the present application, the lookup table is searched according to the lookup index value using the following expression:

[0138]

[0139] Among them, bi2de is the binary to decimal function.

[0140] In an optional embodiment of the present application, determining the target check bit according to the found check bit value includes:

[0141] According to the value of i, the check bits are checked after the i-th segment is divided twice Perform u iterations to obtain the first set of check sequences

[0142] The first set of parity sequence obtains the target parity bits through the following expression:

[0143]

[0144] Among them, p shift is the target parity bit, For other groups of check sequences, λ1~λ l-1 is the check value.

[0145] The bit selection method in the LDPC rate matching of the present application, for the splicing of non-integer byte data, places the last non-integer byte in front of the whole byte sequence when copying is required, and only copies the whole byte sequence, which can complete the copy operation quickly and accurately.

[0146] It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0147] See Figure 8 One embodiment of the present application provides a bit selection device 800 for LDPC rate matching, comprising:

[0148] a dividing module 810, configured to sequentially divide an input bit sequence for rate matching into a first segment bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second segment bit sequence, wherein both the first 1-byte bit sequence and the second 1-byte bit sequence include a padding sequence and an information bit sequence;

[0149] An extraction module 820 is configured to extract a first information bit sequence and a second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence, respectively;

[0150] a concatenation module 830 configured to concatenate the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence;

[0151] The generation module 840 is used to determine a new bit selection position according to the initial bit selection position index and the starting position and ending position of the padding bit, and generate a rate matching output sequence according to the target bit sequence according to the new bit selection position and the preset rate matching output length.

[0152] For the specific limitations of the apparatus 800, please refer to the limitations of the bit selection method in LDPC rate matching above and will not be repeated here. Each module in the apparatus 800 can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0153] In one embodiment, a computer device is provided, wherein the internal structure diagram of the computer device can be as follows: Figure 9As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements a bit selection method in LDPC rate matching as described above. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements any step in the bit selection method in LDPC rate matching as described above.

[0154] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step of the bit selection method in the above LDPC rate matching can be implemented.

[0155] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0156] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0157] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0158] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0159] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0160] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A bit selection method in LDPC rate matching, characterized in that: include: Sequentially dividing an input bit sequence for rate matching into a first bit sequence segment, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second bit sequence segment, wherein both the first 1-byte bit sequence and the second 1-byte bit sequence include a padding sequence and an information bit sequence; extracting a first information bit sequence and a second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence respectively; concatenating the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence; A new bit selection position is determined according to the initial bit selection position index and the starting position and ending position of the padding bit, and a rate matching output sequence is generated according to the target bit sequence according to the new bit selection position and the preset rate matching output length.

2. The method according to claim 1, characterized in that The step of sequentially dividing an input bit sequence for rate matching into a first segment bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second segment bit sequence includes: In the input bit sequence used for rate matching, the whole-byte information bit sequence preceding the padding bit sequence is taken as the first bit sequence segment, the first byte bit sequence following the first bit sequence segment is taken as the first 1-byte bit sequence, the whole-byte padding bit sequence following the first 1-byte bit sequence is taken as the padding bit sequence, the first byte bit sequence following the padding bit sequence is taken as the second 1-byte bit sequence, and the information bit sequence following the second 1-byte bit sequence is taken as the second bit sequence segment.

3. The method according to claim 1, characterized in that The extracting of the first information bit sequence and the second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence respectively includes: Determine an end position index of the padding bit sequence in the second 1-byte bit sequence according to the starting position of the padding bit sequence and the length of the padding bit sequence, perform a logical AND of 7 on the end position index, and determine a second information bit sequence in the second 1-byte bit sequence; Perform a logical AND operation with 7 on the starting position of the padding bit sequence to determine the first information bit sequence in the first 1-byte bit sequence.

4. The method according to claim 3, characterized in that The step of splicing the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence includes: Using the number of the second information bit sequence as a first shift value for concatenating and shifting the second information bit sequence and the second segment bit sequence, and concatenating the second information bit sequence and the second segment bit sequence according to the first shift value to obtain a third segment bit sequence; Using the number of the first information bit sequence as a second shift value for concatenating and shifting the first information bit sequence and the third bit sequence, and concatenating the first information bit sequence and the third bit sequence according to the second shift value to obtain a fourth bit sequence; The first bit sequence and the fourth bit sequence are concatenated to obtain a target bit sequence.

5. The method according to claim 1, wherein The determining of a new bit selection position according to the initial bit selection position index and the starting position and the ending position of the padding bit includes: When the initial bit selection position index is before the starting position of the padding bits or between the starting position and the ending position of the padding bits, the new bit selection position is before the initial bit selection position and the distance between the new bit selection position and the initial bit selection position is the padding bit sequence length; In the case where the initial bit selection position index is arranged after the end position of the padding bits, the new bit selection position is the initial bit selection position.

6. The method according to claim 1, characterized in that Generating a rate matching output sequence according to a target bit sequence according to the new bit selection position and the preset rate matching output length includes: Perform logical AND 7 on the target bit sequence; When the target bit sequence is a whole-byte bit sequence, comparing the target bit sequence length with a preset rate matching output length; When the target bit sequence length is greater than the preset rate matching output length, the target bit sequence is shortened so that the length of the shortened target bit sequence is the same as the preset rate matching output length, and the shortened target bit sequence is used as the rate matching output sequence; In a case where the length of the target bit sequence is less than the preset rate matching output length, the number of repetitions of the target bit sequence is determined according to the target bit sequence length and the preset rate matching output length, the target bit sequence is repeated according to the number of repetitions so that the length of the target bit sequence after the repetition is greater than or equal to the preset rate matching output length, and in a case where the length of the target bit sequence after the repetition is equal to the preset rate matching output length, the repeated target bit sequence is used as the rate matching output sequence, and in a case where the length of the target bit sequence after the repetition is greater than the preset rate matching output length, the repeated target bit sequence is truncated so that the length of the truncated target bit sequence is the same as the preset rate matching output length, and the truncated target bit sequence is used as the rate matching output sequence; When the target bit sequence length is equal to the preset rate matching output length, the target bit sequence is used as the rate matching output sequence; If the target bit sequence is not a full-byte bit sequence, adjust the valid bits of the last byte of the target bit sequence to the front of the target bit sequence to generate a new target bit sequence, and compare the length of the new target bit sequence with the preset rate matching output length; When the length of the new target bit sequence is greater than the preset rate matching output length, the new target bit sequence is shortened so that the length of the shortened bit sequence is the same as the preset rate matching output length, and the shortened bit sequence is used as the rate matching output sequence; In a case where the length of the new target bit sequence is less than the preset rate matching output length, determining the number of repetitions of the new target bit sequence based on the new target bit sequence length and the preset rate matching output length, repeating the new target bit sequence according to the number of repetitions so that the length of the repeated bit sequence is greater than or equal to the preset rate matching output length, and in a case where the length of the repeated bit sequence is equal to the preset rate matching output length, using the repeated bit sequence as the rate matching output sequence; and in a case where the length of the repeated bit sequence is greater than the preset rate matching output length, truncating the repeated bit sequence so that the length of the truncated bit sequence is the same as the preset rate matching output length, and using the truncated bit sequence as the rate matching output sequence; When the length of the new target bit sequence is equal to the preset rate matching output length, the new target bit sequence is used as the rate matching output sequence.

7. The method according to claim 1, characterized in that The determining the number of repetitions of the new target bit sequence according to the new target bit sequence length and the preset rate matching output length, and repeating the new target bit sequence according to the number of repetitions, includes: The number of repetitions of the new target bit sequence is determined according to the new target bit sequence length and the preset rate matching output length using the following expression: N+b*(CN)≥M Where C is the new target bit sequence length, N is the number of valid bits in the last byte of the target bit sequence, b is the number of repetitions, and M is the preset rate matching output length. When the new target bit sequence is repeated according to the repetition number b, bits other than the first N bits in the new target bit sequence are repeated.

8. A bit selection device in LDPC rate matching, characterized in that: include: a dividing module, configured to divide an input bit sequence for rate matching into a first segment bit sequence, a first 1-byte bit sequence, a padding bit sequence, a second 1-byte bit sequence, and a second segment bit sequence, wherein the first 1-byte bit sequence and the second 1-byte bit sequence both include a padding sequence and an information bit sequence; An extraction module is used to extract a first information bit sequence and a second information bit sequence from the first 1-byte bit sequence and the second 1-byte bit sequence respectively; a splicing module, configured to splice the first bit sequence, the first information bit sequence, the second information bit sequence, and the second bit sequence to obtain a target bit sequence; The generation module is used to determine a new bit selection position according to the initial bit selection position index and the starting position and ending position of the padding bit, and generate a rate matching output sequence according to the target bit sequence according to the new bit selection position and the preset rate matching output length.

9. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the bit selection method in LDPC rate matching according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the bit selection method in LDPC rate matching according to any one of claims 1 to 7 are implemented.

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