Method for forming three-dimensional memory device and three-dimensional memory device

Abstract

The invention provides a method for forming a three-dimensional memory device, which comprises the following steps of: i) forming a stack structure in which insulating layers and conductive layers are alternately stacked in a direction perpendicular to the surface of a substrate, the stack structure comprising a core part and a step part, the step part being located on at least one side of the core part; ii) forming an etching stop layer covering the upper surface of the conductive layer on the top of each step of the step part; iii) after the etching stop layer is formed, filling the step gap with a step gap filling material to form a dielectric layer covering the stacked structure; iv) performing first etching operation on the step part of the stacked structure through the dielectric layer to form a step contact hole, taking the etching stop layer as a stop layer in the first etching operation, and exposing a part of the surface of the etching stop layer at each step through the first etching operation; v) performing a second etching operation on the step contact hole formed by the first etching operation to remove the exposed etching stop layer so as to expose a part of the upper surface of the conductive layer at each step; and vi) filling the step contact hole to form a step contact structure. The invention also provides a three-dimensional memory device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a method for forming a three-dimensional memory device and the three-dimensional memory device. Background Art

[0002] As semiconductor architectures become smaller and more complex, 3D NAND structures have become a trend. In 3D NAND, memory cells are stacked on top of each other and arranged three-dimensionally on a substrate, which can improve integration density and provide the reliability, speed, and performance expected of solid-state memory. In a 3D NAND three-dimensional memory device, the memory array area may include a core portion and a stepped portion. The core portion includes the memory array for data storage, and the stepped portion is used to lead out the wordline layer in the memory array.

[0003] However, as the number of 3D NAND layers increases, step contact etching becomes more challenging because the etching operation needs to stop at multiple wordline layers with different heights. Figure 1 As shown, the stacked structure on the substrate includes multiple alternating insulating layers and wordline layers (WL0, WL1, ..., WLN), with a dielectric layer covering the stacked structure. At each step, it is desirable that the wordline electrode be connected only to the wordline layer corresponding to that step. However, due to limitations in the etching process, it is more difficult to lead the wordline layer out of the step. During the process of etching to form the contact hole in the step, a punch-through condition may occur, causing the wordline layer to break down, resulting in the wordline electrode penetrating the insulating layer of the step to connect to the wordline layer below. Short circuits between different wordline layers can cause failure of the three-dimensional memory.

[0004] To address the above issues, one current solution is to form step contacts through multiple etching operations to reduce the number of wordline layers required in each etching step, thereby lowering the etching selectivity requirements for each etching step. However, this approach requires additional process steps and the resulting cost. Another solution is to improve the process capability of the etching step itself by increasing the selectivity of the etching process itself for the wordline layer material. However, this approach significantly increases the development requirements for the etching process and etching equipment, which often leads to delays in development progress and the need for equipment upgrade costs.

[0005] The information disclosed in this Background Art is only for enhancement of understanding of the background of the invention and may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0006] The present invention is proposed based on the above-mentioned technical problems and aims to improve the step contact etching process. Specifically, in the etching process provided by the present invention, an etch stop layer is formed on the top of the formed step as an etch stop layer for the step contact etching process. The etch stop layer can reduce the requirements for etching selectivity, thereby facilitating the control of etching rate and etching depth, and preventing etching through. In addition, the etching process of the present invention allows the simultaneous etching of multiple step contact holes through a single etching operation process, thereby extending the service life of the etching equipment and achieving cost-effective process scale.

[0007] According to one aspect of the present invention, a method for forming a three-dimensional memory device is provided. The method may include the following steps: i) providing a substrate and forming a stacked structure on the substrate in a direction perpendicular to a surface of the substrate, wherein insulating layers and conductive layers are alternately stacked, and the stacked structure includes a core portion and a stepped portion, wherein the stepped portion is located on at least one side of the core portion; ii) forming an etch stop layer covering the upper surface of the conductive layer at the top of each step of the stepped portion; iii) after forming the etch stop layer, filling the step gap with a step gap filling material to form a dielectric layer covering the stacked structure; iv) after completing the step gap filling, performing a first etching operation on the step portion of the stacked structure through the step gap filling material of the dielectric layer to form a step contact hole, the first etching operation using the etch stop layer as a stop layer, and exposing a portion of the surface of the etch stop layer at each step through the first etching operation; v) performing a second etching operation on the step contact hole formed by the first etching operation to remove the exposed etch stop layer, thereby exposing a portion of the upper surface of the conductive layer at each step; and vi) filling the step contact hole to form a step contact structure.

[0008] In an embodiment of the present invention, the etch stop layer can be formed by deposition. The material of the etch stop layer can be nitride, preferably silicon nitride. The thickness of the etch stop layer can be 50-200 nm.

[0009] In an embodiment of the present invention, step contact holes may be formed on each step through a single first etching process.

[0010] In an embodiment of the present invention, the sidewalls of the step contact hole may be substantially vertical or tapered.

[0011] In an embodiment of the present invention, the substrate may be a selection gate layer, the conductive layer may be a word line layer, and the stepped contact structure may be a word line electrode.

[0012] Another aspect of the present invention provides a three-dimensional memory device, which may include: a substrate and a stacked structure formed on the substrate in a direction perpendicular to a surface of the substrate, in which insulating layers and conductive layers are alternately stacked; the stacked structure includes a core portion and a step portion, wherein the step portion is located on at least one side of the core portion; an etch stop layer provided on an upper surface of the step portion; a dielectric layer covering the step portion; and a step contact structure, the step contact structure extending from an upper surface of the dielectric layer through the dielectric layer and the stacked etch stop layer to an upper surface of the conductive layer.

[0013] In an embodiment of the present invention, the material of the etch stop layer may be nitride, preferably silicon nitride, and the thickness of the etch stop layer may be 50-200 nm.

[0014] In an embodiment of the present invention, the substrate may be a selection gate layer, the conductive layer may be a word line layer, and the stepped contact structure may be a word line electrode.

[0015] Additional aspects of the invention will be set forth in the description which follows, and advantages of the invention will be obvious from the description, or may be learned by practice of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other features of the present invention will be described in detail below with reference to the embodiments of the present invention shown in the accompanying drawings, which are given by way of illustration only and are not intended to limit the present invention, in which:

[0017] Figure 1 FIG. 1 is a schematic diagram of a method for forming a word line electrode filling in the prior art;

[0018] Figure 2 FIG. 1 is a schematic diagram illustrating a method for forming a word line electrode filling according to an embodiment of the present invention.

[0019] It should be understood that the accompanying drawings are not necessarily drawn to scale, and that they schematically present simplified representations of various features embodying the basic principles of the invention. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes, will be determined in part by the specific intended application and use environment. DETAILED DESCRIPTION

[0020] In order to fully understand the present invention, the advantages of the operation of the present invention, and the objectives to be achieved by practicing the present invention, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the purpose of providing the exemplary embodiments is to enable a clearer understanding of the present invention. Since the exemplary embodiments can be implemented in various different forms by a person of ordinary skill in the art to which the present invention belongs, the embodiments of the present invention are not limited to the embodiments described herein.

[0021] As discussed above, the present invention relates to methods for fabricating three-dimensional memory devices and three-dimensional memory devices, various aspects of which are described below. Embodiments of the present invention can be used to form various structures, including multi-level memory structures, examples of which include, but are not limited to, three-dimensional memory array devices comprising multiple NAND memory strings.

[0022] Furthermore, in describing the present invention, when repeated description of well-known related arts may unnecessarily obscure the gist of the present invention, the corresponding description will be reduced or omitted.

[0023] In this article, the term "etching" refers to an etching process that forms vertical sidewalls along the edges of mask features, for example, at right angles to the substrate. Etching can produce holes, trenches, step contact holes, gate trenches, capacitor holes, etc., which can be used for step etching, slit etching, buried contact etching, capacitor contact etching, shallow trench isolation etching, etc.

[0024] In this document, the terms "layer" and "film" are used interchangeably. It should be understood that a layer may correspond to or be associated with a film, and a film may refer to a layer. In addition, the terms "layer" or "film" may refer to a material spread or applied on a surface (which may be as large as an entire wafer or as small as a groove or line, etc.).

[0025] It should be understood that, for ease of description, positional relationship terms, such as "under", "below", "on", "above", etc., may be used to describe the relationship of one element or feature to other elements or features. It should be understood that positional relationship terms also include different orientations of the device during operation and use. For example, if the device is flipped, the elements or features described as "under", "below", or "below" will be oriented to be "on" other elements or features. Therefore, the exemplary terms "under", "below" may include both upper and lower orientations. In addition, the device may also be in other orientations, such as rotated 90° or other orientations, and the corresponding spatial position descriptions will be interpreted accordingly.

[0026] It will be understood by those skilled in the art that the stacking and layer geometries shown in the figures are for illustrative purposes only, wherein the number of stacking layers may vary, i.e., may include more or fewer layers than shown, and the stacking geometry may also vary.

[0027] Figure 1 FIG. 1 is a schematic diagram of a method for forming a word line electrode filling in the prior art. Figure 1As shown, the method includes the following steps: Step a1: forming a stacked structure on the select gate layer SGS, the stacked structure including alternately stacked insulating layers and word line layers WL0, WL1, ..., WLN, and as shown in the figure, the stacked structure is formed with a step portion; Step a2: filling the step gaps with a step gap filling material to form a dielectric layer covering the stacked structure; Step a3: etching word line electrodes on each step through the step gap filling material in the dielectric layer to form a plurality of step contact holes; and Step a4: filling the plurality of step contact holes with metal to form word line electrodes.

[0028] At each step, the wordline electrode is expected to connect only to the wordline layer corresponding to that step. However, due to etching process limitations, the wordline electrode may penetrate the insulating layer of the step and connect to the wordline layer below. This short circuit between different wordline layers can cause errors in the control of the memory cells and lead to memory failure.

[0029] The present invention aims to solve the above technical problems. The present invention provides a method for forming a word line electrode filling. Figure 2 Specific embodiments of the method of the present invention are described in detail.

[0030] In an embodiment of the present invention, a 3D NAND three-dimensional memory device may include a substrate and a stacked structure formed on the substrate surface and stacked in a direction perpendicular to the substrate surface. In practical applications, the number of stacked layers in the stacked structure can be determined based on the number of memory cells to be formed in a direction perpendicular to the substrate surface. The number of stacked layers can be, for example, 8, 32, or 64 layers. The greater the number of stacked layers, the higher the degree of integration. Depending on the location and function, the stacked structure can be divided into a core portion and a stepped portion. The stepped portion is located on at least one side of the core portion. The core portion is used for data storage, and the stepped portion is used to lead to the wordline layer in the memory array.

[0031] In the semiconductor field, a substrate is used to form transistors or other semiconductor devices. The substrate is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, a SOi (Silicon on Insulator), or a Germanium on Insulator (GOI). The semiconductor substrate can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, TnP, or SiC. It can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium on Insulator).

[0032] In an embodiment of the present invention, the substrate may be, for example, a selection gate layer SGS. Figure 2As shown, the stacked structure includes alternating insulating layers and wordline layers WL0, WL1, ..., WLN formed on a select gate layer SGS. Here, the insulating layers may be silicon oxide (SiOx), including silicon dioxide and non-stoichiometric silicon oxide having more or less than two oxygen atoms per silicon atom, with silicon dioxide being preferred. The wordline layers are composed of a conductive material such as tungsten, copper, polysilicon, graphite, etc. In other embodiments, the insulating layers and wordline layers may also be made of other suitable materials.

[0033] It should be noted that Figure 2 Only part of the core portion and the step portion are shown in the figure. In practical applications, the step portion can be formed on both sides of the stacked structure, and the step portion can even be formed around the core portion.

[0034] Figure 2 A schematic diagram of a method for forming a word line electrode filling according to an embodiment of the present invention is shown, which includes steps b1 to b6. Each step is described below.

[0035] As shown in step b1, a stacked structure is formed on a horizontally arranged substrate, namely, select gate layer SGS, in a direction perpendicular to the horizontal direction. The stacked structure includes multiple insulating layers and multiple wordline layers WL0, WL1, ..., WLN, alternately stacked in the stacking direction. As shown in the figure, the stacked structure is formed with a stepped portion, which includes multiple steps. The insulating layers and wordline layers in the same layer have substantially the same length in a direction parallel to the substrate, and the insulating layers are located below the wordline layers. The lengths of the insulating layers and wordline layers in the direction parallel to the substrate at different layers are formed to increase in a direction toward the substrate.

[0036] Next, as shown in step b2, an etching stop layer is formed on the top of each step in the stacked structure to cover the upper surface of the word line layer. In the present invention, the etching stop layer serves as a stop layer for subsequent etching.

[0037] The material of the etch stop layer can be a material having a high etch selectivity with respect to the step gap fill material and a material having a high etch selectivity with respect to the material to be etched when the step contact hole is subsequently formed. As used herein, if during the etching process, the rate at which the first material is etched is different from the rate at which the second material is etched (for example, the former is at least twice the latter), then the etching of the first material is selective with respect to the second material. The ratio of the etching rate of the first material to the etching rate of the second material can be referred to as the selectivity of the first material with respect to the second material of the etching process.

[0038] In this embodiment, the etch stop layer can be formed by deposition, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In this embodiment, the material of the etch stop layer can be a nitride, for example, including but not limited to silicon nitride. In other embodiments, other suitable materials can also be selected as the etch stop layer material according to actual needs.

[0039] The thickness of the etch stop layer can be, for example, 50-200 nm, but is not limited thereto. It should be understood by those skilled in the art that the thickness of the etch stop layer can be selected according to actual needs.

[0040] After the above steps, depending on the layers exposed at different steps, each step in the stepped stack structure may include an etch stop layer, a word line layer, and an insulating layer (i.e., as shown in the figure, from top to bottom, the etch stop layer, the word line layer, and the insulating layer), or an etch stop layer and a select gate layer SGS (i.e., as shown in the figure, from top to bottom, the etch stop layer and the select gate layer SGS). It should be noted that the number of alternately stacked word line layers and insulating layers in each step is not limited to one, and may also be two, three, four, or more layers, without limitation.

[0041] Then, as shown in step b3, after forming the etch stop layer, a step gap filler material is used to fill the step gap, thereby forming a dielectric layer covering the stacked structure. The dielectric layer, i.e., the step gap filler material, is an insulating material, such as silicon oxide. The height of the dielectric layer is greater than the height of the topmost step of the stepped portion.

[0042] After the step gap is filled, as shown in step b4, a first etching operation is performed on the step portion of the stacked structure through the step gap filling material of the dielectric layer. The first etching operation uses the etch stop layer as a stop layer. The first etching operation can be performed using a dry etching method, such as plasma etching, ion milling etching, reactive ion etching, laser ablation, etc.

[0043] Through the first etching operation, a step contact hole is formed. The sidewalls of the step contact hole can be substantially vertical or tapered. Through this step, the step contact hole can extend from the upper surface of the dielectric layer to the upper surface of each etch stop layer. Because the material of the etch stop layer has a high etch selectivity with the step gap filler material, it is accordingly advantageous to control the first etching operation to stop when it reaches the etch stop layer.

[0044] In the present invention, the first etching operation can form all step contact holes on each level of steps through a single process.

[0045] Through the first etching operation, a portion of the surface of the etch stop layer formed on the corresponding step is exposed at each step by forming the step contact hole.

[0046] In addition, during the process of forming the step contact hole through the first etching operation, the etch stop layer can be etched to a certain depth while ensuring that the step contact hole does not penetrate through the etch stop layer.

[0047] Next, as shown in step b5, a second etching operation is performed on the step contact hole formed by the first etching operation. That is, in the second etching operation, the etch stop layer is etched to complete the step contact etching. The exposed etch stop layer is removed by the second etching operation, thereby exposing a portion of the surface of the word line layer located below the etch stop layer at each step through the step contact hole.

[0048] The second etching operation may be performed by dry etching, such as plasma etching, ion milling etching, reactive ion etching, laser ablation, etc.

[0049] Then, as shown in step b6, the step contact hole is filled with a metal material. A metal material refers to a conductive material containing at least one metal element. Filling the step contact hole forms a step contact structure serving as a word line electrode, thereby leading to the word line layer in the stacked structure.

[0050] It should be noted that the above-described process is merely an exemplary description, wherein some steps can be decomposed, and some steps can be combined or partially combined, so the actual implementation may be changed according to the actual situation.

[0051] Accordingly, the present invention also provides a three-dimensional memory device that can be manufactured using the above-described method. Specifically, the three-dimensional memory device provided by the present invention may include: a substrate and a stacked structure formed on the substrate in a direction perpendicular to the surface of the substrate, wherein insulating layers and conductive layers are alternately stacked in the stacked structure; the stacked structure includes a core portion and a stepped portion, wherein the stepped portion is located on at least one side of the core portion; an etch stop layer disposed on the upper surface of the stepped portion; a dielectric layer covering the stepped portion; and a stepped contact structure extending from the upper surface of the dielectric layer through the dielectric layer and the stacked etch stop layer to the upper surface of the conductive layer.

[0052] In the method and device for forming a three-dimensional memory device provided by the present invention, an etch stop layer is formed on top of the formed step through the etching process and structure described above, serving as an etch stop layer for the step contact etching process. This etch stop layer can reduce the requirements for etching selectivity, thereby facilitating control of etching rate and etching depth, and preventing etch punch-through. Furthermore, the etching process of the present invention allows for the simultaneous etching of multiple step contact holes through a single etching operation, thereby extending the service life of the etching equipment and achieving cost-effective process scaling.

[0053] It should be noted that the illustrations provided in the specific embodiments of the present invention are only used to illustrate the basic ideas of the present invention in a schematic manner. The illustrations only show components related to the present invention, rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity, positional relationship and proportion of each component can be changed on the premise of realizing the technical solution of the present invention, and the component layout form can also be more complex.

[0054] Although the present invention has been specifically described above with reference to the embodiments, the present invention is not limited thereto and can be implemented in various modifications and alternative forms. It should be understood by those skilled in the art that other and / or further modifications may be made thereto without departing from the technical concept of the present invention, and the present invention is intended to claim protection for all such embodiments that fall within the spirit and scope of the present invention.

Claims

1. A method for forming a three-dimensional memory device, the method comprising the following steps: i) providing a substrate, and forming a stacked structure on the substrate in a direction perpendicular to a surface of the substrate, wherein insulating layers and conductive layers are alternately stacked, and the stacked structure includes a core portion and a stepped portion, wherein the stepped portion is located on at least one side of the core portion; ii) forming an etching stop layer covering the upper surface of the conductive layer at the top of each step of the stepped portion; iii) after forming the etching stop layer, filling the step gap with a step gap filling material to form a dielectric layer covering the stacked structure; iv) after completing the step gap filling, performing a first etching operation on the step portion of the stacked structure through the step gap filling material of the dielectric layer to form a step contact hole, wherein the first etching operation uses an etch stop layer as a stop layer, and through the first etching operation, a portion of the surface of the etch stop layer is exposed at each step; v) performing a second etching operation on the step contact hole formed by the first etching operation to remove the exposed etching stop layer, thereby exposing a portion of the upper surface of the conductive layer at each step; and vi) filling the step contact hole to form a step contact structure.

2. The method according to claim 1, wherein The etch stop layer is formed by deposition.

3. The method according to claim 1, wherein The material of the etching stop layer is nitride.

4. The method according to claim 3, wherein: The material of the etching stop layer is silicon nitride.

5. The method according to claim 1, wherein The thickness of the etching stop layer is 50-200 nm.

6. The method according to claim 1, wherein The step contact holes are formed on each level of the steps through a single first etching process.

7. The method according to claim 1, wherein The sidewalls of the step contact hole are substantially vertical or tapered.

8. The method according to claim 1, wherein in, The substrate is a selection gate layer, the conductive layer is a word line layer, and the step contact structure is a word line electrode.

9. A three-dimensional memory device, comprising: a substrate and a stacked structure formed on the substrate in a direction perpendicular to a surface of the substrate, wherein insulating layers and conductive layers are alternately stacked; The stacking structure includes a core portion and a step portion, wherein the step portion is located on at least one side of the core portion; an etch stop layer disposed on an upper surface of the step portion; a dielectric layer covering the stepped portion; and A step contact structure extends from the upper surface of the dielectric layer through the dielectric layer and the stacked etch stop layer to the upper surface of the conductive layer.

10. The three-dimensional memory device according to claim 9, wherein The material of the etching stop layer is nitride.

11. The three-dimensional memory device according to claim 9, wherein The material of the etching stop layer is silicon nitride.

12. The three-dimensional memory device according to claim 9, wherein The thickness of the etching stop layer is 50-200 nm.

13. The three-dimensional memory device according to claim 9, wherein The substrate is a selection gate layer, the conductive layer is a word line layer, and the step contact structure is a word line electrode.

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