Flash memory device and forming method thereof

Abstract

The invention provides a flash memory device and a forming method thereof, and the forming method comprises the steps: providing a substrate which is provided with a plurality of shallow trench isolation parts formed in the substrate; forming a plurality of corresponding isolation parts on the shallow trench isolation parts, wherein the isolation parts have first stress; performing a surface treatment process on the plurality of surface portions of the isolation component to convert the first stress of the surface portions of the isolation component into second stress; forming a tunneling dielectric layer on the substrate; and forming a floating gate layer on the tunneling dielectric layer, wherein the floating gate layer contacts a surface portion of the isolation feature.

Description

Technical Field

[0001] The present application relates to a flash memory device and a method for forming the same, and more particularly to an isolation component of the flash memory device and a method for forming the same. Background Art

[0002] Flash memory is a non-volatile memory that offers high capacity, high read / write speeds, low power consumption, and low cost. Because of its non-volatile nature, data remains stored even after a power outage, making it widely used.

[0003] In coded flash memory, critical dimension (CD) scaling of memory cells can present challenges. For example, stress mismatch can cause cracks to form at the interface between a self-aligned floating gate (SAG) and adjacent isolation elements, leading to electrical and reliability issues. Therefore, a flash memory device and method for fabricating the same are needed to address these issues. Summary of the Invention

[0004] An embodiment of the present application provides a method for forming a flash memory device. The method includes providing a substrate having a plurality of shallow trench isolation features formed therein; forming a plurality of corresponding isolation features on the shallow trench isolation features, wherein the isolation features have a first stress; performing a surface treatment process on a plurality of surface portions of the isolation features to transform the first stress of the surface portions of the isolation features into a second stress; forming a tunneling dielectric layer on the substrate; and forming a floating gate layer on the tunneling dielectric layer, wherein the floating gate layer contacts the surface portions of the isolation features.

[0005] Embodiments of the present application provide a flash memory device comprising a substrate, a plurality of shallow trench isolation (STI) components, a plurality of isolation components, a tunneling dielectric layer, and a plurality of floating gates. The STI components are formed in the substrate. The isolation components are located on the respective STI components, wherein the isolation components have a surface portion and a central portion covered by the surface portion, wherein the central portion has a first stress, and the surface portion has a second stress. The tunneling dielectric layer is formed on the portion of the substrate not covered by the isolation components. Floating gates are formed on the tunneling dielectric layer and between the isolation components, wherein the floating gates contact the surface portions of the isolation components. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1-11 Schematic cross-sectional views of various process stages of a method for forming a flash memory device according to some embodiments of the present application.

[0007] Figure 12A 、 Figure 12B 、 Figure 12C for Figure 1 、 Figure 3 、 Figure 9 The outer surface profile and internal lattice atomic diagram of the isolation component of some embodiments of the present application are shown, which shows Figure 2 The implanted dopant atoms of the surface treatment process shown cause surface roughness and lattice stress variations in the isolation features.

[0008] Figure 13 for Figure 9 FIG. 1 is a partial enlarged schematic diagram showing that during the formation of the floating gate layer, dopants in the surface portion of the isolation feature diffuse into the floating gate layer.

[0009] Explanation of symbols

[0010] 200: substrate

[0011] 204: Shallow Trench Isolation Components

[0012] 206, 206R: Insulation pad

[0013] 208: Isolation components

[0014] 208T, 208T', 208T", 208T"', 220T: Top

[0015] 208S, 208S': Side

[0016] 208P: Surface part

[0017] 208C: Center

[0018] 212, 212R: Covering layer

[0019] 216: Tunneling dielectric layer

[0020] 218: floating gate layer

[0021] 220: floating gate

[0022] 222: Gate dielectric layer

[0023] 224: Control gate layer

[0024] 500: Flash memory device

[0025] 1000: Surface treatment process

[0026] 1000AT: Doping

[0027] AT1, AT2: lattice atoms

[0028] AT1F, AT2F: free lattice atoms

[0029] VC: lattice defect DETAILED DESCRIPTION

[0030] The present application is more fully described below with reference to the drawings illustrating embodiments of the present application. However, the present application may be implemented in a variety of different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numerals in the various drawings represent the same or similar elements.

[0031] Figures 1-11 Schematic cross-sectional view of various process stages of a method for forming a flash memory device 500 such as a coded flash memory according to an embodiment of the present application. Figure 1 As shown, a substrate 200 is provided. The substrate 200 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In one embodiment, the substrate 200 may be a silicon-on-insulator substrate. In this embodiment, the substrate 200 is a silicon substrate. The substrate 200 has a plurality of shallow trench isolation features 204 formed therein. The shallow trench isolation features 204 may be formed, for example, of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, a patterning process is used to define the formation locations of the shallow trench isolation features 204. Subsequently, a deposition process is used to deposit a dielectric material for the shallow trench isolation features 204. A planarization process, such as chemical mechanical polishing, is then used to remove excess dielectric material from the surface of the substrate 200 to form the shallow trench isolation features 204. Subsequently, a deposition process, such as thermal oxidation or chemical vapor deposition, may be performed to form an insulating pad layer 206 on the substrate 200. The insulating pad layer 206 is a pad oxide layer.

[0032] Then, a deposition process such as high density plasma chemical vapor deposition and a subsequent patterning process may be performed to form a plurality of corresponding isolation features 208 on the shallow trench isolation features 204. Figure 1 As shown, the isolation features 208 protrude from the substrate 200, such that a top surface 208T of the isolation features 208 and a side surface 208S connected to the top surface 208T are located above the substrate 200. Furthermore, the isolation features 208 are located directly above the corresponding shallow trench isolation features 204. The isolation features 208 may be silicon oxide. In one embodiment, the isolation features 208 have a compressive stress type, such as silicon oxide deposited using high-density plasma chemical vapor deposition.

[0033] Then, if Figure 2As shown, a surface treatment process 1000 is performed on the surface portion 208P of the isolation component 208 (the portion close to the top surface 208T and the side surface 208S). The surface treatment process 1000 may, for example, include an ion implantation process to implant dopants into the surface portion 208P of the isolation component 208. The dopants of the ion implantation process may, for example, include boron, carbon, silicon, germanium, nitrogen, phosphorus, arsenic, fluorine, argon, or a combination thereof. In one embodiment, the range of implantation energy, dopant dose, and implantation angle of the ion implantation process may be selected based on the geometric size and spacing of the isolation component 208 to implant dopants into the entire surface portion 208P of the isolation component 208. For example, the implantation energy of the ion implantation process may be 1 keV to 100 keV, and the dopant dose may be 1E10 atoms / cm 2 to 1E18 atoms / cm 2 , the injection angle can be 3 degrees to 30 degrees.

[0034] like Figure 3 As shown, after surface treatment process 1000, the physical properties of surface portion 208P of isolation feature 208 change (surface modification). For example, top surface 208T and side surface 208S of isolation feature 208 may be transformed into top surface 208T' and side surface 208S' with greater roughness. Furthermore, the stress type of surface portion 208P of isolation feature 208 may change from compressive stress to tensile stress or neutral stress. Alternatively, the compressive stress value of surface portion 208P of isolation feature 208 after surface treatment process 1000 may be lower than the compressive stress value before surface treatment process 1000. In one embodiment, center portion 208C covered by surface portion 208P maintains the compressive stress type.

[0035] Then Figure 12A 、 Figure 12B The effect of the surface treatment process 1000 on the isolation member 208 is further described. Figure 12A 、 Figure 12B for Figure 1 、 Figure 3 The outer surface profile of the isolation member 208 (for example, the surface profile of the side surface 208S or the top surface 208T) and the internal lattice atom diagram are shown, which show the surface roughness and lattice stress changes of the isolation member 208 before and after the surface treatment process 1000. Please also refer to Figure 1 、 Figure 12AFor example, the crystal lattice of isolation feature 208, made of silicon oxide, may be composed of an alternating arrangement of oxygen lattice atoms AT1 and silicon lattice atoms AT2. Prior to surface treatment process 1000, the outer surface of isolation feature 208 (including side surface 208S and top surface 208T) is substantially smooth. Furthermore, surface portion 208P and center portion 208C of isolation feature 208 exhibit a compressive stress type.

[0036] Please also refer to Figure 2 、 Figure 3 、 Figure 12B During a surface treatment process 1000, such as an ion implantation process, on isolation feature 208, high-energy dopants (or dopant atoms) 1000AT first bombard the side surfaces 208S or top surface 208T of isolation feature 208, increasing surface roughness. These dopants then collide with some lattice atoms AT1 and AT2 on surface portion 208P of isolation feature 208, resulting in energy transfer. The collided lattice atoms AT1 and AT2 gain energy, leaving their original lattice positions and becoming free lattice atoms AT1F and AT2F, creating lattice defects VC at their original lattice positions. The free lattice atoms AT1F and AT2F then collide with lattice atoms AT1 and AT2 at other lattice positions in surface portion 208P, generating more free lattice atoms AT1F and AT2F that enter the lattice interstices of central portion 208C of isolation feature 208. Therefore, after surface treatment process 1000, the outer surface of isolation feature 208 is transformed into a roughened surface (including top surface 208T' and side surface 208S'). In other words, the roughness of top surface 208T' and side surface 208S' of isolation feature 208 is greater than the roughness of top surface 208T and side surface 208S. Furthermore, after surface treatment process 1000, the stress type of surface portion 208P of isolation feature 208 is transformed from compressive stress to tensile stress or neutral stress (or the original compressive stress value is reduced), while the stress type of central portion 208C of isolation feature 208 remains the original stress type (compressive stress).

[0037] like Figure 4 As shown, during the surface treatment process 1000 ( Figure 2 ), a deposition process such as atomic layer deposition may be performed to conformally form a capping layer 212 on the substrate 200 and the top surface 208T' and the side surface 208S' of the isolation component 208. The capping layer 212 may be used to protect the surface portion 208P of the isolation component 208 from being damaged during the subsequent etching process for removing the insulating pad layer 206. In one embodiment, the insulating pad layer 206 and the capping layer 212 are made of different materials. Furthermore, the isolation component 208 and the capping layer 212 include different materials. For example, the isolation component 208 and the insulating pad layer 206 are made of silicon oxide, and the capping layer 212 is made of silicon nitride.

[0038] Then, if Figure 5 As shown, an etching process such as dry etching may be performed to remove the capping layer 212 on the substrate 200 and the top surface 208T′ of the isolation feature 208, thereby exposing the top surface 208T′ of the isolation feature 208 and the insulating pad layer 206 not covered by the isolation feature 208. The capping layer remaining on the side surface 208S′ of the isolation feature 208 is labeled as a capping layer 212R.

[0039] Then, if Figure 6 As shown, an etching process such as dry etching or wet etching may be performed to remove the insulating pad layer 206 not covered by the isolation feature 208 to expose the substrate 200. The remaining insulating pad layer covered by the isolation feature 208 is labeled as insulating pad layer 206R.

[0040] Then, if Figure 7 As shown, an etching process such as a wet etch process may be performed to selectively remove the capping layer 212R on the side surfaces 208S′ of the isolation features 208 to expose the side surfaces 208S′ of the isolation features 208. Since the capping layer 212R, such as silicon nitride, has a high etching selectivity with respect to the isolation features 208, such as silicon oxide, the removal of the capping layer 212R does not damage the top surfaces 208T′ and the side surfaces 208S′ of the isolation features 208.

[0041] Then, if Figure 8 As shown, a tunnel dielectric layer 216 is formed on the substrate 200 that is not covered by the isolation feature 208. The tunnel dielectric layer 216 may be adjacent to the insulating pad layer 206R, and both may be made of the same or similar material, such as silicon oxide. In one embodiment, the tunnel dielectric layer 216 may be formed by thermal oxidation or chemical vapor deposition.

[0042] Then, if Figure 9 As shown, a deposition process may be performed to form a floating gate layer 218, such as amorphous silicon or polycrystalline silicon, on the tunnel dielectric layer 216. Subsequently, an annealing process, such as rapid thermal annealing, may be performed to convert the amorphous silicon into polycrystalline silicon. The temperature of the annealing process may be 850 degrees Celsius to 950 degrees Celsius, for example, 900 degrees Celsius. In one embodiment, the floating gate layer 218 contacts the surface portion 208P of the isolation component 208 (contacting the top surface 208T' and the side surface 208S' of the isolation component 208). Also refer to Figure 12C This is to further illustrate the interface state between the floating gate layer 218 and the isolation component 208 with surface modification. Figure 12C As shown, due to the surface treatment process 1000 ( Figure 2) can improve the surface roughness of the isolation component 208. When the floating gate layer 218 contacts the rougher top surface 208T' and side surface 208S' of the isolation component 208, the adhesion between the floating gate layer 218 and the isolation component 208 can be increased, thereby preventing cracks from forming at the interface between the floating gate layer 218 and the isolation component 208 (i.e., the top surface 208T' and the side surface 208S') due to stress mismatch between the floating gate layer 218 and the isolation component 208.

[0043] Figure 13 for Figure 9 , which shows that during the annealing process for forming the floating gate layer 218, the dopant 1000AT in the surface portion 208P of the isolation member 208 diffuses into the floating gate layer 218. It is particularly noted that the dopant 1000AT diffused into the floating gate layer 218 during the annealing process can also inhibit the chip growth of the floating gate layer 218, such as polysilicon, thereby preventing stress changes in the floating gate layer 218 caused by the high-temperature annealing process, which may cause cracks to form at the interface between the floating gate layer 218 and the isolation member 208, thereby affecting the electrical performance and reliability of the final flash memory device.

[0044] Then, if Figure 10 As shown, a planarization process such as chemical mechanical polishing may be performed to remove a portion of the floating gate layer 218 and the modified portion of the top surface 208T' of the isolation feature 208 until the central portion 208C of the isolation feature 208 is exposed, thereby forming a plurality of floating gates 220 between the isolation features 208. Figure 10 As shown, after the planarization process, the top surface 220T of the floating gate 220 may be coplanar with the top surface 208T″ of the isolation feature 208. In addition, the roughness of the top surface 208T″ of the isolation feature 208 may be less than the roughness of the side surface 208S′ of the isolation feature 208. In this embodiment, the floating gate 220 is formed in a self-aligned manner and contacts the side surface 208S′ of the isolation feature 208.

[0045] Then, if Figure 11As shown, the isolation member 208 can be selectively etched by, for example, wet etching using hydrofluoric acid (HF) immersion, so that the floating gate 220 protrudes from the isolation member 208. Specifically, after the selective etching, the top surface 208T'' of the isolation member 208 is lower than the top surface 220T of the floating gate 220, and a portion of the side surface of the floating gate 220 is located above the top surface 208T'' of the isolation member 208. Then, a deposition process such as chemical vapor deposition or atomic layer deposition can be performed to conformally form a gate dielectric layer 222 on the selectively etched isolation member 208 and the top surface 220T and a portion of the side surface of the floating gate 220. The gate dielectric layer 222 may contact the top surface 208T'' of the isolation feature 208. The gate dielectric layer 222 may include silicon oxide, silicon nitride, silicon oxynitride, or a triple-layer structure including silicon oxide / silicon nitride / silicon oxide (ONO). Since no cracks exist at the interface between the floating gate 220 and the surface-modified isolation feature 208, the etching solution that selectively etches the isolation feature 208 will not corrode the tunneling dielectric layer beneath the floating gate 220, allowing the subsequently formed gate dielectric layer 222 to contact the substrate 200, thereby improving the electrical performance and reliability of the resulting flash memory device.

[0046] Afterwards, please refer to Figure 11 A deposition process such as chemical vapor deposition may be performed to form a control gate layer 224 on the gate dielectric layer 222 to form the flash memory device 500. In one embodiment, the control gate layer 224 includes polysilicon or other conductive material layers.

[0047] like Figure 11As shown, a flash memory device 500 includes a substrate 200, a plurality of shallow trench isolation features 204, a plurality of isolation features 208, a tunnel dielectric layer 216, a plurality of floating gates 220, a gate dielectric layer 222, and a control gate layer 224. The shallow trench isolation features 204 are formed in the substrate 200. The isolation features 208 are located on the corresponding shallow trench isolation features 204. The isolation features 208 have a surface portion 208P and a central portion 208C covered by the surface portion. In one embodiment, the central portion 208C of the isolation features 208 has a first stress, and the surface portion 208P has a second stress different from the first stress. The isolation features 208 have a top surface 208T'' and a plurality of side surfaces 208S' connected to the top surface 208T''. In one embodiment, a top surface 208T″′ of the isolation feature 208 has a first roughness, and a side surface 208S′ has a second roughness, the second roughness being greater than the first roughness. A surface portion 208P of the isolation feature 208 may have a dopant comprising boron, carbon, silicon, germanium, nitrogen, phosphorus, arsenic, fluorine, argon, or a combination thereof. A tunneling dielectric layer 216 is formed on the substrate 200 not covered by the isolation feature 208. A floating gate 220 is formed on the tunneling dielectric layer 216 and is located between the isolation features 208. The floating gate 220 contacts the surface portion 208P of the isolation feature 208, for example, contacts the side surface 208S′ of the isolation feature 208. The floating gate 220 may have a dopant comprising carbon, nitrogen, argon, or a combination thereof. A gate dielectric layer 222 of the flash memory device 500 is formed on the isolation feature 208 and the floating gate 220. A control gate layer 224 is formed on the gate dielectric layer 222.

[0048] Although the present application is disclosed above with reference to the aforementioned embodiments, they are not intended to limit the present application. Persons skilled in the art may make modifications and improvements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the claims.

Claims

1. A method for forming a flash memory device, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of shallow trench isolation features formed therein; forming a plurality of corresponding isolation features on the shallow trench isolation feature, wherein the isolation features have a first stress; performing a surface treatment process on a plurality of surface portions of the isolation component to transform the first stress of the surface portions of the isolation component into a second stress; forming a tunnel dielectric layer on the substrate; as well as A floating gate layer is formed on the tunnel dielectric layer, wherein the floating gate layer contacts the surface portion of the isolation component.

2. The method for forming a flash memory device according to claim 1, wherein: The surface portion of the isolation member has a first roughness before the surface treatment process, and the surface portion of the isolation member has a second roughness after the surface treatment process, wherein the second roughness is greater than the first roughness.

3. The method for forming a flash memory device according to claim 1, wherein: The surface treatment process includes an ion implantation process.

4. The method for forming a flash memory device according to claim 3, wherein: The ion implantation process implants a dopant into the surface portion of the isolation feature.

5. The method for forming a flash memory device according to claim 4, wherein: The dopant includes boron, carbon, silicon, germanium, nitrogen, phosphorus, arsenic, fluorine, argon or a combination thereof.

6. The method for forming a flash memory device according to claim 4, wherein: Also includes: After forming the floating gate layer, an annealing process is performed to diffuse the dopants in the surface portion of the isolation feature into the floating gate layer.

7. The method for forming a flash memory device according to claim 1, wherein: The first stress is a compressive stress, and wherein the second stress is a tensile stress or a neutral stress.

8. The method for forming a flash memory device according to claim 1, wherein: The first stress and the second stress are compressive stresses, and a first stress value of the first stress is greater than a second stress value of the second stress.

9. The method for forming a flash memory device according to claim 1, wherein: Each of the isolation members has a central portion covered by the surface portion, and after the surface treatment process is performed, the central portion has the first stress.

10. The method for forming a flash memory device according to claim 1, wherein: Also includes: Before forming the isolation component, forming an insulating pad layer on the substrate; After performing the surface treatment process, forming a capping layer on the substrate and the surface portion of the isolation component; removing the capping layer on the substrate and on top surfaces of the isolation components; removing the insulating pad layer not covered by the isolation component to expose the substrate; as well as The capping layer on the sidewalls of the isolation member is removed.

11. The method for forming a flash memory device according to claim 1, wherein: Also includes: After forming the floating gate layer, performing a planarization process to remove a portion of the floating gate layer and the surface portions at multiple top surfaces of the isolation components to form multiple floating gates; selectively etching the isolation component; forming a gate dielectric layer on the selectively etched isolation component and the floating gate; as well as A control gate layer is formed on the gate dielectric layer.

12. The method for forming a flash memory device according to claim 11, wherein: The isolation member has a plurality of side surfaces connected to the top surface, and after the planarization process is performed, a roughness of the top surface of the isolation member is smaller than a roughness of the side surfaces.

13. A flash memory device, characterized in that: include: a substrate; a plurality of shallow trench isolation components formed in the substrate; a plurality of isolation features located on corresponding shallow trench isolation features, wherein each isolation feature has a surface portion and a central portion covered by the surface portion, wherein the central portion has a first stress and the surface portion has a second stress; a tunnel dielectric layer formed on the substrate not covered by the isolation member; as well as A plurality of floating gates are formed on the tunnel dielectric layer and located between the isolation components, wherein the floating gates contact the surface portions of the isolation components.

14. The flash memory device according to claim 13, wherein: Each of the isolation components has a top surface and a plurality of side surfaces connected to the top surface, wherein the floating gate contacts the side surfaces of the isolation component, wherein the top surface has a first roughness, and the side surfaces have a second roughness, and wherein the second roughness is greater than the first roughness.

15. The flash memory device according to claim 13, wherein: Also includes: a gate dielectric layer formed on the isolation member and the floating gate; and A control gate layer is formed on the gate dielectric layer.

16. The flash memory device according to claim 13, wherein: The surface portion of the isolation feature has a first dopant, wherein the first dopant includes boron, carbon, silicon, germanium, nitrogen, phosphorus, arsenic, fluorine, argon, or a combination thereof.

17. The flash memory device according to claim 13, wherein: The floating gate has a second dopant, wherein the second dopant includes carbon, nitrogen, argon or a combination thereof.

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