Silicon carbide power device and preparation method thereof

Abstract

The invention provides a silicon carbide power device and a preparation method thereof. The silicon carbide power device comprises a substrate; the silicon carbide epitaxial layer is arranged on the surface of the substrate; the gate structure is arranged on the surface of the silicon carbide epitaxial layer or arranged in the silicon carbide epitaxial layer; the JFET region is arranged on the silicon carbide epitaxial layer; and the high-resistance region is arranged in the JFET region and is positioned below the gate structure, and the high-resistance region is formed by doping a deep-energy-level dopant matched with silicon carbide. The performance of the silicon carbide power device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide power device and a preparation method thereof. Background Art

[0002] SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) power devices are widely used in new energy vehicles, transportation rails, photovoltaics and other industries due to their advantages such as high voltage and high temperature resistance, high frequency, low power loss and high switching speed.

[0003] Among them, silicon carbide power devices with a Planar MOS structure are widely used in applications requiring high-performance power switches, such as power management, electric vehicle control, and inverters, due to their advantages such as low on-resistance, high withstand voltage, and high switching speed. However, with the further development of electronic control technology for new energy vehicles, higher requirements are being placed on silicon carbide power devices in terms of reducing costs and improving withstand voltage. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides a silicon carbide power device, comprising:

[0005] substrate;

[0006] A silicon carbide epitaxial layer is provided on the surface of the substrate;

[0007] a gate structure, disposed on the surface of the silicon carbide epitaxial layer or in the silicon carbide epitaxial layer;

[0008] A JFET region is provided in the silicon carbide epitaxial layer;

[0009] A high resistance region is provided in the JFET region and contacts the gate structure, wherein the high resistance region is doped with a deep energy level dopant that matches silicon carbide.

[0010] Optionally, the deep level dopant includes any one or more of vanadium ions, iron ions, oxygen ions and magnesium ions.

[0011] Optionally, the doping concentration of the high resistance region is 10 16 ~10 20 / cm 3 .

[0012] Optionally, the silicon carbide power device is a planar gate power device, which includes a P-type body region, a source region and a planar gate structure. The P-type body region is arranged in the silicon carbide epitaxial layer, the source region is arranged in the P-type body region, the JFET region is located between two adjacent P-type body regions, the planar gate structure is located on the JFET region, and the high resistance region is located in the JFET region under the planar gate structure. The high resistance region has a first preset spacing distance from the P-type body regions on both sides.

[0013] Optionally, the width of the high resistance region is less than or equal to 80% of the width of the JFET region.

[0014] Optionally, the thickness of the high resistance region is 0.5 to 2 times the thickness of the P-type body region.

[0015] Optionally, the planar gate power device is a planar IGBT device or a planar MOS device.

[0016] Optionally, the silicon carbide power device is a trench gate power device, which includes a P-type body region, a source region and a trench gate structure. The P-type body region is arranged in the silicon carbide epitaxial layer, the trench gate structure penetrates the P-type body region, the source region is arranged in the P-type body region and contacts the outer wall of the trench gate structure, the JFET region is the region in the silicon carbide epitaxial layer surrounding the portion of the P-type body region extending out of the trench gate structure, the high resistance region is located in the JFET region at the bottom of the trench gate structure and its surroundings, and the high resistance region has a second preset spacing distance from the P-type body region.

[0017] Optionally, the width of the high resistance region is 0.1 to 2 times the width of the trench gate.

[0018] Optionally, the trench gate power device is a trench IGBT device or a trench MOS device.

[0019] According to another aspect of the present invention, a method for preparing a silicon carbide power device is also provided, comprising:

[0020] providing a substrate, and forming a silicon carbide epitaxial layer on a surface of the substrate;

[0021] forming a JFET region in the silicon carbide epitaxial layer;

[0022] A high resistance region and a gate structure are formed, wherein the gate structure is arranged on or in the silicon carbide epitaxial layer, the high resistance region is arranged in the JFET region and contacts the gate structure, and the high resistance region is doped with a deep energy level dopant that matches silicon carbide.

[0023] In summary, the present invention provides a silicon carbide power device and a preparation method thereof, wherein the silicon carbide power device includes a substrate, a silicon carbide epitaxial layer, a gate structure, a JFET region and a high resistance region. The silicon carbide epitaxial layer is provided on the surface of the substrate. The gate structure is provided on the surface of the silicon carbide epitaxial layer or in the silicon carbide epitaxial layer. The JFET region is provided in the silicon carbide epitaxial layer. The high resistance region is provided in the JFET region and is located below the gate structure, and the high resistance region is doped with a deep energy level dopant that matches silicon carbide. In the present application, the high resistance region is located in the JFET region under the gate structure, has a higher resistance than the JFET region, can push the electric field on the lower surface of the gate structure to the N-drift region, can effectively curb the excessive electric field strength on the lower surface of the gate structure, thereby improving the reliability of the silicon carbide power device. More importantly, the high-resistance region is doped with corresponding deep-level dopants. The deep-level dopants in the high-resistance region can serve as recombination centers (or traps) for non-radiative recombination carriers, and its high-resistance performance is intrinsic, rather than relying on the outside to form a PN structure. Therefore, the high-resistance region can exert a smaller impact on the surrounding area (such as the JFET region or the N-drift layer), that is, the high-resistance region has a smaller impact on the current path around the high-resistance region (it does not occupy the current path of the JFET region, so as not to affect the current conduction capability), thereby minimizing or avoiding the impact on the on-resistance of the power device while improving the reliability of the power device (including improving the withstand voltage). BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0025] Figure 1 is a schematic cross-sectional view of a planar MOS device provided in an embodiment of the present application;

[0026] Figure 2 is a schematic cross-sectional view of a planar gate IGBT device provided in an embodiment of the present application;

[0027] Figure 3 is a schematic cross-sectional view of a trench MOS device provided in an embodiment of the present application;

[0028] Figure 4 is a schematic cross-sectional view of a trench gate IGBT device provided in an embodiment of the present application;

[0029] Figure 5 A flow chart of a method for preparing a silicon carbide power device provided in an embodiment of the present application;

[0030] Figure 6A A schematic diagram of forming a silicon carbide epitaxial layer according to an embodiment of the present application;

[0031] Figure 6B A schematic diagram of forming a P-type body region and a JFET region according to an embodiment of the present application;

[0032] Figure 6C A schematic diagram of forming an N+ source region provided in an embodiment of the present application;

[0033] Figure 6D A schematic diagram of forming a second patterned mask provided in an embodiment of the present application;

[0034] Figure 6E A schematic diagram of forming a high resistance region provided in an embodiment of the present application;

[0035] Figure 6F A schematic diagram of forming a P+ contact region provided in an embodiment of the present application;

[0036] Figure 6G A schematic diagram of forming a gate structure provided in an embodiment of the present application;

[0037] Figure 6H A schematic diagram of forming an N+ drain layer and a back metal layer according to an embodiment of the present application.

[0038] In the accompanying drawings: 10-substrate; 11-buffer layer; 12-silicon carbide epitaxial layer; 13-first patterned mask; 14-ion implantation protection layer; 15-P-type body region; 15a-channel; 16-N-drift region; 21-JFET region; 22-sidewall structure; 23-N+ source region; 24-second patterned mask; 25-high resistance region; 26-P+ body contact region; 27-planar gate structure; 27a-gate dielectric layer; 27b-gate conductive layer; 28-N+ drain region; 29-back metal layer; 30-trench; 31-trench gate structure; 31a-gate dielectric layer; 31b-gate conductive layer; 32-P+ collector region; 33-back metal layer. DETAILED DESCRIPTION

[0039] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0040] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or portion discussed below may be represented as a second element, component, region, layer, or portion. Spatially relative terms such as "under," "below," "below," "above," "above," etc. may be used herein for convenience of description to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are intended to also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, then, the elements or features described as "under...", "below," or "below" will be oriented as "on" other elements or features. The device can be oriented differently (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly. The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "one," "an," and "said / the" are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "including" is used to determine the presence of features, steps, operations, elements, and / or parts, but does not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] Figure 1 This is a schematic cross-sectional view of a planar MOS device provided in an embodiment of the present application.

[0042] like Figure 1As shown, the silicon carbide power device provided in an embodiment of the present application can be a planar MOS device, which is provided on a substrate 10. The substrate 10 includes opposite front and back surfaces. The planar MOS device provided in the present application includes, in a direction away from the back surface of the substrate 10, a back metal layer 29, an N+ drain region 28, an N-drift layer 16, a P-type body region 15, a JFET region 21, a high resistance region 25, a planar gate structure 27, a front metal layer, and a passivation layer. The back metal layer 29 is located on the back surface of the substrate 10. The material of the substrate 10 can be a semiconductor substrate material such as silicon carbide or silicon. The substrate 10 can also be a thinned semiconductor substrate, and the N+ drain region 28 is located within the thinned substrate.

[0043] For some examples, please refer to Figure 1 The front surface of the substrate 10 may be provided with a buffer layer 11 and a silicon carbide epitaxial layer 12 in this order. The aforementioned N-drift layer 16, P-type body region 15, JFET region 21, and high-resistance region 25 are all provided in the silicon carbide epitaxial layer 12. The planar gate structure 27, front metal layer, and passivation layer are all located on the surface of the silicon carbide epitaxial layer 12. The doping type and doping concentration of the silicon carbide epitaxial layer 12 are the same as those of the N-drift layer 16. In other words, the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 close to the substrate 10, or the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 excluding the P-type body region 15 and the JFET region 21. At least two P-type body regions 15 are spaced apart on the side of the silicon carbide epitaxial layer 12 away from the substrate 10. The silicon carbide epitaxial layer 12 (or N-drift layer 16) between adjacent P-type body regions 15 constitutes the JFET region 21. Each P-type body region 15 is provided with an N+ source region 23 and a P+ body contact region 26. The N+ source region 23 is in contact with the P+ body contact region 26. The N+ source region 23 is located near the JFET region 21, while the P+ body contact region 26 is located away from the JFET region 21. The portion of the P-type body region 15 between the N+ source region 23 and the JFET region 21 may constitute a channel 15a. A planar gate structure 27 covers the surface of the silicon carbide epitaxial layer 12 in the JFET region 21 and the channels 15a on both sides thereof, and may extend to cover a portion of the surface of the silicon carbide epitaxial layer 12 in the N+ source region 23. The planar gate structure 27 may include a gate dielectric layer 27a and a gate conductive layer 27b formed sequentially. The gate dielectric layer 27a covers the surface of the silicon carbide epitaxial layer 12, and the gate conductive layer 27b covers the surface of the gate dielectric layer 27a.

[0044] Please continue to refer to Figure 1 The high-resistance region 25 is disposed in the JFET region 21 and contacts the bottom of the planar gate structure 27. It is also spaced apart from the P-type body regions 15 on both sides of the JFET region 21. In other words, the top of the high-resistance region 25 contacts the gate dielectric layer 27a. It is understood that in other embodiments, it is also feasible that the top of the high-resistance region 25 does not contact the bottom of the gate dielectric layer 27a.

[0045] The high-resistance region 25 has a first predetermined spacing distance D1 between its two ends along the channel extension direction and the channels 15a on both sides. This first predetermined spacing distance D1 can be determined by the power device's requirements for on-resistance and breakdown voltage. For example, the lower the required on-resistance, the longer the first predetermined spacing distance can be, and the higher the required breakdown voltage, the shorter the first predetermined spacing distance can be. In some examples, the first predetermined spacing distance can be greater than or equal to 10% of the width of the JFET region 21 (i.e., the width of the high-resistance region 25 is less than or equal to 80% of the width of the JFET region 21), taking into account both on-resistance and breakdown voltage. In addition, in addition to being located in the JFET region 21, the high-resistance region 25 can also extend into the N-drift layer 16 below the JFET region 21. Therefore, the thickness of the high-resistance region 25 is between 0.5 and 2 times the thickness of the body region (i.e., the thickness of the JFET region 21). The thickness of the high-resistance region 25 can be set based on the doping concentration of the high-resistance region 25 and in combination with the on-resistance and breakdown voltage of the power device. In some examples, the doping concentration of the high resistance region 25 may be 10 16 ~10 20 / cm 3 .

[0046] It should be noted that the high-resistance region is doped with deep-level dopants compatible with silicon carbide. These deep-level dopants may include any one or more of vanadium, iron, oxygen, and magnesium ions. This high-resistance region, located in the JFET region beneath the gate structure, has a higher resistance than the JFET region and can push the electric field from the lower surface (bottom) of the gate structure toward the N-drift region, effectively preventing excessive electric field strength at the lower surface of the gate structure and thereby improving the reliability of the silicon carbide power device. On the other hand, the high resistance region is doped with corresponding deep energy level dopants. The deep energy level dopants in the high resistance region can serve as recombination centers (or traps) for non-radiative recombination carriers. Its high resistance performance is intrinsic, rather than relying on the outside to form a PN structure. Therefore, the high resistance region can exert a smaller influence on the surrounding area (such as the JFET region or the N-drift layer), that is, the high resistance region has a smaller influence on the current path around the high resistance region (it does not occupy the current path of the JFET region, so as not to affect the current conduction capability), thereby minimizing or avoiding the impact on the on-resistance of the power device while improving the reliability of the power device (including improving the withstand voltage).

[0047] In an example opposite to the embodiment of the present application (i.e., a counterexample), a P-type doped region is formed in the JFET region under the gate structure. This P-type doped region and the JFET region form a PN structure (high resistance) to increase the breakdown voltage. However, the withstand voltage provided by the PN structure is not stable and is affected by multiple factors such as bias voltage, temperature, and switching frequency, making it prone to failure. Moreover, the P-type doped region will also form hole diffusion after injection (i.e., the P-type doped region and the JFET region form a PN structure), squeezing the current path of the JFET region and seriously affecting the on-resistance of the power device. Alternatively, to reduce the impact on the on-resistance (to ensure current conduction capability), the width of the JFET region is increased, which in turn requires increasing the pitch (spacing), which increases the chip area and the cost accordingly.

[0048] Figure 2 This is a schematic cross-sectional view of a planar gate IGBT device provided in an embodiment of the present application.

[0049] like Figure 2 As shown, the silicon carbide power device provided in the embodiment of the present application can be a planar gate IGBT (planar IGBT) device, which is provided on a substrate 10. The substrate 10 includes a front side and a back side. The planar gate IGBT device provided in the present application includes a back metal layer 33, a P+ collector region 32, an N+ field stop layer (not shown), an N-drift region 16, a P-type body region 15, a JFET region 21, a high resistance region 25, a planar gate structure 27, a front metal layer, and a passivation layer, which are arranged in sequence along the direction away from the back side of the substrate 10. Among them, the back metal layer 33 is located on the back side of the substrate 10. The material of the substrate 10 can be a semiconductor substrate material such as silicon carbide and silicon. The substrate 10 can also be a thinned semiconductor substrate. The P+ collector region 32 and the N+ field stop layer can be located within the thinned substrate.

[0050] For some examples, please refer to Figure 1A silicon carbide epitaxial layer 12 may be provided on the front surface of the substrate 10. The aforementioned N+ field stop layer, N-drift region 16, P-type body region 15, JFET region 21, and high resistance region 25 are all provided in the silicon carbide epitaxial layer 12. The planar gate structure 27, front metal layer, and passivation layer are all located on the surface of the silicon carbide epitaxial layer 12. At least two P-type body regions 15 are spaced apart on a side of the silicon carbide epitaxial layer 12 away from the substrate 10. The silicon carbide epitaxial layer 12 (or N-drift layer 16) between adjacent P-type body regions 15 constitutes the JFET region 21. Each P-type body region 15 is provided with an N+ source region 23 (or emitter region) and a P+ body contact region 26. The N+ source region 23 is in contact with the P+ body contact region 26. The N+ source region 23 is located near the JFET region 21, and the P+ body contact region 26 is located away from the JFET region 21. The portion of the P-type body region 15 between the N+ source region 23 and the JFET region 21 may be a channel 15a. A planar gate structure 27 covers the surface of the silicon carbide epitaxial layer 12 in the JFET region 21 and the channels 15a on both sides thereof, and may extend to cover a portion of the surface of the silicon carbide epitaxial layer 12 in the N+ source region 23. The planar gate structure 27 may include a gate dielectric layer 27a and a gate conductive layer 27b formed in sequence. The gate dielectric layer 27a covers the surface of the silicon carbide epitaxial layer 12, and the gate conductive layer 27b covers the surface of the gate dielectric layer 27a.

[0051] Please continue to refer to Figure 2 The high-resistance region 25 is disposed in the JFET region 21 and contacts the bottom of the planar gate structure 27, and is spaced apart from the P-type body regions 15 on both sides of the JFET region 21. In other words, the top of the high-resistance region 25 contacts the gate dielectric layer 27a. It will be appreciated that in other embodiments, it is also feasible that the top of the high-resistance region 25 does not contact the bottom of the gate dielectric layer 27a.

[0052] The high resistance region 25 has a first preset spacing distance D1 between both ends of the channel extension direction and the channels 15a on both sides, and the first preset spacing distance can be determined by the power device's requirements for on-resistance and breakdown voltage. For example, the smaller the required on-resistance, the longer the first preset spacing distance can be, and the higher the required breakdown voltage, the smaller the first preset spacing distance can be. In some examples, the first preset spacing distance can be greater than or equal to 10% of the width of the JFET region 21 (i.e., the width of the high resistance region 25 is less than or equal to 80% of the width of the JFET region 21), so as to take into account both on-resistance and breakdown voltage. In addition, the high resistance region 25 may not only be located in the JFET region 21, but may also extend into the N-drift layer 16 below the JFET region 21. Therefore, the thickness of the high resistance region 25 is between 0.5 and 2 times the thickness of the P-type body region 15 (i.e., the thickness of the JFET region 21). The thickness of the high resistance region 25 may be set based on the doping concentration of the high resistance region 25 and the on-resistance and breakdown voltage of the power device. In some examples, the doping concentration of the high resistance region 25 may be 10 16~10 20 / cm 3 .

[0053] It should be noted that the high-resistance region is doped with deep-level dopants compatible with silicon carbide. These deep-level dopants may include any one or more of vanadium, iron, oxygen, and magnesium ions. This high-resistance region, located in the JFET region beneath the gate structure, has a higher resistance than the JFET region and can push the electric field from the lower surface (bottom) of the gate structure toward the N-drift region, effectively preventing excessive electric field strength at the lower surface of the gate structure and thereby improving the reliability of the silicon carbide power device. On the other hand, the high resistance region is doped with corresponding deep energy level dopants. The deep energy level dopants in the high resistance region can serve as recombination centers (or traps) for non-radiative recombination carriers. Its high resistance performance is intrinsic, rather than relying on the outside to form a PN structure. Therefore, the high resistance region can exert a smaller influence on the surrounding area (such as the JFET region or the N-drift layer), that is, the high resistance region has a smaller influence on the current path around the high resistance region (it does not occupy the current path of the JFET region, so as not to affect the current conduction capability), thereby minimizing or avoiding the impact on the on-resistance of the power device while improving the reliability of the power device (including improving the withstand voltage).

[0054] Figure 3 This is a schematic cross-sectional view of a trench MOS device provided in an embodiment of the present application.

[0055] like Figure 3 As shown, the silicon carbide power device provided in an embodiment of the present application can be a trench MOS device, which is provided on a substrate 10. The substrate 10 includes opposite front and back surfaces. The trench 30-gate trench MOS device provided in the present application includes, in a direction away from the back surface of the substrate 10, a back metal layer 29, an N+ drain region 28, an N-drift layer 16, a P-type body region 15, a JFET region 21, a high-resistance region 25, a trench gate structure 31, a front metal layer, and a passivation layer. The back metal layer 29 is located on the back surface of the substrate 10. The material of the substrate 10 can be a semiconductor substrate material such as silicon carbide or silicon. The substrate 10 can also be a thinned semiconductor substrate, and the N+ drain region 28 is located within the thinned substrate.

[0056] For some examples, please refer to Figure 3The front surface of the substrate 10 may be provided with a buffer layer 11 and a silicon carbide epitaxial layer 12 in sequence. The aforementioned N-drift layer 16, P-type body region 15, JFET region 21, high resistance region 25, and trench gate structure 31 are all provided in the silicon carbide epitaxial layer 12. The front metal layer and passivation layer are both located on the surface of the silicon carbide epitaxial layer 12. The doping type and doping concentration of the silicon carbide epitaxial layer 12 are the same as those of the N-drift layer 16. In other words, the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 that is close to the substrate 10, or the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 excluding the P-type body region 15, the JFET region 21, and the trench gate structure 31. A trench 30 is provided in the silicon carbide epitaxial layer 12 on the side away from the substrate 10. A trench gate structure 31 is provided in the trench 30. The trench gate structure 31 includes a gate dielectric layer 31a and a gate conductive layer 31b, which are formed in sequence. The gate dielectric layer 31a covers the inner wall of the trench 30, and the gate conductive layer 31b covers the surface of the gate dielectric layer 31a and fills the trench 30. P-type body regions 15 are located in the silicon carbide epitaxial layer 12 and are provided on both sides of the trench gate structure 31. The P-type body regions 15 contact the outer walls of the trench 30, and the thickness of the P-type body regions 15 is less than the depth of the trench 30. In other words, the trench gate structure 31 extends vertically from the surface of the silicon carbide epitaxial layer 12 through the P-type body region 15 and into the N-drift layer 16. Each P-type body region 15 is provided with an N+ source region 23 and a P+ body contact region 26. The N+ source region 23 contacts the P+ body contact region 26, which in turn contacts the outer wall of the trench 30. The P+ body contact region 26 is disposed away from the trench 30 and extends into the P-type body region 15 to connect with the P-type body region 15. The portion of the P-type body region 15 extending downward from the N+ source region 23 and along the outer wall of the trench 30 may constitute the channel 15a, and the portion of the N-drift layer 16 surrounding the outer wall of the trench 30 may constitute the JFET region 21.

[0057] The high resistance region 25 is located below the P-type body region 15 and is provided in the JFET region 21 at the bottom of the trench 30. The high resistance region 25 is in contact with the bottom (bottom wall) or the sidewall of the bottom of the trench 30. The top of the high resistance region 25 may have a second predetermined spacing distance D2 from the bottom of the P-type body region 15. In other words, the high resistance region 25 covers the outer portion of the trench 30 extending from the P-type body region 15 (i.e., a portion of the gate dielectric layer 31a). In some examples, please continue to refer to Figure 3The high resistance region 25 is located at the bottom of the trench 30, i.e., the second predetermined spacing distance is the length of the trench 30 extending beyond the P-type body region 15. The center of the high resistance region 25 is aligned or substantially aligned with the center of the trench 30. The width of the high resistance region 25 is less than or equal to the width of the trench 30 (i.e., the high resistance region 25 does not cover the bottom sidewalls of the trench 30). The width of the high resistance region 25 may, for example, be 0.5 to 1 times the width of the trench 30. In other examples, the width of the high resistance region 25 is greater than the width of the trench 30, e.g., 1 to 1.2 times the width of the trench 30. The high resistance region 25 also extends toward the P-type body region 15 and covers a portion of the bottom sidewalls of the trench 30. The second predetermined spacing distance may, for example, be 0.5 to 1 times the length of the trench 30 extending beyond the P-type body region 15. The thickness of the high resistance region 25 can be set based on its doping concentration and in combination with the on-resistance and breakdown voltage of the power device. In some examples, the doping concentration of the high resistance region 25 may be 10 16 ~10 20 / cm 3 In addition, in some other embodiments, it is also feasible that the top of the high resistance region 25 does not contact the outer wall of the gate dielectric layer 31 a (ie, the outside of the trench 30 ).

[0058] It should be noted that the high-resistance region is doped with deep-level dopants compatible with silicon carbide. These deep-level dopants may include any one or more of vanadium, iron, oxygen, and magnesium ions. This high-resistance region, located in the JFET region beneath the gate structure, has a higher resistance than the JFET region and can push the electric field from the lower surface (bottom) of the gate structure toward the N-drift region, effectively preventing excessive electric field strength at the lower surface of the gate structure and thereby improving the reliability of the silicon carbide power device. On the other hand, the high resistance region is doped with corresponding deep energy level dopants. The deep energy level dopants in the high resistance region can serve as recombination centers (or traps) for non-radiative recombination carriers. Its high resistance performance is intrinsic, rather than relying on the outside to form a PN structure. Therefore, the high resistance region can exert a smaller influence on the surrounding area (such as the JFET region or the N-drift layer), that is, the high resistance region has a smaller influence on the current path around the high resistance region (it does not occupy the current path of the JFET region, so as not to affect the current conduction capability), thereby minimizing or avoiding the impact on the on-resistance of the power device while improving the reliability of the power device (including improving the withstand voltage).

[0059] Figure 4 This is a schematic cross-sectional view of a trench gate IGBT device provided in an embodiment of the present application.

[0060] like Figure 4As shown, the silicon carbide power device provided in the embodiment of the present application can be a trench gate IGBT device, which is provided on a substrate 10. The substrate 10 includes a front surface and a back surface relative to each other. The trench gate IGBT device provided in the present application includes a back metal layer 33, a P+ collector region 32, an N+ field stop layer (not shown), an N-drift region 16, a P-type body region 15, a JFET region 21, a high resistance region 25, a trench gate structure 31, a front metal layer, and a passivation layer, which are arranged in sequence along the direction away from the back surface of the substrate 10. Among them, the collector metal layer is located on the back surface of the substrate 10. The material of the substrate 10 can be a semiconductor substrate material such as silicon carbide and silicon. The substrate 10 can also be a thinned semiconductor substrate. The P+ collector region 32 and the N+ field stop layer can be located within the thinned substrate.

[0061] For some examples, please refer to Figure 4 The front surface of the substrate 10 may be provided with a buffer layer 11 and a silicon carbide epitaxial layer 12 in sequence. The aforementioned N-drift layer 16, P-type body region 15, JFET region 21, high resistance region 25, and trench gate structure 31 are all provided in the silicon carbide epitaxial layer 12. The front metal layer and passivation layer are both located on the surface of the silicon carbide epitaxial layer 12. The doping type and doping concentration of the silicon carbide epitaxial layer 12 are the same as those of the N-drift layer 16. In other words, the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 that is close to the substrate 10, or the N-drift layer 16 may be the portion of the silicon carbide epitaxial layer 12 excluding the P-type body region 15, the JFET region 21, and the trench gate structure 31. A trench 30 is provided in the silicon carbide epitaxial layer 12 on the side away from the substrate 10. A trench gate structure 31 is provided in the trench 30. The trench gate structure 31 includes a gate dielectric layer 31a and a gate conductive layer 31b, which are formed in sequence. The gate dielectric layer 31a covers the inner wall of the trench 30, and the gate conductive layer 31b covers the surface of the gate dielectric layer 31a and fills the trench 30. A P-type body region 15 is located on the surface of the silicon carbide epitaxial layer 12 and is provided on both sides of the trench gate structure 31. The P-type body region 15 contacts the outer wall of the trench 30, and the thickness of the P-type body region 15 is less than the depth of the trench 30. In other words, the trench gate structure 31 extends vertically from the surface of the silicon carbide epitaxial layer 12 through the P-type body region 15 and into the N-drift layer 16. Each P-type body region 15 is provided with an N+ source region 23 and a P+ body contact region 26. The N+ source region 23 contacts the P+ body contact region 26, which in turn contacts the outer wall of the trench 30. The P+ body contact region 26 is disposed away from the trench 30 and extends into the P-type body region 15 to connect with the P-type body region 15. The portion of the P-type body region 15 extending downward from the N+ source region 23 and along the outer wall of the trench 30 may constitute the channel 15a, and the portion of the N-drift layer 16 surrounding the outer wall of the trench 30 may constitute the JFET region 21.

[0062] The high resistance region 25 is located below the P-type body region 15 and is provided in the JFET region 21 at the bottom of the trench 30. The high resistance region 25 is in contact with the bottom (bottom wall) or the sidewall of the bottom of the trench 30. The top of the high resistance region 25 may have a second predetermined spacing distance D2 from the bottom of the P-type body region 15. In other words, the high resistance region 25 covers the outer portion of the trench 30 extending from the P-type body region 15 (i.e., a portion of the gate dielectric layer 31a). In some examples, please continue to refer to Figure 3 The high resistance region 25 is located at the bottom of the trench 30, i.e., the second predetermined spacing distance is the length of the trench 30 extending beyond the P-type body region 15. The center of the high resistance region 25 is aligned or substantially aligned with the center of the trench 30. The width of the high resistance region 25 is less than or equal to the width of the trench 30 (i.e., the high resistance region 25 does not cover the bottom sidewalls of the trench 30). The width of the high resistance region 25 may, for example, be 0.5 to 1 times the width of the trench 30. In other examples, the width of the high resistance region 25 is greater than or less than the width of the trench 30. The width of the high resistance region 25 may, for example, be 0.1 to 2 times the width of the trench 30. The high resistance region 25 also extends toward the P-type body region 15 and covers a portion of the bottom sidewalls of the trench 30. The second predetermined spacing distance may, for example, be 0.5 to 1 times the length of the trench 30 extending beyond the P-type body region 15. The thickness of the high resistance region 25 can be determined based on its doping concentration and in combination with the on-resistance and breakdown voltage of the power device. In some examples, the doping concentration of the high resistance region 25 may be 10 16 ~10 20 / cm 3 In addition, in some other embodiments, it is also feasible that the top of the high resistance region 25 does not contact the outer wall of the gate dielectric layer 31 a (ie, the outside of the trench 30 ).

[0063] It should be noted that the high-resistance region is doped with deep-level dopants compatible with silicon carbide. These deep-level dopants may include any one or more of vanadium, iron, oxygen, and magnesium ions. This high-resistance region, located in the JFET region beneath the gate structure, has a higher resistance than the JFET region and can push the electric field from the lower surface (bottom) of the gate structure toward the N-drift region, effectively preventing excessive electric field strength at the lower surface of the gate structure and thereby improving the reliability of the silicon carbide power device. On the other hand, the high resistance region is doped with corresponding deep energy level dopants. The deep energy level dopants in the high resistance region can serve as recombination centers (or traps) for non-radiative recombination carriers. Its high resistance performance is intrinsic, rather than relying on the outside to form a PN structure. Therefore, the high resistance region can exert a smaller influence on the surrounding area (such as the JFET region or the N-drift layer), that is, the high resistance region has a smaller influence on the current path around the high resistance region (it does not occupy the current path of the JFET region, so as not to affect the current conduction capability), thereby minimizing or avoiding the impact on the on-resistance of the power device while improving the reliability of the power device (including improving the withstand voltage).

[0064] An embodiment of the present application provides a silicon carbide power device.

[0065] The silicon carbide power device provided in the embodiment of the present application includes a substrate (eg Figures 1 to 4 The substrate 10 in the silicon carbide epitaxial layer, the gate structure, the JFET region and the high resistance region. The silicon carbide epitaxial layer is provided on the surface of the substrate. The gate structure is provided on the silicon carbide epitaxial layer (for example Figure 1 、 Figure 3 The planar gate structure 27, the silicon carbide epitaxial layer 12) or the ... Figure 2 、 Figure 4 The trench gate structure 31 and the silicon carbide epitaxial layer 12 in the JFET region (e.g. Figures 1 to 4 The JFET region 21 in the silicon carbide epitaxial layer is provided. Figures 1 to 4 The high resistance region 25) is provided in the JFET region and is located below the gate structure. The high resistance region is doped with a deep energy level dopant that matches silicon carbide.

[0066] In some embodiments, the deep level dopant includes any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions.

[0067] In some embodiments, the doping concentration of the high resistance region is 10 16 ~10 20 / cm 3 .

[0068] In some embodiments, the silicon carbide power device is a planar gate power device, and the high resistance region is located adjacent to the P-type body region (for example, including Figure 1 、 Figure 3 In the JFET region between the P-type body regions 15 in the JFET region, the high resistance region and the P-type body regions on both sides have a first preset spacing distance.

[0069] In some embodiments, the width of the high resistance region is less than or equal to 80% of the width of the JFET region.

[0070] In some embodiments, the thickness of the high resistance region is 0.5 to 2 times the thickness of the P-type body region.

[0071] In some embodiments, the planar gate power device is a planar IGBT device or a planar MOS device.

[0072] In some embodiments, the silicon carbide power device is a trench gate power device, the high resistance region is located below the P-type body region and has a second preset spacing distance from the P-type body region, and the high resistance region is spaced from the trench gate (for example Figure 2 、 Figure 4 The bottom of the trench gate structure 31 is in contact with each other.

[0073] In some embodiments, the width of the high resistance region is 0.1 to 2 times the width of the trench gate.

[0074] In some embodiments, the trench gate power device is a trench IGBT device or a trench MOS device.

[0075] The embodiments of the present application also provide a method for preparing a silicon carbide power device.

[0076] Figure 5 Flowchart of a method for preparing a silicon carbide power device provided in an embodiment of the present application.

[0077] like Figure 5 As shown, the method for preparing a silicon carbide power device provided in this application includes:

[0078] S01: providing a substrate, and forming a silicon carbide epitaxial layer on a surface of the substrate;

[0079] S02: forming a JFET region in the silicon carbide epitaxial layer;

[0080] S03: forming a high resistance region and a gate structure, wherein the gate structure is arranged on the surface of the silicon carbide epitaxial layer or in the silicon carbide epitaxial layer, the high resistance region is arranged in the JFET region and is located below the gate structure, and the high resistance region is doped with a deep energy level dopant matching silicon carbide.

[0081] Figures 6A to 6H The structural diagram corresponding to the corresponding steps of the method for preparing the silicon carbide power device provided in this embodiment is shown below. Figures 6A to 6H The preparation method of the silicon carbide power device is described in detail.

[0082] First, execute step S01, please refer to Figure 6A , providing a substrate 10, and forming a silicon carbide epitaxial layer 12 on the surface of the substrate 10.

[0083] The material of the substrate 10 can be any suitable base material for epitaxially growing silicon carbide, such as silicon, sapphire, or silicon carbide. In some examples, before forming the silicon carbide epitaxial layer 12 on the surface (front side) of the substrate 10, a buffer layer 11 can be formed. The buffer layer 11 can be, for example, a low-doped or intrinsic silicon carbide layer. In another example, when the silicon carbide epitaxial layer 12 is formed by epitaxial growth, it can also be in-situ doped to a first conductivity type. The first conductivity type can be the same as the doping type of the N-drift layer 16 (i.e., the first conductivity type is N-type). Moreover, the concentration of the in-situ doping during epitaxial growth can be the same as the doping concentration of the N-drift layer 16. In other words, an N-drift layer 16 is also formed in the silicon carbide epitaxial layer 12.

[0084] Next, step S02 is performed to form a JFET region 21 in the silicon carbide epitaxial layer 12 .

[0085] Please refer to Figure 6B A first patterned mask 13 is formed on the silicon carbide epitaxial layer 12, and ion implantation of the second conductivity type is performed to form a P-type body region 15 in the silicon carbide epitaxial layer 12, with the N-drift layer 16 (silicon carbide epitaxial layer 12) between adjacent P-type body regions 15 serving as a JFET region 21. Furthermore, before forming the first patterned mask 13, an ion implantation protection layer 14 may be formed to cover the surface of the silicon carbide epitaxial layer 12 to protect the surface of the silicon carbide epitaxial layer 12 during subsequent ion implantation.

[0086] The second conductive type ion implantation may be P-type ion implantation, and the material of the ion implantation protection layer 14 may include any one of silicon, silicon nitride, silicon oxide, silicon oxynitride or aluminum nitride, or a composite film layer composed of any of several.

[0087] Please refer to Figure 6C A spacer structure 22 is formed on the sidewalls of the first patterned mask 13, and ion implantation of the first conductivity type is performed to form an N+ source region 23 in the P-type body region 15. The first conductivity type ion implantation may be an N-type conductivity type ion implantation, and the thickness of the N+ source region 23 (i.e., the depth of the ion implantation) may be less than the thickness of the P-type body region 15. The spacer structure 22 covers the sidewalls of the first patterned mask 13, and the width of the spacer structure 22 may be determined based on the length of the subsequent channel and the effect of double diffusion.

[0088] Next, step S03 is performed to form a high resistance region 25 and a gate structure. The gate structure is arranged on the surface of the silicon carbide epitaxial layer 12 or in the silicon carbide epitaxial layer 12. The high resistance region 25 is arranged in the JFET region 21 and contacts the gate structure. The high resistance region 25 is doped with deep energy level dopants that match silicon carbide.

[0089] Please refer to Figure 6DThe first patterned mask 13 and the sidewall structure 22 are removed, and a second patterned mask 24 is formed on the silicon carbide epitaxial layer 12. The opening of the second patterned mask 24 is located directly above the JFET region 21, and the width of the opening of the second patterned mask 24 is less than the width of the JFET region 21. The second patterned mask 24 can be located on the ion implantation protection layer 14. The center of the opening of the second patterned mask 24 can be aligned or substantially aligned with the center of the JFET region 21. The edges of the openings of the second patterned mask 24 are the same or substantially the same distance from their respective corresponding P-type body regions 15. In other words, the edges of the openings of the second patterned mask 24 are the same or substantially the same distance from their respective corresponding P-type body regions 15. In some examples, the width of the opening of the second patterned mask 24 can be less than or equal to 80% of the width of the JFET region 21.

[0090] Please refer to Figure 6E Using the second patterned mask 24 , ion implantation including deep level dopants is performed to form a high resistance region 25 in the JFET region 21 .

[0091] The deep level dopant may include any one or more of vanadium ions, iron ions, oxygen ions, and magnesium ions. The doping concentration (i.e., doping dosage) of the deep level dopant is set according to the on-resistance and breakdown voltage required by the power device. In some examples, the doping dosage of the deep level dopant may be 10 11 ~10 15 / cm 2 The doping concentration of the high resistance region 25 can be 10 16 ~10 20 / cm 3 The depth of the ion implantation can be set based on the doping concentration of the high-resistance region 25 and the on-resistance and breakdown voltage of the power device. For example, the depth can be 0.5 to 2 times the thickness of the P-type body region 15 (i.e., the thickness of the JFET region 21). In other words, it is also feasible for the high-resistance region 25 to extend into the N-drift layer 16 below the P-type body region 15.

[0092] In such Figure 6E In the example, the top of the high resistance region 25 is located on the surface of the JFET region 21, while in other examples, the top of the high resistance region 25 may also be located below the surface of the JFET region 21, that is, the high resistance region 25 does not contact the subsequent gate structure.

[0093] Please refer to Figure 6F , remove the second patterned mask 24 and the ion implantation protection layer 14 , and form a P+ contact region in the N+ source region 23 .

[0094] The step of forming the P+ contact region may, for example, include: forming a third patterned mask on the surface of the silicon carbide epitaxial layer 12, the opening of the third patterned mask exposing a portion of the surface of the P-type body region 15 and the surface of the N+ source region 23 away from the JFET region 21, performing heavy P-type doping to connect the P-type body region 15 and the N+ source region 23 when forming the P+ contact region. In addition, a current spreading layer (not shown) and a protective layer and other junction ion doping regions may be formed on the surface of the silicon carbide epitaxial layer 12, and then after removing the mask layer on the surface of the silicon carbide epitaxial layer 12, an annealing protective layer (e.g., a carbon layer) is formed to cover the surface of the silicon carbide epitaxial layer 12, and an annealing process is performed to activate the above-mentioned doping ions at a high temperature.

[0095] Please refer to Figure 6G , a gate structure, a passivation layer and a front metal layer are formed on the surface of the silicon carbide epitaxial layer 12.

[0096] The gate structure may be, for example, a planar gate structure 27, covering the JFET region 21 (including the high-resistance layer therein) and the surface of the silicon carbide epitaxial layer 12 of the channel on both sides thereof, and may extend to cover a portion of the surface of the silicon carbide epitaxial layer 12 of the N+ source region 23. The gate structure may include a gate dielectric layer 27a and a gate conductive layer 27b, which are formed in sequence. The gate dielectric layer 27a covers the surface of the silicon carbide epitaxial layer 12, and the gate conductive layer 27b covers the surface of the gate dielectric layer 27a. Subsequently, a first passivation layer (not shown) is formed to cover the gate structure and the surface of the silicon carbide epitaxial layer 12, and contact holes are formed in the first passivation layer to expose the area to be connected (the structure to be connected). Subsequently, contact plugs, interconnects, and pads are formed, and this serves as a front metal layer. Subsequently, a second passivation layer (not shown) may be formed to cover the first passivation layer and the interconnects, and to expose the pads. The first and second passivation layers serve as passivation layers. The materials of the first and second passivation layers may include oxide layers and / or nitride layers.

[0097] Please refer to Figure 6H , a thinning process is performed on the back side of the substrate 10 , and an N+ drain region 28 and a back metal layer 33 are formed on the back side of the substrate 10 .

[0098] In summary, the present invention provides a silicon carbide power device and a preparation method thereof, wherein the silicon carbide power device includes a substrate, a silicon carbide epitaxial layer, a gate structure, a JFET region and a high resistance region. The silicon carbide epitaxial layer is provided on the surface of the substrate. The gate structure is provided on the surface of the silicon carbide epitaxial layer or in the silicon carbide epitaxial layer. The JFET region is provided in the silicon carbide epitaxial layer. The high resistance region is provided in the JFET region and is located below the gate structure, and the high resistance region is doped with a deep energy level dopant that matches silicon carbide. In the present application, the high resistance region is located in the JFET region under the gate structure, has a higher resistance than the JFET region, can push the electric field on the lower surface of the gate structure to the N-drift region, can effectively curb the excessive electric field strength on the lower surface of the gate structure, thereby improving the reliability of the silicon carbide power device. More importantly, the high-resistance region is doped with corresponding deep-level dopants. The deep-level dopants in the high-resistance region can serve as recombination centers (or traps) for non-radiative recombination carriers, and its high-resistance performance is intrinsic, rather than relying on the outside to form a PN structure. Therefore, the high-resistance region can exert a smaller impact on the surrounding area (such as the JFET region or the N-drift layer), that is, the high-resistance region has a smaller impact on the current path around the high-resistance region (it does not occupy the current path of the JFET region, so as not to affect the current conduction capability), thereby minimizing or avoiding the impact on the on-resistance of the power device while improving the reliability of the power device (including improving the withstand voltage).

[0099] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A silicon carbide power device, characterized in that: include: substrate; a silicon carbide epitaxial layer, disposed on the surface of the substrate; a gate structure, disposed on the surface of the silicon carbide epitaxial layer or in the silicon carbide epitaxial layer; A JFET region is provided in the silicon carbide epitaxial layer; A high resistance region is provided in the JFET region and is located below the gate structure. The high resistance region is doped with a deep energy level dopant that matches silicon carbide.

2. The silicon carbide power device according to claim 1, characterized in that The deep level dopant includes any one or more of vanadium ions, iron ions, oxygen ions and magnesium ions.

3. The silicon carbide power device according to claim 1, characterized in that: The doping concentration of the high resistance region is 10 16 ~10 20 / cm 3 .

4. The silicon carbide power device according to claim 1, characterized in that The silicon carbide power device is a planar gate power device, which includes a P-type body region, a source region and a planar gate structure. The P-type body region is arranged in the silicon carbide epitaxial layer, the source region is arranged in the P-type body region, the JFET region is located between two adjacent P-type body regions, the planar gate structure is located on the JFET region, and the high resistance region is located in the JFET region under the planar gate structure. The high resistance region has a first preset spacing distance from the P-type body regions on both sides.

5. The silicon carbide power device according to claim 4, characterized in that: The width of the high resistance region is less than or equal to 80% of the width of the JFET region.

6. The silicon carbide power device according to claim 4, characterized in that: The thickness of the high resistance region is 0.5 to 2 times the thickness of the P-type body region.

7. The silicon carbide power device according to any one of claims 4 to 6, characterized in that: The planar gate power device is a planar IGBT device or a planar MOS device.

8. The silicon carbide power device according to claim 1, characterized in that: The silicon carbide power device is a trench gate power device, which includes a P-type body region, a source region and a trench gate structure. The P-type body region is arranged in the silicon carbide epitaxial layer, and the trench gate structure penetrates the P-type body region. The source region is arranged in the P-type body region and contacts the outer wall of the trench gate structure. The JFET region is the region in the silicon carbide epitaxial layer surrounding the portion of the P-type body region extending out of the trench gate structure. The high resistance region is located in the JFET region at the bottom of the trench gate structure and its surroundings, and the high resistance region has a second preset spacing distance from the P-type body region.

9. The silicon carbide power device according to claim 8, characterized in that: The width of the high resistance region is 0.1 to 2 times the width of the trench gate.

10. The silicon carbide power device according to claim 8 or 9, characterized in that: The trench gate power device is a trench IGBT device or a trench MOS device.

11. A method for preparing a silicon carbide power device, characterized in that: include: providing a substrate, and forming a silicon carbide epitaxial layer on a surface of the substrate; forming a JFET region in the silicon carbide epitaxial layer; A high resistance region and a gate structure are formed, wherein the gate structure is arranged on or in the silicon carbide epitaxial layer, the high resistance region is arranged in the JFET region and is located below the gate structure, and the high resistance region is doped with a deep energy level dopant that matches silicon carbide.

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