Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display, in the display panel, an oxide thin film transistor comprises a first oxide layer located on one side of a substrate and a second oxide layer located on the side, away from the substrate, of the first oxide layer, and the two oxide layers are connected between a source electrode and a drain electrode in parallel; the double-layer conductive channel which is longitudinally stacked and connected in parallel is formed, so that the electron mobility of the whole conductive channel of the oxide thin film transistor is improved, the output current of the device is further improved, and the layout area is not increased; moreover, the first oxide layer and the second oxide layer each comprise an oxygen element, a narrow forbidden band element and a wide forbidden band element, and the mole fraction of the narrow forbidden band element in the first oxide layer is set to be larger than that of the narrow forbidden band element in the second oxide layer, so that the electron mobility of the first oxide layer is further improved; therefore, the output current of the device is further improved, and the first oxide layer and the second oxide layer are not easy to be converted into conductors.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The semiconductor materials of thin-film transistors (TFTs) are mainly divided into three categories: amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS) and metal oxides (such as indium gallium zinc oxide (IGZO)). Among them, the electron mobility of metal oxides (such as IGZO) is between amorphous silicon (a-Si) and low-temperature polycrystalline silicon (LTPS), and is significantly better than amorphous silicon (a-Si). In addition, the leakage current of metal oxide (such as IGZO) thin-film transistors (referred to as oxide thin-film transistors) is extremely small, and the energy efficiency advantage is obvious when driven at low frequencies. The power consumption is lower than that of low-temperature polycrystalline silicon (LTPS) thin-film transistors. Therefore, oxide (such as IGZO) thin-film transistors have great potential.

[0003] Currently, most oxide thin-film transistors used in display panels have a single oxide layer. While these transistors offer excellent leakage current, saturation characteristics, and hysteresis performance, they still have insufficient electron mobility, resulting in low device output current. Simply increasing the channel width of an oxide thin-film transistor can increase device output current, but this increases the footprint of the oxide thin-film transistor. Summary of the Invention

[0004] To solve the above technical problems, the present application provides a display panel and a display device to improve the vertical structure of the oxide thin film transistor to increase the device output current and avoid affecting the layout area of ​​the oxide thin film transistor.

[0005] To achieve the above objectives, this application provides the following technical solutions:

[0006] In a first aspect of the present application, a display panel is provided, comprising:

[0007] substrate;

[0008] An oxide thin-film transistor located on one side of the substrate, the oxide thin-film transistor comprising a first oxide layer and a second oxide layer located on a side of the first oxide layer facing away from the substrate, the oxide thin-film transistor comprising a source electrode and a drain electrode, the source electrode being electrically connected to the drain electrode through the first oxide layer, and the source electrode being further electrically connected to the drain electrode through the second oxide layer;

[0009] The first oxide layer and the second oxide layer both include oxygen, narrow bandgap elements and wide bandgap elements. The molar fraction of the narrow bandgap elements in the first oxide layer is greater than the molar fraction of the narrow bandgap elements in the second oxide layer.

[0010] In a second aspect of the present application, a display device is provided, comprising the above-mentioned display panel.

[0011] Compared with the existing technology, the above technical solution has the following advantages:

[0012] Compared with the existing display panel, the oxide thin film transistor with a single oxide layer has a single conductive channel. In the display panel provided by the present application, the oxide thin film transistor includes a first oxide layer located on one side of the substrate and a second oxide layer located on the side of the first oxide layer away from the substrate. The two oxide layers are connected in parallel between the source electrode and the drain electrode to form a double-layer conductive channel stacked and parallel in the vertical direction, thereby improving the electron mobility of the overall conductive channel of the oxide thin film transistor and thus increasing the output current of the device; at the same time, because the two oxide layers constituting the double-layer conductive channel are stacked in the vertical direction, the layout area of ​​the oxide thin film transistor will not be increased, and thus the area of ​​the module including the oxide thin film transistor, such as the pixel circuit, will not be affected.

[0013] Among them, the first oxide layer and the second oxide layer both include oxygen, narrow bandgap elements and wide bandgap elements. By increasing the molar fraction of the narrow bandgap elements in the first oxide layer and the second oxide layer, the electron mobility of the first oxide layer and the second oxide layer can be increased respectively; but considering the actual preparation process, since the second oxide layer is located on the side of the first oxide layer away from the substrate, the second oxide layer is less stable than the first oxide layer. If the molar fraction of the narrow bandgap elements in the second oxide layer is increased, the second oxide layer will be easily conductive, causing a short circuit between the source electrode and the drain electrode; and the first oxide layer is more stable than the second oxide layer. Therefore, the molar fraction of the narrow bandgap element in the first oxide layer can be set to be greater than the molar fraction of the narrow bandgap element in the second oxide layer, so that the electron mobility of the first oxide layer is improved relatively more, and the first oxide layer is not easily conductive, while the electron mobility of the second oxide layer is improved relatively less, and the second oxide layer is also not easily conductive. In this way, the electron mobility of the overall conductive channel of the oxide thin film transistor can be further improved, and the conductive channel where the first oxide layer is located has a larger current than the conductive channel where the second oxide layer is located, and then the output current of the device as a whole is further improved due to the parallel connection of the first oxide layer and the second oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 A schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application;

[0016] Figure 2 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0017] Figure 3 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0018] Figure 4 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0019] Figure 5 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0020] Figure 6 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0021] Figure 7 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0022] Figure 8 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0023] Figure 9 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0024] Figure 10 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0025] Figure 11 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0026] Figure 12 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0027] Figure 13a is a schematic top view of an oxide semiconductor layer;

[0028] Figure 13b Schematic top view of an oxide semiconductor layer with gate electrodes disposed on both the side close to the substrate and the side away from the substrate;

[0029] Figure 14A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0030] Figure 15 A schematic top view of a display panel provided in an embodiment of the present application;

[0031] Figure 16 A schematic diagram of the circuit structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0032] Figure 17 To provide Figure 16 A timing diagram of various signals of the pixel circuit shown;

[0033] Figure 18 1 is a schematic diagram of an equivalent circuit of an oxide thin film transistor when the oxide thin film transistor includes a common gate electrode, and the common gate electrode is located between the first oxide layer and the second oxide layer;

[0034] Figure 19 A schematic diagram of an equivalent circuit of an oxide thin film transistor when the oxide thin film transistor includes a common gate electrode and a first gate electrode, the common gate electrode is located between the first oxide layer and the second oxide layer, and the first gate electrode is located on a side of the first oxide layer close to the substrate;

[0035] Figure 20 A schematic diagram of an equivalent circuit of an oxide thin film transistor when the oxide thin film transistor includes a common gate electrode and a second gate electrode, the common gate electrode is located between the first oxide layer and the second oxide layer, and the second gate electrode is located on a side of the second oxide layer away from the substrate;

[0036] Figure 21 A schematic diagram of an equivalent circuit of an oxide thin-film transistor when the oxide thin-film transistor includes a common gate electrode, a first gate electrode, and a second gate electrode, and the common gate electrode is located between the first oxide layer and the second oxide layer, the first gate electrode is located on a side of the first oxide layer close to the substrate, and the second gate electrode is located on a side of the second oxide layer away from the substrate;

[0037] Figure 22 A schematic diagram of an equivalent circuit of an oxide thin film transistor when the oxide thin film transistor includes a first gate electrode and a second gate electrode, wherein the first gate electrode is located on a side of the first oxide layer close to the substrate, and the second gate electrode is located on a side of the second oxide layer away from the substrate;

[0038] Figure 23 Another schematic top view of the display panel provided in an embodiment of the present application;

[0039] Figure 24A schematic diagram of the circuit structure of a shift register circuit in a scan driving module of a display panel provided in an embodiment of the present application;

[0040] Figure 25 A schematic diagram of the circuit structure of a shift register circuit in a light-emitting control driving module of a display panel provided in an embodiment of the present application;

[0041] Figure 26 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0042] Figure 27 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0043] Figure 28 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0044] Figure 29 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0045] Figure 30 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0046] Figure 31 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0047] Figure 32 This is another schematic top view of the display panel provided in the embodiment of the present application;

[0048] Figure 33 This is another schematic top view of the display panel provided in an embodiment of the present application;

[0049] Figure 34 A schematic top view of a display device provided in an embodiment of the present application.

[0050] Reference numerals:

[0051] 10-substrate; 20-oxide thin film transistor; O10-first oxide layer; O20-second oxide layer; S1-source electrode; D1-drain electrode; G10-gate electrode corresponding to the first oxide layer; G20-gate electrode corresponding to the second oxide layer; I10-gate insulating layer between the first oxide layer and the corresponding gate electrode; I20-gate insulating layer between the second oxide layer and the corresponding gate electrode; O11-channel portion of the first oxide layer; O12-conductor portion of the first oxide layer; O21-channel portion of the second oxide layer; O22-conductor portion of the second oxide layer; G0-common gate electrode; G1-first gate electrode; G2-second gate electrode; 201-oxide semiconductor layer; 202-gate electrode corresponding to the oxide semiconductor layer; 203-gate insulating layer between the oxide semiconductor layer and the corresponding gate electrode; 204-channel portion of the oxide semiconductor layer; 205-conductor portion of the oxide semiconductor layer; Z1-first sublayer; Z2-second sublayer; I11-first gate insulating layer; I12-second gate insulating layer; I21-third gate insulating layer; I22-fourth gate insulating layer; pixel-pixel circuit; 30-light-emitting element; T1-first light-emitting control transistor; T2-data writing transistor; T3-driving transistor; T4-compensation transistor; T 5 - gate reset transistor; T6 - second light-emitting control transistor; T7 - ​​anode reset transistor; Cst - storage capacitor; SN1, SN2, SP - scan lines; Em - light-emitting control line; data - data line; PVDD - first power supply voltage line; PVEE - second power supply voltage line; H1 - IC signal line; H2 - drive control signal line; N1 - first node; N2 - second node; N3 - third node; N4 - fourth node; VSN1, VSN2, VSP - scan signals; VEm - light-emitting control signal; P1 - data write frame; P2 - hold frame; T201, T202 - sub-oxide thin film transistors; VSR - drive Circuit; ScanA-first scanning drive module; ScanB-second scanning drive module; Emit-light emitting control drive module; IC-driver integrated circuit; 41, 42-shift register circuit; M17, M29-first output transistor; M18, M210-second output transistor; 31-first light-emitting element; 32-second light-emitting element; 33-third light-emitting element; 51-first sub-pixel; 52-second sub-pixel; 53-third sub-pixel; 100-display panel; 200-display device; AA-display area; AA1-first display area; AA2-second display area; NA-non-display area; BA-bending area; PA-pin area. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0054] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of illustration, the drawings depicting device structures may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, the three-dimensional dimensions of length, width, and depth should be included.

[0055] As mentioned in the background section, most oxide thin-film transistors currently used in display panels have a single oxide layer. While these transistors offer excellent leakage current, saturation characteristics, and hysteresis performance, they still suffer from insufficient electron mobility, resulting in low device output current. Simply increasing the channel width of an oxide thin-film transistor can increase device output current, but this also increases the footprint of the oxide thin-film transistor.

[0056] In view of this, an embodiment of the present application provides a display panel, Figure 1 FIG. 1 shows a partial cross-sectional structural diagram of a display panel provided in an embodiment of the present application. Figure 1As shown, the display panel includes a substrate 10 and an oxide thin film transistor 20 located on one side of the substrate 10. The oxide thin film transistor 20 includes a first oxide layer O10 and a second oxide layer O20 located on the side of the first oxide layer O10 facing away from the substrate 10. The oxide thin film transistor 20 also includes a source electrode S1 and a drain electrode D1. The source electrode S1 is electrically connected to the drain electrode D1 through the first oxide layer O10, and the source electrode S1 is also electrically connected to the drain electrode D1 through the second oxide layer O20. That is, the first oxide layer O10 and the second oxide layer O20 are connected in parallel between the source electrode S1 and the drain electrode D1, forming a double-layer conductive channel that is stacked and connected in parallel in the vertical direction.

[0057] Compared with the existing display panel, the oxide thin film transistor with a single oxide layer has a single conductive channel. In the display panel provided by the embodiment of the present application, the oxide thin film transistor 20 has a double conductive channel stacked and connected in parallel in the vertical direction. Therefore, the electron mobility of the overall conductive channel of the oxide thin film transistor 20 can be improved, thereby increasing the output current of the device. At the same time, because the two oxide layers constituting the double conductive channel are stacked in the vertical direction, the layout area of ​​the oxide thin film transistor 20 will not be increased, and thus the area of ​​the module including the oxide thin film transistor 20, such as the pixel circuit, will not be affected.

[0058] Furthermore, considering that both the first oxide layer O10 and the second oxide layer O20 include oxygen, narrow bandgap elements, and wide bandgap elements, the electron mobility of the overall conductive channel of the oxide thin film transistor 20 is affected not only by the number of oxide layers, but also by the electron mobility of each oxide layer. If the number of oxide layers is further increased, for example, the oxide thin film transistor 20 includes three oxide layers, the thickness of the display panel will increase and the difficulty of process preparation will increase. Therefore, on the basis that the oxide thin film transistor 20 includes two oxide layers, the first oxide layer O10 and the second oxide layer O20, a more feasible approach is to increase the electron mobility of each oxide layer as much as possible, thereby further increasing the output current of the device.

[0059] The inventors have discovered that for an oxide layer including oxygen, a narrow bandgap element, and a wide bandgap element, the electron mobility of the oxide layer can be improved by increasing the molar fraction of the narrow bandgap element. That is, the electron mobility of the first oxide layer O10 can be improved by increasing the molar fraction of the narrow bandgap element in the first oxide layer O10. Similarly, the electron mobility of the second oxide layer O20 can be improved by increasing the molar fraction of the narrow bandgap element in the second oxide layer O20.

[0060] However, in actual fabrication processes, since the second oxide layer O20 is located on the side of the first oxide layer O10 facing away from the substrate 10, the second oxide layer O20 is less stable than the first oxide layer O10. If the mole fraction of the narrow bandgap element in the second oxide layer O20 is significantly increased, the second oxide layer O20 will be easily converted into a conductor, causing a short circuit between the source electrode S1 and the drain electrode D2. However, the first oxide layer O10 is located on the side of the second oxide layer O10 closer to the substrate 10 and is more stable than the second oxide layer O20. Therefore, the mole fraction of the narrow bandgap element in the first oxide layer O10 can be relatively increased, making the first oxide layer O10 relatively less susceptible to conversion into a conductor.

[0061] That is to say, when increasing the molar fraction of the narrow bandgap element in the first oxide layer O10 to improve the electron mobility of the first oxide layer O10, and increasing the molar fraction of the narrow bandgap element in the second oxide layer O20 to improve the electron mobility of the second oxide layer O20, the molar fraction of the narrow bandgap element in the first oxide layer O10 can be set to be greater than the molar fraction of the narrow bandgap element in the second oxide layer O20, so that the electron mobility of the first oxide layer O10 is improved relatively more, and the first oxide layer O10 is not easily conductive. At the same time, the electron mobility of the second oxide layer O20 is improved relatively less, and the second oxide layer O20 is also not easily conductive. In this way, the electron mobility of the overall conductive channel of the oxide thin film transistor 20 can be further improved, and the conductive channel corresponding to the first oxide layer O10 has a larger current than the conductive channel corresponding to the second oxide layer O20. Therefore, since the first oxide layer O10 and the second oxide layer O20 are connected in parallel, the overall output current of the device is further improved.

[0062] It should be noted that the molar fraction (symbol: x) represents the ratio of the amount of the component substance to the total amount of the substance, and the value range is 0-1, that is, 0≤x≤1. In the embodiment of the present application, the molar fraction of the narrow bandgap element in the oxide layer including oxygen element, narrow bandgap element and wide bandgap element represents the ratio of the amount of the narrow bandgap element to the total amount of oxygen element, narrow bandgap element and wide bandgap element, that is, it represents the component of the narrow bandgap element.

[0063] Optionally, in some embodiments of the present application, the first oxide layer O10 and the second oxide layer O20 are both indium gallium zinc oxide layers. In the indium gallium zinc oxide layer, the indium element is a narrow bandgap element, and the gallium element and the zinc element are wide bandgap elements. Then, when the molar fraction of the indium element in the first oxide layer O10 is increased to improve the electron mobility of the first oxide layer O10, and the molar fraction of indium in the second oxide layer O20 is increased to improve the electron mobility of the second oxide layer O20, the molar fraction of indium in the first oxide layer O10 can be set to be greater than the molar fraction of indium in the second oxide layer O20. The electron mobility of the first oxide layer O10 is improved relatively more, and the first oxide layer O10 is not easily conductive. At the same time, the electron mobility of the second oxide layer O20 is improved relatively less, and the second oxide layer O20 is also not easily conductive. In this way, the electron mobility of the overall conductive channel of the oxide thin film transistor 20 can be further improved, and the conductive channel corresponding to the first oxide layer O10 has a larger current than the conductive channel corresponding to the second oxide layer O20. Therefore, since the first oxide layer O10 and the second oxide layer O20 are connected in parallel, the overall output current of the device is further improved.

[0064] It is understandable that when the molar fraction of the narrow bandgap element in the first oxide layer O10 increases to a certain extent, although the electron mobility of the first oxide layer O10 is improved, the first oxide layer O10 also becomes easily conductive. Therefore, optionally, in some embodiments of the present application, such as Figure 2 As shown, Figure 2 A schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application is shown. The thickness d1 of the first oxide layer O10 can be set to be smaller than the thickness d2 of the second oxide layer O20. In this way, although the molar fraction of the narrow bandgap elements in the first oxide layer O10 is increased to improve the electron mobility of the first oxide layer O10, the thickness d1 of the first oxide layer O10 is set to be relatively thin, thereby reducing the total mass of the narrow bandgap elements in the first oxide layer O10 and reducing the risk of the first oxide layer O10 being conductive.

[0065] It is also understandable that if Figure 1 and Figure 2 As shown, the oxide thin film transistor 20 includes a gate electrode G10 corresponding to the first oxide layer O10 and a gate electrode G20 corresponding to the second oxide layer O20. There is a gate insulating layer I10 between the first oxide layer O10 and the corresponding gate electrode G10, and there is also a gate insulating layer I20 between the second oxide layer O20 and the corresponding gate electrode.

[0066] The first oxide layer O10 includes a channel portion O11 and a conductor portion O12 located on both sides of the channel portion O11. In a direction perpendicular to the plane of the substrate 10, the channel portion O11 of the first oxide layer O10 overlaps with the corresponding gate electrode G10. The portion of the channel portion O11 of the first oxide layer O10 close to the corresponding gate electrode G10 is a channel region.

[0067] Similarly, the second oxide layer O20 includes a channel portion O21 and a conductor portion O22 located on both sides of the channel portion O21. In a direction perpendicular to the plane of the substrate 10, the channel portion O21 of the second oxide layer O20 overlaps with the corresponding gate electrode G20, and the portion of the channel portion O21 of the second oxide layer O20 close to the corresponding gate electrode G20 is a channel region.

[0068] Among them, the conductive portion O12 of the first oxide layer O10 is heavily doped compared to its channel portion O11 to be electrically connected to the source electrode S1 and the drain electrode D1; similarly, the conductive portion O22 of the second oxide layer O20 is heavily doped compared to its channel portion O21 to be electrically connected to the source electrode S1 and the drain electrode D1.

[0069] Optionally, in some embodiments of the present application, such as Figure 1 and Figure 2 As shown, the oxide thin film transistor 20 includes a common gate electrode G0, which is located between the first oxide layer O10 and the second oxide layer O20; it can be understood that the common gate electrode G0 belongs to both the gate electrode G10 corresponding to the first oxide layer O10 and the gate electrode G20 corresponding to the second oxide layer O20; at this time, the portion of the channel portion O11 of the first oxide layer O10 close to the common gate electrode G0 is a channel region, and the portion of the channel portion O21 of the second oxide layer O20 close to the common gate electrode G0 is also a channel region, and the oxide thin film transistor 20 has two channel regions.

[0070] Optionally, in other embodiments of the present application, such as Figure 3As shown, in addition to the common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, the oxide thin film transistor 20 may also include a first gate electrode G1, which is located on the side of the first oxide layer O10 close to the substrate 10; at this time, the gate G10 corresponding to the first oxide layer O10 includes the common gate electrode G0 and the first gate electrode G1, and the portion of the channel portion O11 of the first oxide layer O10 close to the common gate electrode G0 and the portion of the channel portion O11 of the first oxide layer O10 close to the first gate electrode G1 are both channel regions; the gate G20 corresponding to the second oxide layer O20 is the common gate electrode G0, and the portion of the channel portion O21 of the second oxide layer O20 close to the common gate electrode G0 is also a channel region; the oxide thin film transistor 20 has three channel regions.

[0071] Optionally, in some other embodiments of the present application, such as Figure 4 As shown, in addition to the common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, the oxide thin film transistor 20 may also include a second gate electrode G2, which is located on the side of the second oxide layer O20 away from the substrate 10; at this time, the gate G10 corresponding to the first oxide layer O10 is the common gate electrode G0, and the portion of the channel portion O11 of the first oxide layer O10 close to the common gate electrode G0 is the channel region; the gate G20 corresponding to the second oxide layer O20 includes the common gate electrode G0 and the second gate electrode G2, and the portion of the channel portion O21 of the second oxide layer O20 close to the common gate electrode G0 and the portion of the channel portion O21 of the second oxide layer O20 close to the second gate electrode G2 are also channel regions; the oxide thin film transistor 20 has three channel regions.

[0072] Optionally, in some further embodiments of the present application, as Figure 5As shown, in addition to the common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, the oxide thin film transistor 20 also includes a first gate electrode G1 and a second gate electrode G2. The first gate electrode G1 is located on the side of the first oxide layer O10 close to the substrate 10, and the second gate electrode G2 is located on the side of the second oxide layer O20 away from the substrate 10. At this time, the gate G10 corresponding to the first oxide layer O10 includes the common gate electrode G0 and the first gate electrode G1. The portion of the channel portion O11 of the first oxide layer O10 close to the common gate electrode G0 and the portion of the channel portion O11 of the first oxide layer O10 close to the first gate electrode G1 are both channel regions. The gate G20 corresponding to the second oxide layer O20 includes the common gate electrode G0 and the second gate electrode G2. The portion of the channel portion O21 of the second oxide layer O20 close to the common gate electrode G0 and the portion of the channel portion O21 of the second oxide layer O20 close to the second gate electrode G2 are also channel regions. The oxide thin film transistor 20 has four channel regions.

[0073] Alternatively, the oxide thin film transistor 20 may also include a first gate electrode G1, a second gate electrode G2, a third gate electrode and a fourth gate electrode, wherein the first gate electrode G1 is located on a side of the first oxide layer O10 close to the substrate 10, the second gate electrode G2 is located on a side of the second oxide layer O20 away from the substrate 10, the third gate electrode and the fourth gate electrode are both located between the first oxide layer O10 and the second oxide layer O20, and the fourth gate electrode is located on a side of the third electrode away from the substrate 10. At this time, the gate electrode G10 corresponding to the first oxide layer O10 includes the first gate electrode G1 and the third gate electrode, and the gate electrode G20 corresponding to the second oxide layer O20 includes the second gate electrode G2 and the fourth gate electrode. The above-mentioned common gate electrode G0 is the result of merging the third gate electrode and the fourth gate electrode, which is conducive to reducing the thickness of the display panel.

[0074] Optionally, in some other embodiments of the present application, such as Figure 6 As shown, the oxide thin film transistor 20 includes a first gate electrode G1 and a second gate electrode G2. The first gate electrode G1 is located on the side of the first oxide layer O10 close to the substrate 10, and the second gate electrode G2 is located on the side of the second oxide layer O20 away from the substrate 10. At this time, the gate G10 corresponding to the first oxide layer O10 is the first gate electrode G1, and the portion of the channel portion O11 of the first oxide layer O10 close to the first gate electrode G1 is the channel region. The gate G10 corresponding to the second oxide layer O20 is the second gate electrode G2, and the portion of the channel portion O21 of the second oxide layer O20 close to the second gate electrode G2 is also the channel region. The oxide thin film transistor 20 has two channel regions.

[0075] It can be understood that, the more channel regions the oxide thin film transistor 20 has, the greater the output current of the oxide thin film transistor 20 can be.

[0076] In summary, if Figures 1-6 As shown, the oxide thin film transistor 20 includes an oxide semiconductor layer 201, and the oxide semiconductor layer 201 includes one of a first oxide layer O10 and a second oxide layer O20, that is, the oxide semiconductor layer 201 is the first oxide layer O10, or the oxide semiconductor layer 201 is the second oxide layer O20, the oxide thin film transistor 20 includes a gate electrode 202 corresponding to the oxide semiconductor layer 201, and a gate insulating layer 203 located between the oxide semiconductor layer 201 and the corresponding gate electrode 202; the oxide semiconductor layer 201 includes a channel portion 204 and a conductor portion 205 located on both sides of the channel portion 204, in a direction perpendicular to the plane of the substrate 10, the channel portion 204 of the oxide semiconductor layer 201 overlaps with the corresponding gate electrode 202, and the portion of the channel portion 204 of the oxide semiconductor layer 201 close to the corresponding gate electrode 202 is a channel region.

[0077] On this basis, optionally, in some embodiments of the present application, such as Figure 7-11 As shown, the oxide semiconductor layer 201 (such as the first oxide layer O10 or the second oxide layer O20 in each figure) includes a first sublayer Z1 and a second sublayer Z2. In the direction perpendicular to the plane of the substrate 10, the second sublayer Z2 is located on the side of the first sublayer Z1 away from the corresponding gate electrode 202. In other words, the first sublayer Z1 is the sublayer closest to the corresponding gate electrode 202 in the oxide semiconductor layer 201, and the second sublayer Z2 is located on the side of the first sublayer Z1 away from the corresponding gate electrode 202.

[0078] As previously mentioned, the portion of the channel portion 204 of the oxide semiconductor layer 201 that is closest to the corresponding gate electrode 202 constitutes the channel region. That is, the first sublayer Z1 of the oxide semiconductor layer 201 that is closest to the corresponding gate electrode 202 at least partially corresponds to the channel region. Therefore, the molar fraction of the narrow-bandgap element in the first sublayer Z1 of the oxide semiconductor layer 201 can be set to be greater than the molar fraction of the narrow-bandgap element in the second sublayer Z2, thereby increasing the electron mobility in the channel region of the oxide semiconductor layer 201 and, in turn, the output current of the device. Furthermore, to prevent the oxide semiconductor layer 201 from being easily conductive due to the increased molar fraction of the narrow-bandgap element in the first sublayer Z1, the thickness of the first sublayer Z1 of the oxide semiconductor layer 201 can be set to be less than the thickness of the second sublayer Z2, so that the total amount of the narrow-bandgap element in the oxide semiconductor layer 201 is not excessive, thereby reducing the risk of the oxide semiconductor layer 201 being conductive.

[0079] Optionally, in some embodiments of the present application, such as Figure 7 As shown, the oxide thin film transistor 20 includes a common gate electrode G0, which is located between a first oxide layer O10 and a second oxide layer O20. In this case, the first oxide layer O10 may include a first sublayer Z1 closest to the common gate electrode G0 and a second sublayer Z2 located on a side of the first sublayer Z1 away from the common gate electrode G0. The molar fraction of the narrow bandgap element in the first sublayer Z1 is greater than the molar fraction of the narrow bandgap element in the second sublayer Z2. The thickness of the first sublayer Z1 is less than the thickness of the second sublayer Z2. In this way, the first sublayer Z1 at least partially corresponds to the channel region of the first oxide layer O10 close to the common gate electrode G0, thereby improving the electron mobility in the channel region of the first oxide layer O10 close to the common gate electrode G0, thereby improving the output current of the device, and making the first oxide layer O10 less likely to be conductive.

[0080] And / or, the second oxide layer O20 may include a first sublayer Z1 closest to the common gate electrode G0 and a second sublayer Z2 located on the side of the first sublayer Z1 away from the common gate electrode G0, and the molar fraction of the narrow bandgap element in the first sublayer Z1 is greater than the molar fraction of the narrow bandgap element in the second sublayer Z2, and the thickness of the first sublayer Z1 is less than the thickness of the second sublayer Z2. In this way, the first sublayer Z1 at least partially corresponds to the channel region of the second oxide layer O20 close to the common gate electrode G0, thereby improving the electron mobility in the channel region of the second oxide layer O20 close to the common gate electrode G0, thereby improving the output current of the device, and making the second oxide layer O20 not easily conductive.

[0081] Optionally, in other embodiments of the present application, such as Figure 8As shown, the oxide thin film transistor 20 includes, in addition to the common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, a first gate electrode G1, which is located on the side of the first oxide layer O10 close to the substrate 10; at this time, since the first oxide layer O10 corresponds to the two gate electrodes, the common gate electrode G0 and the first gate electrode G1, the first oxide layer O10 may include a first sublayer Z1, a second sublayer Z2 and a first sublayer Z1 stacked in a direction away from the substrate 10, wherein one first sublayer Z1 at least partially corresponds to the channel region of the first oxide layer O10 close to the first gate electrode G1, and the other sublayer Z2 corresponds to the channel region of the first oxide layer O10 close to the first gate electrode G1. A first sublayer Z1 at least partially corresponds to the channel region of the first oxide layer O10 near the common gate electrode G0. It is understandable that the molar fractions of the narrow bandgap elements in the two first sublayers Z1 can be the same or different, but both are greater than the molar fraction of the narrow bandgap elements in the second sublayer Z2. In addition, the thicknesses of the two first sublayers Z1 can be the same or different, but both are less than the thickness of the second sublayer Z2. In this way, the electron mobility in the channel region of the first oxide layer O10 near the first gate electrode G1 and the channel region of the first oxide layer O10 near the common gate electrode G0 can be improved, thereby increasing the output current of the device and making the first oxide layer O10 less likely to be conductive.

[0082] And / or, the second oxide layer O20 may include a first sublayer Z1 closest to the common gate electrode G0 and a second sublayer Z2 located on the side of the first sublayer Z1 away from the common gate electrode G0, and the molar fraction of the narrow bandgap element in the first sublayer Z1 is greater than the molar fraction of the narrow bandgap element in the second sublayer Z2, and the thickness of the first sublayer Z1 is less than the thickness of the second sublayer Z2. In this way, the first sublayer Z1 at least partially corresponds to the channel region of the second oxide layer O20 close to the common gate electrode G0, thereby improving the electron mobility in the channel region of the second oxide layer O20 close to the common gate electrode G0, thereby improving the output current of the device, and making the second oxide layer O20 not easily conductive.

[0083] Optionally, in some other embodiments of the present application, such as Figure 9As shown, the oxide thin film transistor 20 includes, in addition to the common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, a second gate electrode G2, which is located on the side of the second oxide layer O20 away from the substrate 10. In this case, the first oxide layer O10 may include a first sublayer Z1 closest to the common gate electrode G0 and a second sublayer Z2 located on the side of the first sublayer Z1 away from the common gate electrode G0, and the molar fraction of the narrow bandgap element in the first sublayer Z1 is greater than the molar fraction of the narrow bandgap element in the second sublayer Z2, and the thickness of the first sublayer Z1 is less than the thickness of the second sublayer Z2. In this way, the first sublayer Z1 at least partially corresponds to the channel region of the first oxide layer O10 close to the common gate electrode G0, thereby improving the electron mobility in the channel region of the first oxide layer O10 close to the common gate electrode G0, thereby improving the output current of the device, and making the first oxide layer O10 less likely to be conductive.

[0084] And / or, since the second oxide layer O20 corresponds to the two gate electrodes, the common gate electrode G0 and the second gate electrode G2, the second oxide layer O20 may include a first sublayer Z1, a second sublayer Z2, and a first sublayer Z1 stacked in a direction away from the substrate 10, wherein one first sublayer Z1 at least partially corresponds to a channel region of the second oxide layer O20 close to the common gate electrode G0, and another first sublayer Z1 at least partially corresponds to a channel region of the second oxide layer O10 close to the second gate electrode G2. It can be understood that this The molar fraction of the narrow bandgap element in the two first sub-layers Z1 can be the same or different, but both are greater than the molar fraction of the narrow bandgap element in the second sub-layer Z2. Moreover, the thickness of the two first sub-layers Z1 can be the same or different, but both are less than the thickness of the second sub-layer Z2. In this way, the electron mobility of the channel region of the second oxide layer O20 close to the common gate electrode G0 and the channel region of the second oxide layer O20 close to the second gate electrode G2 can be improved, thereby increasing the output current of the device and making the second oxide layer O20 less likely to be conductive.

[0085] Optionally, in some further embodiments of the present application, as Figure 10As shown, the oxide thin film transistor 20 includes, in addition to the common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, a first gate electrode G1 and a second gate electrode G2. The first gate electrode G1 is located on the side of the first oxide layer O10 close to the substrate 10, and the second gate electrode G2 is located on the side of the second oxide layer O20 away from the substrate 10. At this time, since the first oxide layer O10 corresponds to the common gate electrode G0 and the first gate electrode G1, the first oxide layer O10 may include a first sublayer Z1, a second sublayer Z2 and a first sublayer Z1 stacked in a direction away from the substrate 10, wherein one first sublayer Z1 at least partially corresponds to the first oxide layer O10. O10 is close to the channel region of the first gate electrode G1, and another first sub-layer Z1 at least partially corresponds to the channel region of the first oxide layer O10 close to the common gate electrode G0. It can be understood that the molar fractions of the narrow bandgap elements in the two first sub-layers Z1 can be the same or different, but are both greater than the molar fraction of the narrow bandgap elements in the second sub-layer Z2, and the thicknesses of the two first sub-layers Z1 can be the same or different, but are both less than the thickness of the second sub-layer Z2. In this way, the electron mobility of the channel region of the first oxide layer O10 close to the first gate electrode G1 and the channel region of the first oxide layer O10 close to the common gate electrode G0 can be improved, thereby increasing the output current of the device and making the first oxide layer O10 less likely to be conductive;

[0086] And / or, since the second oxide layer O20 corresponds to the two gate electrodes, the common gate electrode G0 and the second gate electrode G2, the second oxide layer O20 may include a first sublayer Z1, a second sublayer Z2, and a first sublayer Z1 stacked in a direction away from the substrate 10, wherein one first sublayer Z1 at least partially corresponds to a channel region of the second oxide layer O20 close to the common gate electrode G0, and another first sublayer Z1 at least partially corresponds to a channel region of the second oxide layer O10 close to the second gate electrode G2. It can be understood that this The molar fraction of the narrow bandgap element in the two first sub-layers Z1 can be the same or different, but both are greater than the molar fraction of the narrow bandgap element in the second sub-layer Z2. Moreover, the thickness of the two first sub-layers Z1 can be the same or different, but both are less than the thickness of the second sub-layer Z2. In this way, the electron mobility of the channel region of the second oxide layer O20 close to the common gate electrode G0 and the channel region of the second oxide layer O20 close to the second gate electrode G2 can be improved, thereby increasing the output current of the device and making the second oxide layer O20 less likely to be conductive.

[0087] Optionally, in some other embodiments of the present application, such as Figure 11As shown, the oxide thin film transistor 20 includes a first gate electrode G1 and a second gate electrode G2. The first gate electrode G1 is located on a side of the first oxide layer O10 close to the substrate 10, and the second gate electrode G2 is located on a side of the second oxide layer O20 away from the substrate 10. At this time, the first oxide layer O10 may include a first sublayer Z1 closest to the first gate electrode G1 and a second sublayer Z2 located on a side of the first sublayer Z1 away from the first gate electrode G1. The molar fraction of the narrow bandgap element in the first sublayer Z1 is greater than the molar fraction of the narrow bandgap element in the second sublayer Z2. The thickness of the first sublayer Z1 is less than the thickness of the second sublayer Z2. In this way, the first sublayer Z1 at least partially corresponds to the channel region of the first oxide layer O10 close to the first gate electrode G1, thereby improving the electron mobility in the channel region of the first oxide layer O10 close to the first gate electrode G1, thereby improving the output current of the device, and making the first oxide layer O10 less likely to be conductive.

[0088] And / or, the second oxide layer O20 may include a first sublayer Z1 closest to the second gate electrode G2 and a second sublayer Z2 located on the side of the first sublayer Z1 away from the second gate electrode G2, and the molar fraction of the narrow bandgap element in the first sublayer Z1 is greater than the molar fraction of the narrow bandgap element in the second sublayer Z2, and the thickness of the first sublayer Z1 is less than the thickness of the second sublayer Z2. In this way, the first sublayer Z1 at least partially corresponds to the channel region of the second oxide layer O20 close to the second gate electrode G2, thereby improving the electron mobility in the channel region of the second oxide layer O20 close to the second gate electrode G2, thereby improving the output current of the device, and making the second oxide layer O20 not easily conductive.

[0089] In summary, any oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20) in the oxide thin film transistor 20 may correspond to one gate electrode 202 or two gate electrodes 202. When one oxide semiconductor layer 201 corresponds to one gate electrode 202, the oxide semiconductor layer 201 may only include a first sublayer Z1 closest to the corresponding gate electrode 202 and a second sublayer Z2 located in the first sublayer Z1 away from the corresponding gate electrode 202; when one oxide semiconductor layer 201 corresponds to two gate electrodes 202, the oxide semiconductor layer 201 is located between the corresponding two gate electrodes 202, and the oxide semiconductor layer 201 may include a first sublayer Z1, a second sublayer Z2 and a first sublayer Z1 stacked in a direction away from the substrate 10.

[0090] The inventors continued their research and found that for any oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20) in the oxide thin film transistor 20, the thinner the thickness of the gate insulating layer 203 between the oxide semiconductor layer 201 and the corresponding gate electrode 202, the greater the output current of the channel region of the oxide semiconductor layer 201 close to the corresponding gate electrode 202, which makes the output current of the conductive channel corresponding to the oxide semiconductor layer 201 greater, but the oxide semiconductor layer 201 is also relatively easier to be conductive.

[0091] As is known from the above, the first oxide layer O10 is correspondingly provided with a gate electrode G10, and a gate insulating layer I10 is provided between the first oxide layer O10 and the corresponding gate electrode G10; the second oxide layer O20 is correspondingly provided with a gate electrode G20, and a gate insulating layer I20 is provided between the second oxide layer O20 and the corresponding gate electrode G20; thus, optionally, in some embodiments of the present application, the thickness of at least one gate insulating layer I20 corresponding to the second oxide layer O20 can be set to be smaller than the thickness of at least one gate insulating layer I10 corresponding to the first oxide layer O10, so that by reducing the thickness of at least one gate insulating layer I20 corresponding to the second oxide layer O20, the output current of the conductive channel corresponding to the second oxide layer O20 is increased, thereby increasing the output current of the device, and by increasing the thickness of at least one gate insulating layer I10 corresponding to the first oxide layer O10, the risk of the first oxide layer O10 being conductive due to the increase in the molar fraction of its narrow bandgap element is reduced.

[0092] It should be noted that in the embodiments of the present application, the thickness of the gate insulating layer I10 corresponding to the first oxide layer O10 refers to the thickness of the gate insulating layer I10 between the first oxide layer O10 and the corresponding gate electrode G10. Similarly, the thickness of the gate insulating layer I20 corresponding to the second oxide layer O20 refers to the thickness of the gate insulating layer I20 between the second oxide layer O20 and the corresponding gate electrode G20. In the various figures of this application, for ease of drawing, the thickness of each gate insulating layer appears to be inconsistent throughout the entire layer. However, in actual processes, the thickness of each gate insulating layer is consistent throughout the entire layer.

[0093] like Figure 12As shown, taking the example in which the first oxide layer O10 is correspondingly provided with two gate electrodes, a common gate electrode G0 and a first gate electrode G1, and the second oxide layer O20 is correspondingly provided with two gate electrodes, a common gate electrode G0 and a second gate electrode G2, it can be seen that a first gate insulating layer I11 is provided between the first oxide layer O10 and the first gate electrode G1, and the thickness of the first gate insulating layer I11 is d11; a second gate insulating layer I12 is provided between the first oxide layer O10 and the common gate electrode G0, and the thickness of the second gate insulating layer I12 is d12; a third gate insulating layer I21 is provided between the second oxide layer O20 and the common gate electrode G0, and the thickness of the third gate insulating layer I21 is d21; a fourth gate insulating layer I22 is provided between the second oxide layer O20 and the second gate electrode G2, and the thickness of the fourth gate insulating layer I22 is d22.

[0094] Among them, the thickness d21 of the third gate insulating layer I21 can be less than the thickness d11 of the first gate insulating layer I11, or the thickness d21 of the third gate insulating layer I21 can be less than the thickness d12 of the second gate insulating layer I12, or the thickness d21 of the third gate insulating layer I12 is both less than the thickness d11 of the first gate insulating layer I11 and less than the thickness d12 of the second gate insulating layer I12; similarly, the thickness d22 of the fourth gate insulating layer I22 can be less than the thickness d11 of the first gate insulating layer I11, or the thickness d22 of the fourth gate insulating layer I22 can be less than the thickness d12 of the second gate insulating layer I12, or the thickness d22 of the fourth gate insulating layer I22 is both less than the thickness d11 of the first gate insulating layer I11 and less than the thickness d12 of the second gate insulating layer I12, depending on the specific circumstances.

[0095] From this, it can be understood that no matter whether the first oxide layer O10 corresponds to one gate electrode G10 or two gate electrodes G10, and no matter whether the second oxide layer O20 corresponds to one gate electrode G20 or two gate electrodes G20, the thickness of any gate insulating layer I20 corresponding to the second oxide layer O20 can be less than the thickness of a gate insulating layer I10 corresponding to the first oxide layer O10, and can also be less than the thickness of each gate insulating layer I10 corresponding to the first oxide layer O10. Other situations will not be elaborated.

[0096] The inventors also discovered that for any oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20) in the oxide thin film transistor 20, the greater the dielectric constant of the gate insulating layer 203 between the oxide semiconductor layer 201 and the corresponding gate electrode 202, the greater the output current of the channel region of the oxide semiconductor layer 201 close to the corresponding gate electrode 202, which makes the output current of the conductive channel corresponding to the oxide semiconductor layer 201 greater, but the oxide semiconductor layer 201 is also relatively easier to be conductive.

[0097] Therefore, optionally, in some embodiments of the present application, the dielectric constant of at least one gate insulating layer I20 corresponding to the second oxide layer O20 can be set to be greater than the dielectric constant of at least one gate insulating layer I10 corresponding to the first oxide layer O10. In this way, by increasing the dielectric constant of at least one gate insulating layer I20 corresponding to the second oxide layer O20, the output current of the conductive channel corresponding to the second oxide layer O20 is increased, thereby increasing the output current of the device, and by reducing the dielectric constant of at least one gate insulating layer I10 corresponding to the first oxide layer O10, the risk of the first oxide layer O10 being conductorized due to the increase in the molar fraction of its narrow bandgap element is reduced.

[0098] like Figure 12 As shown, the first oxide layer O10 is provided with two gate electrodes, a common gate electrode G0 and a first gate electrode G1, and the second oxide layer O20 is provided with two gate electrodes, a common gate electrode G0 and a second gate electrode G2, as an example for explanation, wherein the dielectric constant of the third gate insulating layer I21 can be greater than the dielectric constant of the first gate insulating layer I11, or the dielectric constant of the third gate insulating layer I21 can be greater than the dielectric constant of the second gate insulating layer I12, or the dielectric constant of the third gate insulating layer I12 can be greater than the dielectric constant of the second gate insulating layer I12. The dielectric constant is greater than both the dielectric constant of the first gate insulating layer I11 and the dielectric constant of the second gate insulating layer I12; similarly, the dielectric constant of the fourth gate insulating layer I22 may be greater than the dielectric constant of the first gate insulating layer I11, or the dielectric constant of the fourth gate insulating layer I22 may be greater than the dielectric constant of the second gate insulating layer I12, or the dielectric constant of the fourth gate insulating layer I22 is greater than both the dielectric constant of the first gate insulating layer I11 and the dielectric constant of the second gate insulating layer I12, depending on the specific circumstances.

[0099] From this, it can be understood that regardless of whether the first oxide layer O10 corresponds to one gate electrode G10 or two gate electrodes G10, and regardless of whether the second oxide layer O20 corresponds to one gate electrode G20 or two gate electrodes G20, the dielectric constant of any gate insulating layer I20 corresponding to the second oxide layer O20 may be greater than the dielectric constant of one gate insulating layer I10 corresponding to the first oxide layer O10, or may be greater than the dielectric constant of each gate insulating layer I10 corresponding to the first oxide layer O10, depending on the specific circumstances.

[0100] It is also understood that the dielectric constant of the oxide semiconductor layer 201 can be changed by selecting the material of the oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20 ).

[0101] In summary, by setting the thickness of at least one gate insulating layer I20 corresponding to the second oxide layer O20 to be smaller than the thickness of at least one gate insulating layer I10 corresponding to the first oxide layer O10; and / or the dielectric constant of at least one gate insulating layer I20 corresponding to the second oxide layer O20 is greater than the dielectric constant of at least one gate insulating layer I10 corresponding to the first oxide layer O10, the output current of the conductive channel corresponding to the second oxide layer O20 is increased, thereby increasing the output current of the device, and reducing the risk of the first oxide layer O10 being conductorized due to the increase in the molar fraction of its narrow bandgap elements.

[0102] As is known from the above, any oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20) in the oxide thin film transistor 20 can be correspondingly provided with a gate electrode 202 or two gate electrodes 202, and the corresponding gate electrode 202 is located on the side of the oxide semiconductor layer 201 close to the substrate 10, or, on the side of the oxide semiconductor layer 201 away from the substrate 10, and the portion of the channel portion 204 of the oxide semiconductor layer 201 close to the corresponding gate electrode 202 is the channel region, so that the oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20) has one channel region or two channel regions.

[0103] Figure 13a 1 shows a schematic top view of an oxide semiconductor layer 201 (a first oxide layer O10 or a second oxide layer O20). Figure 13b A schematic top view of an oxide semiconductor layer 201 is shown in which a gate electrode 202 is provided on both the side close to the substrate 10 and the side away from the substrate 10. Figure 13a and 13bAs shown, the oxide semiconductor layer 201 includes a channel portion 204 and conductor portions 205 located on both sides of the channel portion 204, wherein the conductor portion 205 is heavily doped so as to be electrically connected to the source electrode S1 and the drain electrode D2. In an actual process, if a corresponding gate electrode 202 is provided on the side of the oxide semiconductor layer 201 facing away from the substrate 10, the gate electrode 202 on the side of the oxide semiconductor layer 201 facing away from the substrate 10 can be used as a blocking mask to shield the channel portion 204 of the oxide semiconductor layer 201 from ion implantation, while the two sides of the channel portion 204 of the oxide semiconductor layer 201 are ion implanted to form the conductor portion 205. This shielding is similar to a "self-aligned mask". In addition, considering that after ion implantation is performed on both sides of the channel portion 204 of the oxide semiconductor layer 201, the heavily doped region will extend a little toward the channel portion 204 of the oxide semiconductor layer 201. Therefore, a gate electrode 202 is provided on the side of the oxide semiconductor layer 201 facing away from the substrate 10. The length L1 of the gate electrode 202 disposed on the side of the oxide semiconductor layer 201 facing the substrate 10 can be slightly less than the length L of the channel portion 204 of the oxide semiconductor layer 201. If the corresponding gate electrode 202 is not disposed on the side of the oxide semiconductor layer 201 facing away from the substrate 10, a photolithography mask is used to shield the channel portion 204 of the oxide semiconductor layer 201 from ion implantation, so that both sides of the channel portion 204 of the oxide semiconductor layer 201 are ion implanted to form the conductor portion 205. If the corresponding gate electrode 202 is disposed on the side of the oxide semiconductor layer 201 facing the substrate 10, the length L2 of the gate electrode 202 disposed on the side of the oxide semiconductor layer 201 facing the substrate 10 can be slightly greater than the length L of the channel portion 204 of the oxide semiconductor layer 201. Furthermore, the width W1 of the gate electrode 202 on the side of the oxide semiconductor layer 201 facing away from the substrate 10 and the width W2 of the gate electrode 202 on the side of the oxide semiconductor layer 201 facing the substrate 10 are generally greater than the width W of the channel portion 204 of the oxide semiconductor layer 201.

[0104] It can be understood that for any oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20) in the oxide thin film transistor 20, if a corresponding gate electrode 202 is provided on the side of the oxide semiconductor layer 201 facing away from the substrate 10, then the portion of the channel portion 204 of the oxide semiconductor layer 201 close to the gate electrode 202 on the side facing away from the substrate 10 is the channel region. If a corresponding gate electrode 202 is provided on the side of the oxide semiconductor layer 201 facing the substrate 10, then the portion of the channel portion 204 of the oxide semiconductor layer 201 close to the gate electrode 202 on the side facing the substrate 10 is the channel region. In other words, the size of the channel portion 204 of the oxide semiconductor layer 201 determines the size of the channel region of the oxide semiconductor layer 201. The length L of the channel portion 204 of the oxide semiconductor layer 201 is the length L of the channel region of the oxide semiconductor layer 201, and the width W of the channel portion 204 of the oxide semiconductor layer 201 is the width W of the channel region of the oxide semiconductor layer 201.

[0105] Based on this, the inventors have found that by increasing the length L and / or width W of the channel region of the oxide semiconductor layer 201 (the first oxide layer O10 or the second oxide layer O20), the risk of the oxide semiconductor layer 201 being conductive due to the increase in the molar fraction of its narrow bandgap elements can be reduced, and the oxide semiconductor layer 201 can be made more stable in terms of process.

[0106] Therefore, optionally, in some embodiments of the present application, the length of the channel region of the first oxide layer O10 can be set to be greater than the length of the channel region of the second oxide layer O20; and / or, the width of the channel region of the first oxide layer O10 can be set to be greater than the width of the channel region of the second oxide layer O20, that is, the length and / or width of the channel region of the first oxide layer O10 is appropriately increased, thereby reducing the risk of the first oxide layer O10 being conductive due to the increase in the molar fraction of its narrow bandgap elements, and making the first oxide layer O10 more stable in terms of process.

[0107] Further optionally, in some embodiments of the present application, the orthographic projection of the channel region of the second oxide layer O20 on the plane where the substrate 10 is located can be set to be located within the orthographic projection of the channel region of the first oxide layer O10 on the plane where the substrate 10 is located. In this way, not only is the length of the channel region of the first oxide layer O10 greater than the length of the channel region of the second oxide layer O20, the width of the channel region of the first oxide layer O10 is greater than the width of the channel region of the second oxide layer O20, but also, in the direction perpendicular to the plane where the substrate 10 is located, the channel region of the second oxide layer O20 and the channel region of the first oxide layer O10 are aligned, so that the oxide thin film transistor 20 has a compact and stable structure.

[0108] As is known from the foregoing, in the oxide thin film transistor 20, the source electrode S1 is electrically connected to the drain electrode D1 through the first oxide layer O10, and the source electrode S2 is electrically connected to the drain electrode D1 through the second oxide layer O20. For the connection method of the first oxide layer O10 and the source electrode S1 and the drain electrode D1, and the connection method of the second oxide layer O20 and the source electrode S1 and the drain electrode D1, optionally, in some embodiments of the present application, such as Figures 1-12 As shown, the source electrode S1 and the drain electrode D1 are located on the side of the second oxide layer O20 facing away from the substrate 10. The source electrode S1 is electrically connected to the first oxide layer O10 through the first via K1, and the drain electrode D1 is electrically connected to the first oxide layer O10 through the second via K2. The source electrode S1 is directly overlapped with the second oxide layer O20, and the drain electrode D1 is directly overlapped with the second oxide layer O20. In this way, the process is relatively simpler.

[0109] However, considering that when the source electrode S1 and the drain electrode D1 are directly overlapped on the second oxide layer O20, the surface of the second oxide layer O20 may be damaged during the process of etching to form the source electrode S1 and the drain electrode D1. Based on this, optionally, in other embodiments of the present application, such as Figure 14 As shown, taking the example in which the first oxide layer O10 is provided with two gate electrodes, a common gate electrode G0 and a first gate electrode G1, and the second oxide layer O20 is provided with two gate electrodes, a common gate electrode G0 and a second gate electrode G2, as an example, it can be seen that an etch stop layer ESL is provided on the side of the second oxide layer O20 facing away from the substrate 10, and the source electrode S1 and the drain electrode D1 are located on the side of the etch stop layer ESL facing away from the substrate 10. The source electrode S1 is electrically connected to the first oxide layer O10 through a first via K1, and the drain electrode D1 is electrically connected to the first oxide layer O10 through a second via K2. The source electrode S1 is also electrically connected to the second oxide layer O20 through a third via K3 penetrating the etch stop layer ESL, and the drain electrode D1 is also electrically connected to the second oxide layer O20 through a fourth via K4 penetrating the etch stop layer ESL. In this way, damage to the surface of the second oxide layer O20 when etching the source electrode S1 and the drain electrode D1 can be avoided, thereby improving the reliability of the oxide thin film transistor 20.

[0110] It can be understood from this that no matter whether the first oxide layer O10 corresponds to one gate electrode G10 or two gate electrodes G10, and no matter whether the second oxide layer O20 corresponds to one gate electrode G20 or two gate electrodes G20, an etching stopper layer ESL can be provided on the side of the second oxide layer O20 facing away from the substrate 10, so that the source electrode S1 and the drain electrode D1 are located on the side of the etching stopper layer ESL facing away from the substrate 10, the source electrode S1 is electrically connected to the first oxide layer O10 through the first via K1, the drain electrode D1 is electrically connected to the first oxide layer O10 through the second via K2, the source electrode S1 is also electrically connected to the second oxide layer O20 through the third via K3 penetrating the etching stopper layer ESL, and the drain electrode D1 is also electrically connected to the second oxide layer O20 through the fourth via K4 penetrating the etching stopper layer ESL. Other situations are not described in detail.

[0111] Figure 15 A schematic top view of a display panel provided in an embodiment of the present application is shown in FIG. Figure 15 As shown, the display panel includes a plurality of pixel circuits pixel arranged in an array, a driving circuit VSR and a driving integrated circuit IC located on at least one side of the plurality of pixel circuits pixel arranged in an array, wherein the driving integrated circuit IC receives an operating voltage signal of the driving integrated circuit IC, a setting signal of the driving circuit VSR and a display picture signal provided by the IC signal line H1, and provides a driving control signal to the driving circuit VSR through a driving control signal line H2, and also provides a data signal to each column of the pixel circuit pixel through a data signal line data; the driving circuit VSR provides a scanning signal to each row of the pixel circuit pixel under the control of the driving control signal; the pixel circuit pixel also receives a first power supply voltage signal through a first power supply voltage line PVDD, and receives a second power supply voltage signal through a second power supply voltage line PVEE.

[0112] It is understandable that the display panel further includes a plurality of light emitting elements, and the pixel circuit pixel drives the light emitting elements to emit light and display under the control of the received scan signal, data signal, first power supply voltage signal and second power supply voltage signal.

[0113] Figure 16 FIG. 1 shows a schematic diagram of a circuit structure of a pixel circuit in a display panel provided by an embodiment of the present application, such as Figure 16As shown, the pixel circuit pixel includes a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a gate reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7 and a storage capacitor Cst. The signal lines electrically connected to the pixel circuit pixel include a scan line SN1, a scan line SN2 and a scan line SP, a light-emitting control line Em, a data line data and a first power supply voltage line PVDD. The pixel circuit pixel is electrically connected to the anode of the light-emitting element 30, and the cathode of the light-emitting element 30 is electrically connected to the second power supply voltage line PVEE.

[0114] The first electrode of the first light emitting control transistor T1 is electrically connected to the first power supply voltage line PVDD, the second electrode of the first light emitting control transistor T1 is electrically connected to the second node N2, and the gate of the first light emitting control transistor T1 is electrically connected to the light emitting control line Em;

[0115] A first electrode of the data writing transistor T2 is electrically connected to the data line data, a second electrode of the data writing transistor T2 is electrically connected to the second node N2, and a gate of the data writing transistor T2 is electrically connected to the scan line SP;

[0116] A first electrode of the driving transistor T3 is electrically connected to the second node N2, a second electrode of the driving transistor T3 is electrically connected to the third node N3, and a gate of the driving transistor T3 is electrically connected to the first node N1;

[0117] A first electrode of the compensation transistor T4 is electrically connected to the third node N3, a second electrode of the compensation transistor T4 is electrically connected to the first node N1, and a gate of the compensation transistor T4 is electrically connected to the scan line SN2;

[0118] A first electrode of the gate reset transistor T5 is electrically connected to the reference voltage line Ref, a second electrode of the gate reset transistor T5 is electrically connected to the first node N1, and a gate of the gate reset transistor T5 is electrically connected to the scan line SN1;

[0119] A first electrode of the second light emitting control transistor T6 is electrically connected to the third node N3, a second electrode of the second light emitting control transistor T6 is electrically connected to the fourth node N4, and a gate of the second light emitting control transistor T6 is electrically connected to the light emitting control line Em;

[0120] A first electrode of the anode reset transistor T7 is electrically connected to the reference voltage line Ref, a second electrode of the anode reset transistor T7 is electrically connected to the fourth node N4, and a gate of the anode reset transistor T7 is electrically connected to the scan line SP;

[0121] Thus, a pixel circuit with a 7T1C structure is realized.

[0122] It can be understood that the first node N1, the second node N2, the third node N3 and the fourth node N4 may be virtually existing connection nodes or actually existing connection nodes.

[0123] It should be noted that Figure 16 The pixel circuit shown is only an example. In practical applications, pixel circuits with other circuit structures can be selected based on needs and are not limited to Figure 16 The 7T1C pixel circuit shown.

[0124] Figure 17 Shown to provide Figure 16 A timing diagram of each signal of the pixel circuit pixel shown in FIG. Figure 16 and Figure 17 As shown, the scanning line SN1 provides a scanning signal VSN1 to the pixel circuit pixel, the scanning line SP provides a scanning signal VSP to the pixel circuit pixel, the scanning line SN2 provides a scanning signal VSN2 to the pixel circuit pixel, and the light-emitting control line Em provides a light-emitting control signal VEm (also a scanning signal) to the pixel circuit pixel. Taking the case where all thin film transistors in the pixel circuit 10 are PMOS thin film transistors as an example, the effective levels of the scanning signal VSN1, the scanning signal VSP, the scanning signal VSN2 and the light-emitting control signal VEm are low levels, and the invalid level is high levels.

[0125] Combine Figure 16 and Figure 17 As shown in FIG, the working process of the pixel circuit pixel is roughly divided into the following periods, among which:

[0126] During period t1, the scanning signal VSN1 is at an active level (low level), turning on the gate reset transistor T5. The reference voltage signal VRef provided by the reference voltage line Ref resets the first node N1 (ie, the gate of the driving transistor T3) through the turned-on gate reset transistor T5.

[0127] During the t2 period, the scan signal VSN2 is at an effective level (low level), turning on the compensation transistor T4, and the scan signal VSP is at an effective level (low level), turning on the data write transistor T2, and writing the data signal Vdata provided by the data line data into the gate of the driving transistor T3, also known as the threshold capture of the driving transistor T3; during the t2 period, the scan signal VSP is at an effective level (low level), and also turning on the anode reset transistor T7, and the reference voltage signal VRef provided by the reference voltage line Ref resets the fourth node N4 through the turned-on anode reset transistor T7.

[0128] During the period t3 , the light emitting control signal VEm is at an active level (low level), the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on, and the driving transistor T3 drives the light emitting element 30 to emit light.

[0129] In the display panel, the light emitting control signal VEm scans each row of pixel circuits at a fixed frequency, such as Figure 17 As shown, the total period in which the light-emitting control signal Em undergoes a valid level period and an invalid level period is called a frame, a frame including the t1 period, the t2 period and the t3 period is called a data writing frame P1, and the total period in which the pixel circuits of each row in the display panel complete the writing of the data signal is called a data writing cycle. In this way, a data writing cycle of the display panel includes M frames of refresh screen, M≥2, and the M frames include a data writing frame P1 and at least one holding frame P2, wherein, in the data writing frame P1, the pixel circuit 10 writes a new data signal and displays a new frame of screen; in the holding frame P2, the pixel circuit 10 refreshes normally, but the pixel circuit 10 maintains the data signal of the previous frame and displays the previous frame of screen.

[0130] It is understandable that if Figure 16 As shown, the pixel circuit pixel includes a driving transistor T3, a first light-emitting control transistor T1, and a second light-emitting control transistor T6. The first light-emitting control transistor T1 is electrically connected between the first power supply voltage line PVDD and the driving transistor T3, and the second light-emitting control transistor T6 is electrically connected between the driving transistor T3 and the light-emitting element 30. In this way, the first light-emitting control transistor T1, the driving transistor T3, and the second light-emitting control transistor T6 are located on the path of driving the light-emitting element 30 and all require high output current. The data writing transistor T2 and the compensation transistor T4 are located on the data writing path and do not require high output current, but require high device stability. Therefore, optionally, in some embodiments of the present application, at least one of the driving transistor T3, the first light-emitting control transistor T1, and the second light-emitting control transistor T6 can be an oxide thin film transistor 20. The various structures of the oxide thin film transistor 20 can refer to the aforementioned embodiments and will not be described in detail.

[0131] Furthermore, when at least two of the driving transistor T3, the first emission control transistor T1, and the second emission control transistor T6 are oxide thin film transistors 20, the structures of the two oxide thin film transistors 20 may be the same or different. For example, if both the driving transistor T3 and the first emission control transistor T1 are oxide thin film transistors 20, the structures of the driving transistor T3 and the first emission control transistor T1 may be the same or different, depending on the specific situation.

[0132] For ease of understanding, Figure 1 、 Figure 2 and Figure 7 As shown, when the oxide thin film transistor 20 includes a common gate electrode G0, and the common gate electrode G0 is located between the first oxide layer O10 and the second oxide layer O20, the equivalent circuit of the oxide thin film transistor 20 is as follows: Figure 18 shown.

[0133] like Figure 3 and Figure 8 As shown, when the oxide thin film transistor 20 includes a common gate electrode G0 and a first gate electrode G1, and the common gate electrode G0 is located between the first oxide layer O10 and the second oxide layer O20, and the first gate electrode G1 is located on the side of the first oxide layer O10 close to the substrate 10, the equivalent circuit of the oxide thin film transistor 20 is as follows: Figure 19 As shown, the common gate electrode G0 and the first gate electrode G1 are electrically connected.

[0134] like Figure 4 and Figure 9 As shown, when the oxide thin film transistor 20 includes a common gate electrode G0 and a second gate electrode G2, and the common gate electrode G0 is located between the first oxide layer O10 and the second oxide layer O20, and the second gate electrode G2 is located on the side of the second oxide layer O20 away from the substrate 10, the equivalent circuit of the oxide thin film transistor 20 is as follows Figure 20 As shown, the common gate electrode G0 and the second gate electrode G2 are electrically connected.

[0135] like Figure 5 、 Figure 10 、 Figure 12 as well as Figure 14 As shown, when the oxide thin film transistor 20 includes a common gate electrode G0, a first gate electrode G1, and a second gate electrode G2, and the common gate electrode G0 is located between the first oxide layer O10 and the second oxide layer O20, the first gate electrode G1 is located on the side of the first oxide layer O10 close to the substrate 10, and the second gate electrode G2 is located on the side of the second oxide layer O20 away from the substrate 10, the equivalent circuit of the oxide thin film transistor 20 is as follows: Figure 21 As shown, the common gate electrode G0, the first gate electrode G1 and the second gate electrode G2 are electrically connected.

[0136] like Figure 6 and Figure 11 As shown, when the oxide thin film transistor 20 includes a first gate electrode G1 and a second gate electrode G2, and the first gate electrode G1 is located on a side of the first oxide layer O10 close to the substrate 10, and the second gate electrode G2 is located on a side of the second oxide layer O20 away from the substrate 10, the equivalent circuit of the oxide thin film transistor 20 is as follows: Figure 22 As shown, the first gate electrode G1 and the second gate electrode G2 are electrically connected.

[0137] like Figures 18-22 As shown, since the oxide thin film transistor 20 includes a first oxide layer O10 and a second oxide layer O20 connected in parallel between the source electrode S1 and the drain electrode D1, the oxide thin film transistor 20 can be equivalent to two sub-oxide thin film transistors T201 and T202 connected in parallel. Each sub-oxide thin film transistor T201 / T202 has a single gate structure or a double gate structure. The gates of the two sub-oxide thin film transistors T201 and T202 are electrically connected and receive the same signal. In the pixel circuit pixel, the driving transistor T3 can be Figures 18-22 Similarly, the first light emitting control transistor T1 can be Figures 18-22 In any circuit structure, the second light emitting control transistor T6 can be Figures 18-22 Any circuit structure in .

[0138] Figure 23 Another schematic top view of the display panel provided in the embodiment of the present application is shown in FIG. Figure 23 As shown, optionally, the driving circuit VSR may include a first scanning driving module ScanA for providing scanning signals VSN1 and VSN2 to the pixel circuit pixel; another optional embodiment, the driving circuit VSR may include a second scanning driving module ScanB for providing a scanning signal VSP to the pixel circuit pixel; the driving module VSR may include a light-emitting control driving module Emit for providing a light-emitting control signal VEm to the pixel circuit pixel; of course, other optional embodiments, the driving circuit VSR may also include any two of the first scanning driving module ScanA, the second scanning driving module ScanB, and the light-emitting control driving module Emit, or the driving circuit VSR may also include the first scanning driving module ScanA, the second scanning driving module ScanB, and the light-emitting control driving module Emit at the same time. That is, in the present application, the driving circuit VSR may include at least one of the first scanning driving module ScanA, the second scanning driving module ScanB, and the light-emitting control driving module Emit.

[0139] like Figure 23 As shown, the shift register module VSR needs to receive driving control signals such as STV1 and STV2 transmitted by the driving integrated circuit IC through the driving control signal line H2.

[0140] like Figure 23As shown, the display panel may include two scan driver modules (e.g., ScanA or ScanB). These two scan driver modules may be disposed on opposite sides of the display panel along the pixel row direction to perform bilateral driving of each pixel row. Of course, the display panel may also include only one scan driver module, located on one side of the display panel along the pixel row direction, or two scan driver modules may be disposed on one side of the pixel row direction, depending on the specific circumstances.

[0141] The scanning driving module (such as ScanA or ScanB) includes a plurality of shift registers 41. One shift register 41 may be electrically connected to a row of pixel circuits, or may be electrically connected to a plurality of rows of pixel circuits, depending on the specific situation.

[0142] Similarly, the display panel may include two emission control and driving modules (Emit). These two emission control and driving modules (Emit) may be disposed on opposite sides of the display panel along the pixel row direction to provide bilateral driving for each pixel row. Of course, the display panel may also include only one emission control and driving module (Emit), located on one side of the display panel along the pixel row direction, or two emission control and driving modules (Emit) may be disposed on one side of the display panel along the pixel row direction, depending on the specific circumstances.

[0143] The light emitting control driving module Emit includes a plurality of shift registers 42 . One shift register 42 may be electrically connected to a row of pixel circuits pixel, or may be electrically connected to a plurality of rows of pixel circuits pixel, depending on the specific situation.

[0144] That is to say, the driving circuit VSR includes a shift register circuit with a multi-stage cascade arrangement. When the driving circuit VSR includes a scan driving module (such as ScanA or ScanB), the scan driving module (such as ScanA or ScanB) includes a shift register circuit 41 with a multi-stage cascade arrangement to provide a scan signal (such as VS1, VS2 and VSP, etc.) to the pixel circuit pixel; when the driving circuit VSR includes a light-emitting control driving module Emit, the light-emitting control driving module Emit includes a shift register circuit 42 with a multi-stage cascade arrangement to provide a light-emitting control signal VEm to the pixel circuit Pixel.

[0145] Figure 24 FIG. 4 shows a schematic diagram of a circuit structure of a shift register circuit 41 in a scan driving module (such as ScanA or ScanB) of a display panel provided in an embodiment of the present application. Figure 24As shown, the shift register circuit 41 includes a first output transistor M17 and a second output transistor M18. The first output transistor M17 is electrically connected between the first level signal VGH and the output terminal OUT of the shift register circuit 41. The second output transistor M18 is electrically connected between the second level signal XCK and the output terminal OUT of the shift register circuit 41. When the first output transistor M17 is turned on, the shift register circuit 41 outputs the first level signal VGH. When the second output transistor M18 is turned on, the shift register circuit 41 outputs the second level signal XCK.

[0146] It can be understood that the first output transistor M17 and the second output transistor M18 are located on the output path of the shift register circuit 41 and require a high output current. Therefore, at least one of the first output transistor M17 and the second output transistor M18 can be an oxide thin film transistor 20. The various structures and equivalent circuits of the oxide thin film transistor 20 can refer to the aforementioned embodiments and will not be repeated here.

[0147] Figure 25 FIG. 4 shows a circuit structure diagram of a shift register circuit 42 in a light emitting control driving module Emit of a display panel provided in an embodiment of the present application. Figure 24 As shown, the shift register circuit 42 includes a first output transistor M29 and a second output transistor M210. The first output transistor M29 is electrically connected between the first level signal VGH and the output terminal OUT of the shift register circuit 42. The second output transistor M210 is electrically connected between the second level signal VGL and the output terminal OUT of the shift register circuit 42. When the first output transistor M29 is turned on, the shift register circuit 42 outputs the first level signal VGH. When the second output transistor M210 is turned on, the shift register circuit 42 outputs the second level signal XCK.

[0148] It can be understood that the first output transistor M29 and the second output transistor M210 are located on the output path of the shift register circuit 42 and require a high output current. Therefore, at least one of the first output transistor M29 and the second output transistor M210 can be an oxide thin film transistor 20. The various structures and equivalent circuits of the oxide thin film transistor 20 can refer to the aforementioned embodiments and will not be repeated here.

[0149] Figures 26-31 Schematic diagrams of partial cross-sectional structures of several display panels provided in the embodiments of the present application are shown. Figures 26-31As shown, the oxide thin film transistor 20 includes a first oxide thin film transistor 21 and a second oxide thin film transistor 22. The number of channel regions of the first oxide thin film transistor 21 is greater than the number of channel regions of the second oxide thin film transistor 22. Thus, the output current of the first oxide thin film transistor 21 is higher than that of the second oxide thin film transistor 22.

[0150] Optionally, in some embodiments of the present application, such as Figure 26 and Figure 27 As shown, the first oxide thin film transistor 21 has three channel regions, and the second oxide thin film transistor 22 has two channel regions.

[0151] Combining the above, we can see that Figure 26 As shown, when the second oxide thin film transistor 22 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, the second oxide thin film transistor 22 has two channel regions; or Figure 27 As shown, when the second oxide thin film transistor 22 includes the first gate electrode G1 located on the side of the first oxide layer O10 close to the substrate 10 and the second gate electrode G2 located on the side of the second oxide layer O20 away from the substrate 10, the second oxide thin film transistor 22 has two channel regions.

[0152] Combining the above, we can see that Figure 26 As shown, the first oxide thin film transistor 21 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, and a first gate electrode G1 located on the side of the first oxide layer O10 close to the substrate 10, and the first oxide thin film transistor 21 has three channel regions; or Figure 27 As shown, the first oxide thin film transistor 21 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, and a second gate electrode G2 located on a side of the second oxide layer O20 away from the substrate 10. The first oxide thin film transistor 21 has three channel regions.

[0153] Optionally, in other embodiments of the present application, such as Figure 28 and Figure 29 As shown, the second oxide thin film transistor 22 has two channel regions, and the first oxide thin film transistor 21 has four channel regions.

[0154] Combining the above, we can see that Figure 28 As shown, when the second oxide thin film transistor 22 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, the second oxide thin film transistor 22 has two channel regions; or Figure 29As shown, when the second oxide thin film transistor 22 includes the first gate electrode G1 located on the side of the first oxide layer O10 close to the substrate 10 and the second gate electrode G2 located on the side of the second oxide layer O20 away from the substrate 10, the second oxide thin film transistor 22 has two channel regions.

[0155] Combining the above, we can see that Figure 28 and Figure 29 As shown, when the first oxide thin film transistor 21 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, a first gate electrode G1 located on the side of the first oxide layer O10 close to the substrate 10, and a second gate electrode G2 located on the side of the second oxide layer O20 away from the substrate 10, the first oxide thin film transistor 21 has four channel regions.

[0156] Optionally, in some further embodiments of the present application, as Figure 30 and Figure 31 As shown, the second oxide thin film transistor 22 has three channel regions, and the first oxide thin film transistor 21 has four channel regions.

[0157] Combining the above, we can see that Figure 30 As shown, the second oxide thin film transistor 22 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, and a first gate electrode G1 located on the side of the first oxide layer O10 close to the substrate 10, and the second oxide thin film transistor 22 has three channel regions; or Figure 31 As shown, the second oxide thin film transistor 22 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, and a second gate electrode G2 located on a side of the second oxide layer O20 away from the substrate 10. The second oxide thin film transistor 22 has three channel regions.

[0158] Combining the above, we can see that Figure 30 and Figure 31 As shown, when the first oxide thin film transistor 21 includes a common gate electrode G0 located between the first oxide layer O10 and the second oxide layer O20, a first gate electrode G1 located on the side of the first oxide layer O10 close to the substrate 10, and a second gate electrode G2 located on the side of the second oxide layer O20 away from the substrate 10, the first oxide thin film transistor 21 has four channel regions.

[0159] From the above, combined with Figure 15 、 Figure 16 as well as Figure 23-Figure 25As shown, the display panel includes a plurality of pixel circuits, each pixel circuit including a driving transistor T3, a first light-emitting control transistor T1, and a second light-emitting control transistor T6. The first light-emitting control transistor T1 is electrically connected between a first power supply voltage line PVDD and the driving transistor T3, and the second light-emitting control transistor T6 is electrically connected between the driving transistor T3 and the light-emitting element 30. At least one of the driving transistor T3, the first light-emitting control transistor T1, and the second light-emitting control transistor T6 may be an oxide thin film transistor 20. Furthermore, the driving circuit VSR (scanning driving modules ScanA, ScanB and / or light-emitting control driving module Emit) ) includes a shift register circuit with a multi-stage cascade arrangement, the shift register circuit including a first output transistor and a second output transistor, the first output transistor being electrically connected between a first level signal line and an output end of the shift register circuit, and the second output transistor being electrically connected between a second level signal line and an output end of the shift register circuit; at least one of the first output transistor and the second output transistor is an oxide thin film transistor 20; on this basis, considering that the thin film transistors on the output path of the shift register circuit in the driving circuit VSR require a higher output current than the thin film transistors on the driving path of the pixel circuit pixel, therefore, optionally, in some embodiments of the present application, combined with Figures 26-31 As shown, at least one of the first output transistor and the second output transistor of the shift register circuit in the driving circuit VSR can be set to the first oxide thin film transistor 21 to meet the higher output current requirements of the first output transistor and the second output transistor of the shift register circuit in the driving circuit VSR, and at least one of the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 in the pixel circuit pixel can be set to the second oxide thin film transistor 22 to meet the high output current requirements of the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 in the pixel circuit pixel.

[0160] Figure 32 Another schematic top view of the display panel provided in the embodiment of the present application is shown in FIG. Figure 31 As shown, the display panel includes a plurality of light emitting elements 30, combined with Figure 16As shown, the pixel circuit pixel and the light-emitting element 30 are electrically connected in a one-to-one correspondence, driving the light-emitting element 30 to emit light for display. The pixel circuit pixel and the light-emitting element 30 constitute a sub-pixel 50. That is, the display panel includes a plurality of sub-pixels 50, and the sub-pixel includes the pixel circuit pixel and the light-emitting element 30. Specifically, the pixel circuit pixel includes a driving transistor T3, a first light-emitting control transistor T1, and a second light-emitting control transistor T6. The first light-emitting control transistor T1 is electrically connected between the first power supply voltage line PVDD and the driving transistor T3, and the second light-emitting control transistor T6 is electrically connected between the driving transistor T3 and the light-emitting element 30.

[0161] Considering that the driving currents required by the light emitting elements 30 in the sub-pixels 50 of different colors are inconsistent, optionally, in some embodiments of the present application, for example Figure 32 As shown, the plurality of sub-pixels 50 of the display panel include a first sub-pixel 51 and a second sub-pixel 52, the first sub-pixel 51 includes a first pixel circuit and a first light-emitting element 31, the second sub-pixel 52 includes a second pixel circuit and a second light-emitting element 32, and the first light-emitting element 31 and the second light-emitting element 32 emit different colors; on this basis, combined with Figures 26-31 As shown, in the first pixel circuit, at least one of the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 can be set as the first oxide thin film transistor 21 to meet the higher driving current requirement of the first light-emitting element 31, and in the second pixel circuit, at least one of the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 can be set as the second oxide thin film transistor 22 to meet the high driving current requirement of the second light-emitting element 32, thereby improving the display brightness uniformity of the display panel.

[0162] Further optionally, the first light-emitting element 31 can be a red light-emitting element, and the second light-emitting element 32 can be a green light-emitting element or a blue light-emitting element. This is because the red light-emitting element requires a higher driving current than the green light-emitting element and the blue light-emitting element. Therefore, at least one of the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 in the pixel circuit corresponding to the red light-emitting element can be set to be an oxide thin film transistor with a larger number of channel regions.

[0163] For example, Figure 32As shown, the multiple sub-pixels 50 of the display panel include a first sub-pixel 51, a second sub-pixel 52 and a third sub-pixel 53. The first sub-pixel 51 includes a first pixel circuit and a first light-emitting element 31, the second sub-pixel 52 includes a second pixel circuit and a second light-emitting element 32, and the third sub-pixel 53 includes a third pixel circuit and a third light-emitting element 33. The first light-emitting element 31 can be a red light-emitting element, the second light-emitting element 32 can be a green light-emitting element, and the third light-emitting element 33 can be a red light-emitting element. In the first pixel circuit, at least one of the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 is a first oxide thin film transistor 21, which meets the higher driving current requirement of the red light-emitting element; in the second pixel circuit and the third pixel circuit, at least one of the driving transistor T3, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 is a second oxide thin film transistor 22, which meets the high driving current requirement of the green light-emitting element and the blue light-emitting element.

[0164] Figure 33 Another schematic top view of the display panel provided in the embodiment of the present application is shown in FIG. Figure 33 As shown, the display panel includes a display area AA and a non-display area NA that at least partially surrounds the display area AA. The non-display area NA includes a bending area BA located on one side of the display area AA, and a pin area PA located on a side of the bending area BA away from the display area AA. The pin area PA is bound and connected to a driver integrated circuit IC.

[0165] It can be understood that the display panel can be bent at the bending area BA, so that the pin area PA is bent to the back side of the display panel.

[0166] It is also understandable that, combined with Figure 33 、 Figure 32 、 Figure 15 and Figure 16 As shown, the display area AA includes a plurality of sub-pixels 50, the sub-pixel 50 includes a pixel circuit pixel and a light-emitting element 30, the pixel circuit pixel includes a driving transistor T3, a first light-emitting control transistor T1 and a second light-emitting control transistor T6, the first light-emitting control transistor T1 is electrically connected between the first power supply voltage line PVDD and the driving transistor T3, and the second light-emitting control transistor T6 is electrically connected between the driving transistor T3 and the light-emitting element 30.

[0167] like Figure 33As shown, the display area AA includes a first display area AA1 and a second display area AA2, and the second display area AA2 is located on a side of the first display area AA1 away from the pin area PA; considering that the second display area AA2 is farther away from the pin area PA than the first display area AA1, then, due to the IR drop of the signal line, the brightness of the light-emitting element 30 in the second display area AA2 will be lower than that of the light-emitting element 30 in the first display area AA1.

[0168] Therefore, optionally, in some embodiments of the present application, at least one of the driving transistor T3, the first light-emitting control transistor T1, and the second light-emitting control transistor T6 of the pixel circuit pixel in the second display area AA2 can be set to be a first oxide thin film transistor 21 to further improve the driving current of the pixel circuit pixel to the light-emitting element 30 in the second display area AA2, and at least one of the driving transistor T3, the first light-emitting control transistor T1, and the second light-emitting control transistor T6 of the pixel circuit pixel in the first display area AA1 can be set to be a second oxide thin film transistor 22 to improve the driving current of the pixel circuit pixel to the light-emitting element 30 in the first display area AA1, thereby improving the display brightness uniformity of the display panel.

[0169] Accordingly, the embodiment of the present application further provides a display device, such as Figure 34 As shown, the display device 200 includes the above-mentioned display panel 100. Since the display panel 100 has been described in detail in the above-mentioned embodiments, it will not be repeated here.

[0170] The display device 200 can be any electronic device with a display function, such as a touch screen display, a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television.

[0171] The various parts in this manual are described in a combination of parallel and progressive manners. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0172] With respect to the above description of the disclosed embodiments, the features described in the various embodiments in this specification may be interchanged or combined with one another to enable those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: substrate; an oxide thin film transistor located on one side of the substrate, the oxide thin film transistor comprising a first oxide layer and a second oxide layer located on a side of the first oxide layer facing away from the substrate, the oxide thin film transistor comprising a source electrode and a drain electrode, the source electrode being electrically connected to the drain electrode through the first oxide layer, and the source electrode being further electrically connected to the drain electrode through the second oxide layer; The first oxide layer and the second oxide layer both include oxygen, narrow bandgap elements and wide bandgap elements, and the molar fraction of the narrow bandgap elements in the first oxide layer is greater than the molar fraction of the narrow bandgap elements in the second oxide layer.

2. The display panel according to claim 1, wherein: The first oxide layer and the second oxide layer are both indium gallium zinc oxide layers, and the mole fraction of indium in the first oxide layer is greater than the mole fraction of indium in the second oxide layer.

3. The display panel according to claim 1, wherein: The thickness of the first oxide layer is smaller than the thickness of the second oxide layer.

4. The display panel according to claim 1, wherein: The oxide thin film transistor includes an oxide semiconductor layer, which includes one of the first oxide layer and the second oxide layer; the oxide thin film transistor includes a gate electrode corresponding to the oxide semiconductor layer, and a gate insulating layer located between the oxide semiconductor layer and the corresponding gate electrode.

5. The display panel according to claim 4, wherein: The oxide semiconductor layer includes a first sublayer and a second sublayer, and in a direction perpendicular to the plane of the substrate, the second sublayer is located on a side of the first sublayer away from the corresponding gate electrode; wherein, The molar fraction of the narrow bandgap element in the first sublayer is greater than the molar fraction of the narrow bandgap element in the second sublayer, and the thickness of the first sublayer is less than the thickness of the second sublayer.

6. The display panel according to claim 5, wherein: The oxide semiconductor layer is correspondingly provided with two gate electrodes, and the oxide semiconductor layer is located between the corresponding two gate electrodes; The oxide semiconductor layer includes the first sublayer, the second sublayer, and the first sublayer stacked in a direction away from the substrate.

7. The display panel according to claim 1, wherein: The first oxide layer and the second oxide layer are both provided with gate electrodes, a gate insulating layer is provided between the first oxide layer and the corresponding gate electrode, and a gate insulating layer is also provided between the second oxide layer and the corresponding gate electrode; wherein, The thickness of at least one gate insulating layer corresponding to the second oxide layer is smaller than the thickness of at least one gate insulating layer corresponding to the first oxide layer; And / or, the dielectric constant of at least one gate insulating layer corresponding to the second oxide layer is greater than the dielectric constant of at least one gate insulating layer corresponding to the first oxide layer.

8. The display panel according to claim 1, wherein: The oxide thin film transistor includes a common gate electrode located between the first oxide layer and the second oxide layer.

9. The display panel according to claim 8, wherein: The oxide thin film transistor further includes a first gate electrode and / or a second gate electrode. The first gate electrode is located on a side of the first oxide layer close to the substrate, and the second gate electrode is located on a side of the second oxide layer away from the substrate.

10. The display panel according to claim 1, wherein The length of the channel region of the first oxide layer is greater than the length of the channel region of the second oxide layer; And / or, the width of the channel region of the first oxide layer is greater than the width of the channel region of the second oxide layer.

11. The display panel according to claim 10, wherein: The orthographic projection of the channel region of the second oxide layer on the plane where the substrate is located is located within the orthographic projection of the channel region of the first oxide layer on the plane where the substrate is located.

12. The display panel according to claim 1, wherein The source electrode and the drain electrode are located on the side of the second oxide layer facing away from the substrate, the source electrode is electrically connected to the first oxide layer through a first via, the drain electrode is electrically connected to the first oxide layer through a second via, the source electrode is directly overlapped with the second oxide layer, and the drain electrode is directly overlapped with the second oxide layer.

13. The display panel according to claim 1, wherein An etch stop layer is provided on the side of the second oxide layer facing away from the substrate, the source electrode and the drain electrode are located on the side of the etch stop layer facing away from the substrate, the source electrode is electrically connected to the first oxide layer through a first via hole, the drain electrode is electrically connected to the first oxide layer through a second via hole, the source electrode is also electrically connected to the second oxide layer through a third via hole penetrating the etch stop layer, and the drain electrode is also electrically connected to the second oxide layer through a fourth via hole penetrating the etch stop layer.

14. The display panel according to claim 1, wherein The display panel includes a plurality of pixel circuits, each of which includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. The first light-emitting control transistor is electrically connected between a first power supply voltage line and the driving transistor, and the second light-emitting control transistor is electrically connected between the driving transistor and the light-emitting element. At least one of the driving transistor, the first light-emitting control transistor, and the second light-emitting control transistor is the oxide thin film transistor.

15. The display panel according to claim 1, wherein The display panel includes a driving circuit, which includes a multi-stage cascaded shift register circuit. The shift register circuit includes a first output transistor and a second output transistor. The first output transistor is electrically connected between a first level signal line and an output end of the shift register circuit, and the second output transistor is electrically connected between a second level signal line and an output end of the shift register circuit. At least one of the first output transistor and the second output transistor is the oxide thin film transistor.

16. The display panel according to claim 1, wherein The oxide thin film transistor includes a first oxide thin film transistor and a second oxide thin film transistor, and the number of channel regions of the first oxide thin film transistor is greater than the number of channel regions of the second oxide thin film transistor.

17. The display panel according to claim 16, wherein: The display panel includes a plurality of pixel circuits, each pixel circuit including a driving transistor, a first emission control transistor, and a second emission control transistor, wherein the first emission control transistor is electrically connected between a first power supply voltage line and the driving transistor, and the second emission control transistor is electrically connected between the driving transistor and a light-emitting element; at least one of the driving transistor, the first emission control transistor, and the second emission control transistor is the second oxide thin film transistor; The display panel includes a driving circuit, which includes a multi-stage cascaded shift register circuit. The shift register circuit includes a first output transistor and a second output transistor. The first output transistor is electrically connected between a first level signal line and an output end of the shift register circuit, and the second output transistor is electrically connected between a second level signal line and an output end of the shift register circuit. At least one of the first output transistor and the second output transistor is the first oxide thin film transistor.

18. The display panel according to claim 16, wherein: The display panel includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor, the first light-emitting control transistor is electrically connected between a first power supply voltage line and the driving transistor, and the second light-emitting control transistor is electrically connected between the driving transistor and the light-emitting element; The plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel includes a first pixel circuit and a first light-emitting element, the second sub-pixel includes a second pixel circuit and a second light-emitting element, and the first light-emitting element and the second light-emitting element emit light of different colors; In the first pixel circuit, at least one of the driving transistor, the first light emission control transistor, and the second light emission control transistor is the first oxide thin film transistor; In the second pixel circuit, at least one of the driving transistor, the first light emission control transistor, and the second light emission control transistor is the second oxide thin film transistor.

19. The display panel according to claim 18, wherein: The first light-emitting element is a red light-emitting element, and the second light-emitting element is a green light-emitting element or a blue light-emitting element.

20. The display panel according to claim 16, wherein The display panel includes a display area and a non-display area at least partially surrounding the display area, the non-display area includes a bending area located on one side of the display area, and a pin area located on a side of the bending area away from the display area, the pin area being bound and connected to a driver integrated circuit; The display area includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor, the first light-emitting control transistor is electrically connected between a first power supply voltage line and the driving transistor, and the second light-emitting control transistor is electrically connected between the driving transistor and the light-emitting element; The display area includes a first display area and a second display area, wherein the second display area is located on a side of the first display area away from the pin area; In the second display area, at least one of the driving transistor, the first light emission control transistor, and the second light emission control transistor of the pixel circuit is the first oxide thin film transistor; In the first display area, at least one of the driving transistor, the first light emission control transistor, and the second light emission control transistor of the pixel circuit is the second oxide thin film transistor.

21. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 20.

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