Gallium nitride CMOS (complementary metal oxide semiconductor) and miniature LED (light-emitting diode) single chip integration preparation method and product

Abstract

The invention relates to a gallium nitride CMOS (complementary metal oxide semiconductor) and miniature LED (light-emitting diode) single chip integrated preparation method and product, and the method comprises the steps: carrying out the epitaxial growth of micro-LED epitaxy on a commercial mature p-type gallium nitride gate high-electron mobility transistor epitaxy through selective region epitaxy, and preparing an enhanced n-channel HEMT, a p-channel field-effect transistor, a micro-LED single chip, a micro-LED single chip and a micro-LED single chip on a substrate of the p-type gate HEMT, constructing a gallium nitride CMOS circuit for digital control; and furthermore, interconnection with a selective area epitaxial micro-LED device is carried out, so that digital control of the micro-LED on the full-gallium nitride integrated chip can be realized, and the integration level and reliability of the digital control circuit and the micro-LED are effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of gallium nitride micro-LED processing technology, and more specifically, to a preparation method and product of a gallium nitride CMOS and micro-LED single-chip integration. Background Art

[0002] Gallium nitride micro-LEDs (micro-LEDs) are widely used in display, visible light communication, and optogenetics. In these application scenarios, digital control of micro-LEDs is required.

[0003] Traditional micro-LED digital control mostly uses silicon-based CMOS (complementary metal oxide semiconductor) circuits, which require interconnecting the control circuit and micro-LED through heterogeneous integration methods such as bonding. With the emergence of high-pixel density application scenarios, the size of micro-LEDs has shrunk to below 2 microns. Heterogeneous integration faces challenges in reliability, integration and speed.

[0004] The ideal solution is to integrate GaN-based transistors and micro-LEDs into a single chip. However, the current solution is still limited to the integration of a single transistor and a micro-LED, and the digital control function cannot be realized. A preparation method for the single-chip integration of GaN-based transistors and micro-LEDs is needed. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a preparation method for integrating gallium nitride CMOS and micro LED single chips in response to the above-mentioned defects of the prior art, and also provide a product of gallium nitride CMOS and micro LED single chip integration manufactured by this method.

[0006] The technical solution adopted by the present invention to solve its technical problem is:

[0007] A method for preparing a gallium nitride CMOS and micro LED single chip integration is constructed, which includes the following steps:

[0008] A growth mask is deposited on the surface of the p-GaN gate HEMT substrate;

[0009] Patterning the growth mask and p-GaN gate HEMT substrate to expose the area where micro-LED selective epitaxy is required;

[0010] Conduct selective epitaxial growth of micro-LEDs;

[0011] removing the growth mask;

[0012] Perform mesa etching on HEMT devices to achieve electrical isolation of p-GaN gate enhancement mode HEMTs, p-channel FETs, and micro-LED devices;

[0013] Performing a mesa etching process on the micro-LED device to form a mesa of the micro-LED device;

[0014] Patterning the p-GaN gate of the N-channel HEMT, retaining the p-GaN at the gate location of the enhancement-mode HEMT, and etching away the p-GaN in other areas of the HEMT to form a p-GaN epitaxial layer below the gate of the enhancement-mode n-channel HEMT;

[0015] Etching the p-GaN at the gate of the p-FET to a thickness of 5-10 nanometers, and directly forming an enhanced-mode p-channel field-effect transistor using the p-GaN epitaxial layer;

[0016] Making ohmic contacts between the source and drain of the n-channel HEMT;

[0017] Depositing a dielectric layer and patterning it to form the gate dielectric of the p-FET, the sidewall passivation layer of the micro-LED, and the surface passivation layer of the n-channel HEMT;

[0018] Forming source and drain contacts for p-channel field-effect transistors and ohmic contacts for micro-LED p-GaN;

[0019] Deposit the p-channel transistor gate and the interconnect metal of the entire chip to complete the interconnection of the p-GaN gate enhancement mode n-channel HEMT, enhancement mode p-channel FET and micro-LED.

[0020] In the method for preparing a single-chip integrated GaN CMOS and micro-LED according to the present invention, the patterned growth mask and the p-GaN gate HEMT substrate expose areas where micro-LED selective epitaxy is required, including:

[0021] Spin-coat the photoresist, perform UV exposure with a mask, and then develop and remove the photoresist in the exposed areas;

[0022] Dry etching is performed using inductively coupled plasma. The etching depth includes the thickness of the mask and the depth of the HEMT. The thickness of the mask is not less than 500nm, and the etching depth of the HEMT substrate is between 200nm and 300nm.

[0023] The etching stops on the unintentionally doped GaN buffer layer, exposing the area where selective epitaxy is required.

[0024] The method for preparing a gallium nitride CMOS and micro-LED single-chip integration of the present invention, wherein the selective epitaxial growth of the micro-LED comprises:

[0025] The p-GaN gate HEMT substrate is placed into the reaction chamber of the metal organic chemical vapor deposition equipment for selective epitaxial growth of micro-LEDs;

[0026] The LED structure of selective area epitaxy mainly includes n-type doped gallium nitride layer, indium gallium nitride / gallium nitride multi-quantum well layer and p-type gallium nitride layer from bottom to top.

[0027] In the method for preparing a single-chip integrated gallium nitride CMOS and micro-LED device according to the present invention, the step of performing mesa etching on the HEMT device to achieve electrical isolation of the p-GaN gate enhancement mode HEMT, the p-channel FET, and the micro-LED device comprises:

[0028] Spin-coat photoresist, perform UV exposure with a mask, develop and remove the photoresist in the exposed area, and perform etching using inductively coupled plasma. The etching stays on the unintentionally doped gallium nitride buffer layer, electrically isolating the p-GaN gate enhancement mode HEMT, p-channel FET, and micro-LED devices.

[0029] The method for preparing a single-chip integrated gallium nitride CMOS and micro-LED according to the present invention, wherein the etching of the p-GaN at the gate position of the p-FET to retain a thickness of 5-10 nanometers and directly forming an enhancement mode p-channel field effect transistor using the p-GaN epitaxial layer includes:

[0030] The photoresist is spin-coated, and the photoresist in the exposed area is developed and removed through UV exposure lithography with a mask. Etching is performed using inductively coupled plasma, leaving only the p-GaN at the gate position of the p-FET with a thickness of 5-10 nanometers. The enhanced p-channel field-effect transistor is directly formed using the p-GaN epitaxial layer.

[0031] In the method for preparing the integrated GaN CMOS and micro LED single chip of the present invention, the step of making ohmic contact between the source and drain of the n-channel HEMT comprises:

[0032] Spin-coat the photoresist, perform UV exposure with a mask, and then develop and remove the photoresist in the exposed areas;

[0033] Ti / Al / Ti / Au was deposited by electron beam evaporation or thermal evaporation, with thicknesses of Ti, Al, Ti, and Au of 20 nm, 100 nm, 40 nm, and 60 nm, respectively;

[0034] Metal stripping in acetone to remove the photoresist and metal in the unexposed areas;

[0035] A rapid annealing process was performed at 850°C for 30 seconds in a nitrogen atmosphere to form drain and source contacts of the enhancement mode n-channel HEMT.

[0036] The method for preparing a single-chip integrated GaN CMOS and micro-LED according to the present invention includes depositing a dielectric layer and performing patterning to form a gate dielectric of a p-FET, a sidewall passivation layer of a micro-LED, and a surface passivation layer of an n-channel HEMT, including:

[0037] Aluminum oxide is deposited by atomic layer deposition to a thickness of 20 nanometers, covering the entire substrate surface;

[0038] The photoresist is spin-coated, and the photoresist in the exposed area is developed and removed through UV exposure lithography with a mask. The photoresist is then etched through inductively coupled plasma to form the gate dielectric of the p-FET, the sidewall passivation layer of the micro-LED, and the surface passivation layer of the n-channel HEMT.

[0039] The method for preparing the integrated GaN CMOS and micro-LED single chip of the present invention, wherein the forming of the source-drain contacts of the p-channel field effect transistor and the ohmic contacts of the micro-LED p-GaN comprises:

[0040] Spin-coat photoresist, perform UV exposure with a mask, develop and remove the photoresist in the exposed area, and deposit Ni / Au by electron beam evaporation or thermal evaporation, with Ni and Au thicknesses of 7 nm each;

[0041] Metal stripping is performed in acetone to remove the photoresist and metal in the unexposed areas, and a rapid annealing process is performed in air at a temperature of 550°C for 2 minutes to simultaneously form the source and drain contacts of the p-channel field-effect transistor and the ohmic contacts of the micro-LED p-GaN.

[0042] The method for preparing a single-chip integrated GaN CMOS and micro-LED according to the present invention includes depositing the p-channel transistor gate and the interconnection metal of the entire chip to complete the interconnection and integration of the p-GaN gate enhancement mode n-channel HEMT, the enhancement mode p-channel FET, and the micro-LED, including:

[0043] Spin-coat photoresist, perform masked UV exposure lithography, develop and remove the photoresist in the exposed area, and deposit Ti / Al / Ti / Au by electron beam evaporation or thermal evaporation, with Ti, Al, Ti, and Au having thicknesses of 40 nm, 100 nm, 50 nm, and 60 nm, respectively;

[0044] Metal stripping is performed in acetone to remove the photoresist and metal in the unexposed areas, enabling interconnection between the p-GaN gate-enhanced n-channel HEMT, p-channel FET, and micro-LED.

[0045] A product integrating a gallium nitride CMOS and a micro LED single chip, wherein the product is manufactured according to the above-mentioned preparation method for integrating a gallium nitride CMOS and a micro LED single chip.

[0046] The beneficial effects of the present invention are as follows: the preparation method of the present application for the integration of a gallium nitride CMOS and micro-LED single chip selectively grows micro-LED epitaxy on a commercially mature p-type gallium nitride gate high electron mobility transistor epitaxy. By fabricating an enhancement-mode n-channel HEMT and a p-channel field-effect transistor on a p-type gate HEMT substrate, a gallium nitride CMOS circuit for digital control is constructed. Further interconnection with the selectively grown micro-LED device enables digital control of the micro-LED on a full gallium nitride integrated chip, effectively improving the integration and reliability of the digital control circuit and the micro-LED. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be further described below with reference to the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts.

[0048] Figure 1 This is a flow chart of a method for preparing a single-chip integration of gallium nitride CMOS and micro LEDs according to a preferred embodiment of the present invention;

[0049] Figure 2 This is a cross-sectional view of the substrate structure in the initial state of the preparation method for the integration of a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0050] Figure 3 2. This is a cross-sectional view of the substrate structure after executing step 1 of the preparation method for integrating a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0051] Figure 4 This is a cross-sectional view of the substrate structure after executing step 2 of the preparation method for integrating a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0052] Figure 5 2. This is a cross-sectional view of the substrate structure after executing step 3 of the preparation method for integrating a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0053] Figure 6 2. This is a cross-sectional view of the substrate structure after executing step 4 of the preparation method for integrating a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0054] Figure 7 2. This is a cross-sectional view of the substrate structure after executing step five of the preparation method for integrating a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0055] Figure 8 2. This is a cross-sectional view of the substrate structure after executing step 6 of the preparation method for integrating a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0056] Figure 9 2. This is a cross-sectional view of the substrate structure after executing step seven of the preparation method for integrating a gallium nitride CMOS and micro LED single chip according to a preferred embodiment of the present invention;

[0057] Figure 10 2. This is a cross-sectional view of the substrate structure after executing step eight of the method for preparing a gallium nitride CMOS and micro LED single chip integrated circuit according to a preferred embodiment of the present invention;

[0058] Figure 11 2. This is a cross-sectional view of the substrate structure after executing step nine of the method for preparing the gallium nitride CMOS and micro LED single chip integration according to a preferred embodiment of the present invention;

[0059] Figure 12 2. This is a cross-sectional view of the substrate structure after executing step 10 of the method for preparing the gallium nitride CMOS and micro LED single chip integration according to a preferred embodiment of the present invention;

[0060] Figure 13 2. This is a cross-sectional view of the substrate structure after executing step 11 of the method for preparing a single-chip integration of gallium nitride CMOS and micro LEDs according to a preferred embodiment of the present invention;

[0061] Figure 14 FIG. 1 is a cross-sectional view of the substrate structure after executing step 12 of the method for preparing the gallium nitride CMOS and micro LED single chip integration according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0062] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the following will be a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work shall fall within the scope of protection of the present invention.

[0063] The preparation method of the integrated GaN CMOS and micro LED single chip in the preferred embodiment of the present invention is as follows: Figure 1 See also Figure 2-Figure 14 , including the following steps:

[0064] S01: Covering the surface of the p-GaN gate HEMT substrate with a deposition growth mask;

[0065] like Figure 2 and Figure 3 As shown;

[0066] The epitaxial structure of the p-GaN gate HEMT substrate (from bottom to top) includes: substrate 100, unintentionally doped buffer layer 101, GaN channel layer 102, AlGaN barrier layer 103, and p-type doped GaN layer 104.

[0067] After the p-GaN gate HEMT substrate sample is initially cleaned, silicon dioxide (SiO2) is evaporated by plasma enhanced chemical vapor deposition (PECVD) to a thickness of approximately 500 nanometers, covering the entire sample surface to form a growth mask 105;

[0068] It should be noted that the selective epitaxial growth mask can be SiO2, Si3N4 deposited by PECVD, or metal titanium (Ti) or tungsten (W) formed by sputtering;

[0069] S02: Patterning the growth mask and p-GaN gate HEMT substrate to expose the area where micro-LED selective epitaxy is required;

[0070] This step refers to Figure 4 Specifically, the process can be implemented by spin-coating photoresist, performing masked UV exposure lithography, developing and removing the photoresist in the exposed areas, and performing dry etching using inductively coupled plasma (ICP) to a depth of approximately 800 nanometers (including the thickness of the SiO2 mask and the depth of the HEMT, with the mask thickness being no less than 500 nanometers and the etching depth of the HEMT substrate being between 200 nanometers and 300 nanometers). The etching stops on the unintentionally doped GaN buffer layer, exposing the area where selective epitaxy is required.

[0071] S03: Perform selective epitaxial growth of micro-LEDs;

[0072] This step refers to Figure 5 , the specific implementation can be:

[0073] The sample was placed into the reaction chamber of a metal-organic chemical vapor deposition (MOCVD) device for selective epitaxial growth of micro-LEDs. The structure of the selective epitaxially grown LED, from bottom to top, primarily consists of an n-type doped GaN layer 200, an InGaN / GaN multi-quantum well layer 201, and a p-type GaN layer 202.

[0074] S04: removing the growth mask;

[0075] This step refers to Figure 6 , taking silicon dioxide growth mask as an example, the specific implementation can be:

[0076] By wet etching (the etching solution is BOE, buffer oxide etchant), the silicon dioxide growth mask in the exposed area is fully removed;

[0077] S05: Perform mesa etching on the HEMT device to achieve electrical isolation of the p-GaN gate enhancement mode HEMT, p-channel FET and micro-LED devices;

[0078] This step refers to Figure 7 , the specific implementation can be:

[0079] Spin-coat photoresist, develop and remove the photoresist in the exposed areas through masked UV exposure lithography, and etch using inductively coupled plasma (ICP) to a depth of approximately 380 nanometers, stopping at the unintentionally doped gallium nitride buffer layer to electrically isolate the p-GaN gate enhancement mode HEMT, p-channel FET, and micro-LED devices;

[0080] Mesa etching can also be done by fluoride ions (F - ) injection method for electrical insulation of the device;

[0081] S06: performing a mesa etching process on the micro-LED device to form a mesa of the micro-LED device;

[0082] This step refers to Figure 8 , the specific implementation can be:

[0083] Spin-coat the photoresist, perform UV exposure with a mask, develop and remove the photoresist in the exposed area, and etch using inductively coupled plasma (ICP). The etching depth depends on the thickness of the p-type GaN and multi-quantum wells in the micro-LED epitaxy. The etching needs to stop on the n-type GaN to form the mesa of the micro-LED device.

[0084] S07: Patterning the gate p-GaN of the N-channel HEMT, retaining the p-GaN at the gate position of the enhancement-mode HEMT, etching away the p-GaN in other areas of the HEMT, and forming a p-GaN epitaxial layer under the gate of the enhancement-mode n-channel HEMT;

[0085] This step refers to Figure 9 , the specific implementation can be:

[0086] Spin-coating photoresist, performing UV exposure lithography with a mask, developing and removing the photoresist in the exposed areas, and etching using inductively coupled plasma (ICP) to retain only the p-GaN at the gate location of the enhancement-mode HEMT and to etch away the p-GaN in other areas of the HEMT to a depth determined by the thickness of the p-type gallium nitride in the HEMT epitaxial layer (approximately 70 nanometers), thereby forming a p-GaN epitaxial layer below the gate of the enhancement-mode n-channel HEMT.

[0087] S08: Etching the p-GaN at the gate position of the p-FET to a thickness of 5-10 nanometers, and directly forming an enhancement mode p-channel field effect transistor using the p-GaN epitaxial layer;

[0088] This step refers to Figure 10 , the specific implementation can be:

[0089] Spin-coat the photoresist, perform UV exposure lithography with a mask, develop and remove the photoresist in the exposed area, and perform etching using inductively coupled plasma (ICP) to retain only a portion (5-10nm thick) of the p-GaN at the gate position of the p-FET, thereby directly forming an enhancement mode p-channel field effect transistor using the p-GaN epitaxial layer;

[0090] S09: forming ohmic contacts between the source and drain of the n-channel HEMT;

[0091] This step refers to Figure 11 , the specific implementation can be:

[0092] Spin-coat photoresist, develop and remove the exposed areas using masked UV lithography, deposit Ti / Al / Ti / Au (20 / 100 / 40 / 60 nm thickness) using electron beam evaporation or thermal evaporation, remove the photoresist and metal from the unexposed areas using metal lift-off in acetone, and perform rapid thermal annealing (RTA) at 850°C for 30 seconds in a nitrogen atmosphere to form drain and source contacts for the enhancement-mode n-channel HEMT.

[0093] S10: depositing a dielectric layer and performing patterning to form a gate dielectric of the p-FET, a sidewall passivation layer of the micro-LED, and a surface passivation layer of the n-channel HEMT;

[0094] This step refers to Figure 12 , the specific implementation can be:

[0095] Aluminum oxide (Al2O3) is deposited by atomic layer deposition (ALD) to a thickness of approximately 20 nanometers, covering the entire sample surface. A photoresist is then spin-coated, and the exposed areas are developed and removed using masked UV lithography. Etching is then performed using inductively coupled plasma (ICP) to form the gate dielectric 300 of the p-FET, the sidewall passivation layer 301 of the micro-LED, and the surface passivation layer 302 of the n-channel HEMT.

[0096] The ALD oxide deposition serves as both the gate dielectric layer for p-type FETs and the sidewall passivation layer for micro-LEDs and n-channel enhancement-mode HEMTs. It eliminates non-radiative recombination centers on the sidewalls created by etching the micro-LED mesa in step 6, ensuring the micro-LED's luminous efficiency; forms the gate dielectric layer for p-type FETs; and passivates the surface of discrete devices in preparation for depositing interconnect metals.

[0097] ALD oxide can be Al2O3 or other oxides such as HfO2;

[0098] S11: forming source and drain contacts of the p-channel field effect transistor and ohmic contacts of the micro-LED p-GaN;

[0099] This step refers to Figure 13 , the specific implementation can be:

[0100] Spin-coat photoresist, develop and remove the exposed areas using masked UV lithography, deposit Ni / Au (7 / 7nm thick) using electron beam evaporation or thermal evaporation, perform metal lift-off in acetone to remove the photoresist and metal in the unexposed areas, and perform rapid thermal annealing (RTA) in air at 550°C for 2 minutes to simultaneously form the source and drain contacts for the p-channel FET and the ohmic contacts for the p-GaN micro-LED.

[0101] The p-type transistor and micro-LED share the ohmic metal contact of Ni / Au, which simplifies the process steps and complexity and reduces costs;

[0102] S12: Deposit the gate of the p-channel transistor and the interconnect metal of the entire chip to complete the interconnection and integration of the p-GaN gate enhancement mode n-channel HEMT, enhancement mode p-channel FET and micro-LED;

[0103] This step refers to Figure 14 , the specific implementation can be:

[0104] Spin-coating photoresist is performed, and the exposed areas are developed and removed using masked UV lithography. Ti / Al / Ti / Au (thicknesses of 40 / 100 / 50 / 60 nm) are deposited using electron beam evaporation or thermal evaporation. Metal lift-off is performed in acetone to remove the photoresist and metal from the unexposed areas, thereby achieving interconnection and integration of the p-GaN gate enhancement mode n-channel HEMT 400, the p-channel FET 401, and the micro-LED 402.

[0105] The present invention discloses a method for fabricating a single-chip integrated GaN CMOS circuit and micro-LED. Micro-LED epitaxy is selectively grown on a commercially available p-type GaN gate high electron mobility transistor (HEMT) epitaxial layer. A GaN CMOS circuit for digital control is constructed by fabricating an enhancement-mode n-channel HEMT and a p-channel field-effect transistor (FET) on a p-type gate HEMT substrate. This circuit is then interconnected with the selectively grown micro-LED device to achieve digital control of the micro-LED on a fully GaN integrated chip, effectively improving the integration and reliability of the digital control circuit and micro-LED.

[0106] A product integrating a gallium nitride CMOS and a micro LED single chip is manufactured according to the above-mentioned preparation method for integrating a gallium nitride CMOS and a micro LED single chip.

[0107] Products manufactured using the preparation method of the gallium nitride CMOS circuit and micro-LED single-chip integration of the present application can realize digital control of micro-LEDs on a full gallium nitride integrated chip, effectively improving the integration and reliability of the digital control circuit and micro-LED.

[0108] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A method for preparing a gallium nitride CMOS and micro LED single chip integration, characterized in that: The following steps are involved: A growth mask is deposited on the surface of the p-GaN gate HEMT substrate; Patterning the growth mask and p-GaN gate HEMT substrate to expose the area where micro-LED selective epitaxy is required; Conduct selective epitaxial growth of micro-LEDs; removing the growth mask; Perform mesa etching on HEMT devices to achieve electrical isolation of p-GaN gate enhancement mode HEMTs, p-channel FETs, and micro-LED devices; Performing a mesa etching process on the micro-LED device to form a mesa of the micro-LED device; Patterning the p-GaN gate of the N-channel HEMT, retaining the p-GaN at the gate location of the enhancement-mode HEMT, and etching away the p-GaN in other areas of the HEMT to form a p-GaN epitaxial layer below the gate of the enhancement-mode n-channel HEMT; Etching the p-GaN at the gate of the p-FET to a thickness of 5-10 nanometers, and directly forming an enhanced-mode p-channel field-effect transistor using the p-GaN epitaxial layer; Making ohmic contacts between the source and drain of the n-channel HEMT; Depositing a dielectric layer and patterning it to form the gate dielectric of the p-FET, the sidewall passivation layer of the micro-LED, and the surface passivation layer of the n-channel HEMT; Forming source and drain contacts for p-channel field-effect transistors and ohmic contacts for micro-LED p-GaN; Deposit the p-channel transistor gate and the interconnect metal of the entire chip to complete the interconnection of the p-GaN gate enhancement mode n-channel HEMT, enhancement mode p-channel FET and micro-LED.

2. The method for preparing a gallium nitride CMOS and micro LED single chip integration according to claim 1, characterized in that: The patterned growth mask and p-GaN gate HEMT substrate expose areas where micro-LED selective epitaxy is required, including: Spin-coat the photoresist, perform UV exposure with a mask, and then develop and remove the photoresist in the exposed areas; Dry etching is performed using inductively coupled plasma. The etching depth includes the thickness of the mask and the depth of the HEMT substrate. The thickness of the mask is not less than 500nm, and the etching depth of the HEMT substrate is between 200nm and 300nm. The etching stops on the unintentionally doped GaN buffer layer, exposing the area where selective epitaxy is required.

3. The method for preparing a single-chip integrated GaN CMOS and micro LED according to claim 1, characterized in that: The selective epitaxial growth of micro-LEDs includes: The p-GaN gate HEMT substrate is placed into the reaction chamber of the metal organic chemical vapor deposition equipment for selective epitaxial growth of micro-LEDs; The LED structure of selective area epitaxy includes an n-type doped gallium nitride layer, an indium gallium nitride / gallium nitride multi-quantum well layer and a p-type gallium nitride layer from bottom to top.

4. The method for preparing a gallium nitride CMOS and micro LED single chip integration according to claim 1, characterized in that: The mesa etching process is performed on the HEMT device to achieve electrical isolation of the p-GaN gate enhancement mode HEMT, the p-channel FET and the micro-LED device, including: Spin-coat photoresist, develop and remove the photoresist in the exposed area through masked UV exposure lithography, and etch using inductively coupled plasma, stopping at the unintentionally doped gallium nitride buffer layer to electrically isolate the p-GaN gate enhancement mode HEMT, p-channel FET and micro-LED devices.

5. The method for preparing a gallium nitride CMOS and micro LED single chip integration according to claim 1, characterized in that: The etching of the p-GaN at the gate position of the p-FET to retain a thickness of 5-10 nanometers and directly forming an enhanced-mode p-channel field-effect transistor using the p-GaN epitaxial layer includes: The photoresist is spin-coated, and the photoresist in the exposed area is developed and removed through UV exposure lithography with a mask. Etching is performed using inductively coupled plasma, leaving only the p-GaN at the gate position of the p-FET with a thickness of 5-10 nanometers. The enhanced p-channel field-effect transistor is directly formed using the p-GaN epitaxial layer.

6. The method for preparing a gallium nitride CMOS and micro LED single chip integration according to claim 1, characterized in that: The step of forming ohmic contacts between the source and the drain of the n-channel HEMT comprises: Spin-coat the photoresist, perform UV exposure with a mask, and then develop and remove the photoresist in the exposed areas; Ti / Al / Ti / Au was deposited by electron beam evaporation or thermal evaporation, with thicknesses of Ti, Al, Ti, and Au of 20 nm, 100 nm, 40 nm, and 60 nm, respectively; Metal stripping in acetone to remove the photoresist and metal in the unexposed areas; A rapid annealing process was performed at 850°C for 30 seconds in a nitrogen atmosphere to form drain and source contacts of the enhancement mode n-channel HEMT.

7. The method for preparing a gallium nitride CMOS and micro LED single chip integration according to claim 1, characterized in that: The process of depositing a dielectric layer and patterning the dielectric layer to form a gate dielectric of a p-FET, a sidewall passivation layer of a micro-LED, and a surface passivation layer of an n-channel HEMT includes: Aluminum oxide is deposited by atomic layer deposition to a thickness of 20 nanometers, covering the entire substrate surface; The photoresist is spin-coated, and the photoresist in the exposed area is developed and removed through UV exposure lithography with a mask. The photoresist is then etched through inductively coupled plasma to form the gate dielectric of the p-FET, the sidewall passivation layer of the micro-LED, and the surface passivation layer of the n-channel HEMT.

8. The method for preparing a gallium nitride CMOS and micro LED single chip integration according to claim 1, characterized in that: The forming of the source-drain contacts of the p-channel field effect transistor and the ohmic contacts of the micro-LED p-GaN includes: Spin-coat photoresist, perform UV exposure with a mask, develop and remove the photoresist in the exposed area, and deposit Ni / Au by electron beam evaporation or thermal evaporation, with Ni and Au thicknesses of 7 nm each; Metal stripping is performed in acetone to remove the photoresist and metal in the unexposed areas, and a rapid annealing process is performed in air at a temperature of 550°C for 2 minutes to simultaneously form the source and drain contacts of the p-channel field-effect transistor and the ohmic contacts of the micro-LED p-GaN.

9. The method for preparing a gallium nitride CMOS and micro LED single chip integration according to claim 1, characterized in that: The process of depositing the p-channel transistor gate and the interconnect metal of the entire chip to complete the interconnection of the p-GaN gate enhancement mode n-channel HEMT, the enhancement mode p-channel FET and the micro-LED includes: Spin-coat photoresist, perform masked UV exposure lithography, develop and remove the photoresist in the exposed area, and deposit Ti / Al / Ti / Au by electron beam evaporation or thermal evaporation, with Ti, Al, Ti, and Au having thicknesses of 40 nm, 100 nm, 50 nm, and 60 nm, respectively; Metal stripping is performed in acetone to remove the photoresist and metal in the unexposed areas, enabling the interconnection and integration of p-GaN gate-enhanced n-channel HEMTs, p-channel FETs, and micro-LEDs.

10. A product integrating a gallium nitride CMOS and a micro LED single chip, characterized in that: The product is manufactured according to the preparation method for integrating gallium nitride CMOS and micro LED single chip according to any one of claims 1 to 9.

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