Photoelectric co-packaging structure and manufacturing method thereof

Abstract

The invention relates to a photoelectric co-packaging structure and a manufacturing method thereof. The photoelectric co-packaging structure comprises an optical integrated chip which comprises an optical element area and an electric chip area located outside the optical element area, and a built-in optical element is arranged in the optical element area; the electronic chip is mounted on the electric chip area on the front surface of the optical integrated chip, and the electronic chip is electrically connected with the optical integrated chip; the transparent block structure is mounted on the optical element area of the optical integrated chip, and the transparent block structure comprises a lower surface facing the optical integrated chip and an upper surface opposite to the lower surface in the first direction; and the plastic packaging layer is located on the front face of the optical integrated chip and used for packaging the electronic chip and the transparent block structure in a plastic mode, and the upper surface of the transparent block structure is exposed out of the plastic packaging layer. According to the invention, the built-in optical element is prevented from being polluted by the plastic package particles, and meanwhile, the controllability of the whole process is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an optoelectronic co-packaging structure and a manufacturing method thereof. Background Art

[0002] With the rapid development of big data models and AI technology this year, data-intensive networks have posed challenges to bandwidth density, communication latency, and power efficiency, driving the development of optoelectronic co-packaging technology. Optoelectronic co-packaging technology integrates silicon photonic modules and electronic chips using 2.5D or 3D advanced packaging technologies to form an optoelectronic co-packaging structure. The formation of this optoelectronic co-packaging structure can shorten the distance between the electronic chip and the silicon photonic module, thereby improving the efficiency of signal transmission between the electronic chip and the silicon photonic module.

[0003] In the process of forming the optoelectronic co-packaging structure through optoelectronic co-packaging technology, in order to integrate the optical element protection process and the plastic packaging process, a plastic sacrificial cover is generally used to cover the optical element before the plastic packaging process is implemented to protect the optical element. After the plastic packaging process is completed, the plastic sacrificial cover is removed to expose the optical element, and finally the optical path is connected by placing an inserted optical fiber array element. However, due to the poor controllability of the processing process of the plastic sacrificial cover, it eventually does not match the size of the inserted optical fiber array element, affecting the smooth implementation of the packaging process and the yield of the optoelectronic co-packaging structure. Moreover, the exposed packaging structure is susceptible to contamination by particles falling from the plastic packaging layer, which will also affect the transmission of the optical signal, and further affect the performance stability and reliability of the optoelectronic co-packaging structure.

[0004] Therefore, how to increase the process controllability during the manufacturing process of the optoelectronic co-packaging structure while preventing the optical components from being contaminated by plastic particles, thereby improving the performance stability and reliability of the optoelectronic co-packaging structure, is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides an optoelectronic co-packaging structure and a manufacturing method thereof, which are used to increase the process controllability during the manufacturing process of the optoelectronic co-packaging structure, while preventing optical components from being contaminated by plastic packaging particles, thereby improving the performance stability and reliability of the optoelectronic co-packaging structure.

[0006] According to some embodiments, the present invention provides an optoelectronic co-packaging structure, comprising:

[0007] An optical integrated chip comprising a front surface and a back surface that are oppositely distributed along a first direction, the optical integrated chip comprising an optical element region and an electrical chip region located outside the optical element region along a second direction, wherein a built-in optical element is disposed in the optical element region, and the second direction is parallel to the front surface of the optical integrated chip;

[0008] an electronic chip mounted on the electrical chip region on the front side of the optical integrated chip, and electrically connected to the optical integrated chip;

[0009] a transparent block structure mounted on the optical element region of the optical integrated chip, the transparent block structure comprising a lower surface facing the optical integrated chip and an upper surface opposite to the lower surface along the first direction;

[0010] A plastic sealing layer is located on the front surface of the optical integrated chip and plastic seals the electronic chip and the transparent block structure, and the plastic sealing layer exposes the upper surface of the transparent block structure.

[0011] In some embodiments, further comprising:

[0012] An external optical element is mounted on the upper surface of the transparent block structure.

[0013] In some embodiments, the external optical element is a laser array element.

[0014] In some embodiments, the transparent block structure is a hexahedral structure, and the light transmittance of the transparent block structure is above 90%.

[0015] In some embodiments, the material of the transparent block structure includes any one of silicon oxide, optical quartz, polymethyl methacrylate, and polystyrene, or a combination of two or more thereof.

[0016] In some embodiments, the roughness of the upper surface of the transparent bulk structure is below 100 nm.

[0017] In some embodiments, further comprising:

[0018] The bottom transparent connector structure is located on the front side of the optical integrated chip, and one end of the bottom transparent connector structure is connected to the optical integrated chip, and the other end is connected to the transparent block structure.

[0019] In some embodiments, further comprising:

[0020] A bottom support dam is connected to the optical integrated chip at one end and to the transparent block structure at the other end. The projection of the bottom support dam on the front surface of the optical integrated chip is distributed around the periphery of the optical element area.

[0021] In some embodiments, the bottom support dam is located inside the bottom transparent connector structure; or,

[0022] The bottom support dam covers the side surfaces of the bottom transparent connector structure.

[0023] In some embodiments, further comprising:

[0024] The top transparent connector structure is located on the upper surface of the transparent block structure, and one end of the top transparent connector structure is connected to the transparent block structure, and the other end is connected to the external optical element.

[0025] In some embodiments, further comprising:

[0026] A top support dam is located on the upper surface of the transparent block structure, and a projection of the top support dam on the upper surface of the transparent block structure is distributed around the periphery of a projection of the external optical element on the upper surface of the transparent block structure.

[0027] In some embodiments, a plurality of the electronic chips are arranged at intervals on the front surface of the optical integrated chip at least along the second direction;

[0028] At least one of the electronic chips is a control chip, and a surface of the control chip facing away from the optical integrated chip is flush with the upper surface of the transparent block structure.

[0029] According to other embodiments, the present invention further provides a method for manufacturing an optoelectronic co-packaging structure, comprising the following steps:

[0030] forming an optical integrated chip, the optical integrated chip comprising a front surface and a back surface opposite to each other along a first direction, the optical integrated chip comprising an optical element region and an electrical chip region located outside the optical element region along a second direction, the optical element region being provided with a built-in optical element, the second direction being parallel to the front surface of the optical integrated chip;

[0031] Mounting an electronic chip on the electrical chip region on the front side of the optical integrated chip, and electrically connecting the electronic chip and the optical integrated chip;

[0032] Mounting a transparent block structure on the optical element region of the optical integrated chip, wherein the transparent block structure includes a lower surface facing the optical integrated chip and an upper surface opposite to the lower surface along the first direction;

[0033] A plastic sealing layer for sealing the electronic chip and the transparent block structure is formed on the front surface of the optical integrated chip, wherein the plastic sealing layer exposes the upper surface of the transparent block structure.

[0034] In some embodiments, the specific steps of mounting the transparent block structure on the optical element area of ​​the optical integrated chip include:

[0035] The transparent block structure is mounted on the optical element region of the optical integrated chip via a bottom transparent connector structure.

[0036] In some embodiments, the specific steps of attaching the transparent block structure to the optical element region of the optical integrated chip via a bottom transparent connector structure include:

[0037] forming a bottom support dam on the front surface of the optical integrated chip, wherein the projection of the bottom support dam on the front surface of the optical integrated chip is distributed around the periphery of the optical element area;

[0038] Applying a bottom transparent colloid material to the area enclosed by the bottom support dam;

[0039] Mounting the transparent block structure onto the bottom transparent colloid material;

[0040] The bottom transparent colloid material is solidified to form the bottom transparent connector structure.

[0041] In some embodiments, the specific steps of attaching the transparent block structure to the optical element region of the optical integrated chip via a bottom transparent connector structure include:

[0042] Mounting the bottom transparent connector structure on the front surface of the optical integrated chip;

[0043] The transparent block structure is mounted on the bottom transparent connector structure.

[0044] In some embodiments, a plurality of the electronic chips are arranged at intervals on the front surface of the optical integrated chip at least along the second direction;

[0045] At least one of the electronic chips is a control chip, and a surface of the control chip facing away from the optical integrated chip is flush with the upper surface of the transparent block structure.

[0046] In some embodiments, the transparent block structure is a hexahedral structure, and the light transmittance of the transparent block structure is above 90%.

[0047] In some embodiments, the material of the transparent block structure includes any one of silicon oxide, optical quartz, polymethyl methacrylate, and polystyrene, or a combination of two or more thereof.

[0048] In some embodiments, the specific steps of forming a plastic encapsulation layer on the front surface of the optical integrated chip to encapsulate the electronic chip and the transparent block structure include:

[0049] Injecting a molding compound onto the front surface of the optical integrated chip to form the molding layer covering the electronic chip and the transparent block structure;

[0050] The plastic sealing layer is thinned to expose the upper surface of the transparent block structure and the surface of the control chip facing away from the optical integrated chip.

[0051] In some embodiments, after forming a plastic encapsulation layer on the front surface of the optical integrated chip to encapsulate the electronic chip and the transparent block structure, the method further includes the following steps:

[0052] An external optical element is mounted on the upper surface of the transparent block structure.

[0053] In some embodiments, the external optical element is a laser array element.

[0054] In some embodiments, before mounting an external optical element on the upper surface of the transparent block structure, the method further includes the following steps:

[0055] The roughness of the upper surface of the transparent block structure is reduced to below 100 nm.

[0056] In some embodiments, the specific steps of reducing the roughness of the upper surface of the transparent block structure to less than 100 nm include:

[0057] The upper surface of the transparent block structure is processed by any one of a physical polishing process, a laser surface treatment process and a chemical mechanical grinding process, or a combination of two or more processes, so that the roughness of the upper surface of the transparent block structure is reduced to below 100 nm.

[0058] In some embodiments, the specific steps of mounting an external optical element on the upper surface of the transparent block structure include:

[0059] The external optical element is mounted on the upper surface of the transparent block structure through a top transparent connector structure.

[0060] In some embodiments, the specific steps of attaching the external optical element to the upper surface of the transparent block structure through a top transparent connector structure include:

[0061] forming a top support dam on the upper surface of the transparent block structure;

[0062] Applying a top transparent colloid material to the area enclosed by the top support dam;

[0063] Mounting the external optical element onto the top transparent colloid material;

[0064] The top transparent colloid material is solidified to form the top transparent connector structure.

[0065] In some embodiments, the specific steps of attaching the external optical element to the upper surface of the transparent block structure through a top transparent connector structure include:

[0066] Mounting the top transparent connector structure on the upper surface of the transparent block structure;

[0067] Mount the external optical element on the top transparent connector structure.

[0068] The optoelectronic co-packaging structure and manufacturing method provided by the present invention achieve co-packaging of the optical chip and the electronic chip by providing an optical element region and an electronic chip region located outside the optical element region on an optical integrated chip, wherein the optical element is provided in the optical element region, and the electronic chip is mounted on the electronic chip region of the optical integrated chip. A transparent block structure is mounted on the optical element region, and the plastic sealing layer of the electronic chip and the transparent block structure is exposed to the upper surface of the transparent block structure, so that the transparent block structure protects the optical element located in the optical foreseeable region during the plastic sealing process. Moreover, since the transparent block structure does not need to be removed after the plastic sealing process, exposure of the optical element is avoided, and contamination of the plastic sealing particles of the optical element can also be avoided after the plastic sealing process. Furthermore, the present invention utilizes a transparent block structure to protect the optical element. The processing of the transparent block structure is highly controllable, ensuring that the external optical element subsequently mounted on the upper surface of the transparent block structure matches the optical element in the optical integrated chip. This improves the controllability of the entire co-package structure manufacturing process, thereby enhancing the performance stability and reliability of the optoelectronic co-package structure. The present invention is compatible with both 2.5D and 3D advanced packaging processes and can be widely applied to a variety of optoelectronic co-package structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly describes the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0070] Figure 1 2 is a schematic structural diagram of an optoelectronic co-packaging structure according to a specific embodiment of the present invention;

[0071] Figure 2 is another structural schematic diagram of the optoelectronic co-packaging structure in a specific embodiment of the present invention;

[0072] Figure 3 This is another structural diagram of the optoelectronic co-packaging structure in a specific embodiment of the present invention;

[0073] Figure 4 This is another structural diagram of the optoelectronic co-packaging structure in a specific embodiment of the present invention;

[0074] Figure 5 is a flow chart of a method for manufacturing an optoelectronic co-packaging structure according to a specific embodiment of the present invention;

[0075] Figure 6 is a schematic structural diagram after a bottom support dam is formed on an optical integrated chip in a specific embodiment of the present invention;

[0076] Figure 7 1 is a schematic structural diagram of a specific embodiment of the present invention after a bottom transparent colloid material is dot-coated on an optical integrated chip;

[0077] Figure 8 It is a structural schematic diagram of a specific embodiment of the present invention after the transparent block structure is attached to the bottom support dam and the bottom transparent connector structure;

[0078] Figure 9 This is a schematic diagram of a structure after a plastic sealing layer is formed in a specific embodiment of the present invention;

[0079] Figure 10 This is a structural schematic diagram of a specific embodiment of the present invention after the plastic sealing layer is thinned;

[0080] Figure 11 1 is a schematic structural diagram of a specific embodiment of the present invention after mounting a bottom transparent connector structure on the front surface of the optical integrated chip;

[0081] Figure 12 1 is a schematic structural diagram of a transparent block structure mounted on a bottom transparent connector structure in a specific embodiment of the present invention;

[0082] Figure 13 is another structural schematic diagram after the plastic sealing layer is formed in a specific embodiment of the present invention;

[0083] Figure 14 This is another structural schematic diagram after the plastic sealing layer is thinned in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0084] The specific embodiments of the optoelectronic co-packaging structure and the manufacturing method thereof provided by the present invention are described in detail below with reference to the accompanying drawings.

[0085] This specific embodiment provides an optoelectronic co-packaging structure, Figure 1 FIG. 1 is a schematic diagram of a photoelectric co-packaging structure according to a specific embodiment of the present invention. Figure 1 As shown, the optoelectronic co-packaging structure includes:

[0086] An optical integrated chip 10 includes a front surface and a back surface that are oppositely distributed along a first direction D1. The optical integrated chip 10 includes an optical element region and an electrical chip region located outside the optical element region along a second direction D2. A built-in optical element 11 is disposed in the optical element region. The second direction D2 is parallel to the front surface of the optical integrated chip 10.

[0087] an electronic chip 12 mounted on the electrical chip region on the front side of the optical integrated chip 10 and electrically connected to the optical integrated chip 10;

[0088] a transparent block structure 13 mounted on the optical element region of the optical integrated chip 10, wherein the transparent block structure 13 includes a lower surface facing the optical integrated chip 10 and an upper surface opposite to the lower surface along the first direction D1;

[0089] The plastic sealing layer 19 is located on the front surface of the optical integrated chip 10 and plastic seals the electronic chip 12 and the transparent block structure 13 . The plastic sealing layer 19 exposes the upper surface of the transparent block structure 13 .

[0090] Specifically, the optical integrated chip 10 includes a front side and a back side that are relatively distributed along the first direction D1. The optical integrated chip 10 includes the optical element region and the electrical chip region located outside the optical element region along the second direction D2. In one example, the projection of the optical element region on the front side of the optical integrated chip 10 can be circular, rectangular, or elliptical. The built-in optical element 11 is embedded in the optical element region of the optical integrated chip 10. The light-sensing surface of the built-in optical element 11 is exposed on the front side of the optical integrated chip 10, that is, the light-sensing surface of the built-in optical element 11 is flush with the front side of the optical integrated chip 10. In one example, the built-in optical element 11 includes a grating coupler, an end coupler, etc. At least one electronic chip 12 is mounted on the front side of the optical integrated chip 10, and the electronic chip 12 is located in the electrical chip region. The electronic chip 12 is electrically connected to the control circuit layer inside the optical integrated chip 10. The number of electronic chips 12 mounted on the front side of the optical integrated chip 10 can be one or more. Figure 1 FIG. 1 shows three electronic chips 12 mounted on the front surface of the optical integrated chip 10. The multiple mentioned in this embodiment refers to more than two. In one example, Figure 1 As shown, the structures and functions of the multiple electronic chips 12 are the same, and the heights of the multiple electronic chips 12 along the first direction D1 are the same, that is, the multiple electronic chips 12 are flush with the surface away from the optical integrated chip 10 .

[0091] The transparent block structure 13 is directly mounted on the optical element region of the optical integrated chip 10, and the projection of the transparent block structure 13 on the front surface of the optical integrated chip 10 covers the built-in optical element 11, thereby avoiding contamination of the built-in optical element 11 due to overflow of the molding compound during the molding process of forming the molding layer 19, and avoiding the built-in optical element 11 being affected by the molding process. Moreover, the transparent block structure 13 can transmit optical signals and will not affect the transmission of the optical signals. Therefore, after the molding process is completed, the transparent block structure 13 does not need to be removed, thereby avoiding the problems of molding compound diffusion and abnormal falling of particles when removing the plastic sacrificial cover in the traditional process, and avoiding contamination of the built-in optical element 11 by the removal process. At the same time, since the manufacturing process of the transparent block structure 13 is simple and the processing process is highly controllable, it can not only be effectively applied to production operations, but also improve the matching with external optical elements, increase the controllability of the optoelectronic co-packaging structure process, and reduce the manufacturing cost of the optoelectronic co-packaging structure.

[0092] In some embodiments, the optoelectronic co-packaging structure further comprises:

[0093] The external optical element 16 is mounted on the upper surface of the transparent block structure 13 .

[0094] In some embodiments, the external optical element 16 is a laser array element.

[0095] Specifically, since the transparent block structure 13 is mounted on the optical area element area of ​​the optical integrated chip 10, and the transparent block structure 13 is not removed after the plastic packaging process, the external optical element 16 can be directly mounted on the upper surface of the transparent block structure 13. Not only does it not need to use an inserted external optical element, it further simplifies the manufacturing process of the optoelectronic co-packaging structure, and it is easy to align the external optical element 16 with the built-in optical element 11, avoiding the problem in traditional processes that the external optical element cannot match the built-in optical element due to the poor controllability of the processing technology of the plastic sacrificial cover.

[0096] In some embodiments, the transparent block structure 13 is a hexahedral structure, and the light transmittance of the transparent block structure 13 is above 90%.

[0097] For example, the transparent block structure 13 is a rectangular parallelepiped structure or a cube structure, which not only further simplifies the manufacturing process of the transparent block structure 13, but also facilitates the formation of a flat plastic package surface, which helps to smoothly implement subsequent processes. The light transmittance of the transparent block structure 13 is more than 90%, which means that the transmittance of the transparent block structure 13 to the incident light from the outside (such as the external optical element 16) entering the light sensing surface of the built-in optical element 11 is more than 90%. Alternatively, the light transmittance of the transparent block structure 13 is more than 90%, which means that the transmittance of the transparent block structure 13 to the outgoing light emitted from the light sensing surface of the built-in optical element 11 is more than 90%.

[0098] In other embodiments, the transparent block structure 13 is in the shape of a polygonal prism structure or a cylindrical structure to meet the requirements of specific optical devices.

[0099] In some embodiments, the material of the transparent block structure 13 includes any one of silicon oxide, optical quartz, polymethyl methacrylate, and polystyrene, or a combination of two or more thereof.

[0100] In some embodiments, the roughness of the upper surface of the transparent bulk structure 13 is below 100 nm.

[0101] Specifically, by setting the roughness of the upper surface of the transparent block structure 13 to below 100 nm, it is possible to avoid excessive scattering and diffuse reflection of the light signal when it is incident on the upper surface of the transparent block structure 13 or emitted from the upper surface of the transparent block structure 13, thereby ensuring the transmission quality of the light signal.

[0102] In some embodiments, the optoelectronic co-packaging structure further comprises:

[0103] The bottom transparent connector structure 14 is located on the front surface of the optical integrated chip 10 , and one end of the bottom transparent connector structure 14 is connected to the optical integrated chip 10 , and the other end is connected to the transparent block structure 13 .

[0104] Specifically, the bottom transparent connector structure 14 has double-sided adhesive, allowing its two opposing surfaces to bond to the front surface of the optical integrated chip 10 and the bottom surface of the transparent block structure 13, respectively. This ensures that the transparent block structure 13 is stably fixed to the front surface of the optical integrated chip 10 and prevents the position of the transparent block structure 13 from shifting during the molding process. In one example, the light transmittance of the bottom transparent connector structure 14 is the same as that of the transparent block structure 13, for example, the light transmittance of the bottom transparent connector structure 14 is also above 90%.

[0105] In one example, the bottom transparent connector structure 14 is made of a solid thermal release film, ABF (Ajinomoto Build-up Film Adhesive), or DAF (Die Attach Film). In another example, the bottom transparent connector structure 14 is formed by curing a liquid epoxy molding compound, underfill, edge dam adhesive, or bonding adhesive.

[0106] In some embodiments, the optoelectronic co-packaging structure further comprises:

[0107] The bottom support dam 15 is connected to the optical integrated chip 10 at one end and to the transparent block structure 13 at the other end. The projection of the bottom support dam 15 on the front surface of the optical integrated chip 10 is distributed around the periphery of the optical element area.

[0108] In some embodiments, the bottom support dam 15 is located inside the bottom transparent connector structure 14; or,

[0109] The bottom support dam 15 covers the side surface of the bottom transparent connector structure 14 .

[0110] For example, if Figure 1 As shown, the bottom support dam 15 and the bottom transparent connector structure 14 are arranged between the transparent block structure 13 and the front of the optical integrated chip 10, and the bottom support dam 15 is located inside the bottom transparent connector structure 14 or covers the side of the bottom transparent connector structure 14. On the one hand, it can control the height of the bottom transparent connector structure 14 and ensure the thickness uniformity of the bottom transparent connector structure 14, thereby improving the flatness of the entire package surface and ensuring the transmission quality of the optical signal; on the other hand, it can jointly support the transparent block structure 13 with the bottom transparent connector structure 14, thereby further improving the stability of the transparent block structure 13.

[0111] In one example, the material of the bottom support dam 15 can be a rigid material or a flexible material that can be formed through a curing process, such as photoresist, PI (Polyimide) glue, bonding glue, epoxy molding compound, bottom filler, dam glue, DAF film or high temperature resistant tape.

[0112] In one example, the bottom support dam 15 is a continuously distributed annular structure, and the projection of the annular bottom support dam 15 on the front surface of the optical integrated chip 10 surrounds the periphery of the optical element area. In another example, the bottom support dam 15 includes a plurality of bottom support pillars arranged at intervals, and the projections of the plurality of bottom support pillars on the front surface of the optical integrated chip 10 surround the periphery of the optical element area. The bottom support pillars can be cylinders or prisms.

[0113] Figure 3 is another structural diagram of the optoelectronic co-packaging structure in a specific embodiment of the present invention. In other embodiments, such as Figure 3 As shown, only the bottom transparent connector structure 14 is provided between the transparent block structure 13 and the front surface of the optical integrated chip 10, thereby further simplifying the manufacturing process of the optoelectronic co-packaging structure and improving the manufacturing efficiency of the optoelectronic co-packaging structure.

[0114] In some embodiments, the optoelectronic co-packaging structure further comprises:

[0115] The top transparent connector structure 17 is located on the upper surface of the transparent block structure 13 , and one end of the top transparent connector structure 17 is connected to the transparent block structure 13 , and the other end is connected to the external optical element 16 .

[0116] For example, if Figure 1 As shown, the top transparent connector structure 17 has double-sided adhesiveness, so that the two opposite sides of the top transparent connector structure 17 are respectively bonded to the upper surface of the transparent block structure 13 and the external optical element 16, thereby stably fixing the external optical element 16 on the upper surface of the transparent block structure 13, ensuring that the position of the external optical element 16 is aligned with the position of the internal optical element 11 in the optical integrated chip 10, and ensuring smooth and high-quality transmission of the light between the external optical element 16 and the internal optical element 11. In one example, the transmittance of the top transparent connector structure 17 to the light is the same as the transmittance of the transparent block structure 13 to the light, for example, the transmittance of the top transparent connector structure 17 to the light is also above 90%.

[0117] In one example, the top transparent connector structure 17 is made of a solid thermal release film, ABF, or DAF. In another example, the top transparent connector structure 17 is formed by curing a liquid epoxy molding compound, bottom filler, edge dam glue, or bonding glue.

[0118] In some embodiments, the optoelectronic co-packaging structure further comprises:

[0119] The top support dam 18 is located on the upper surface of the transparent block structure 13, and the projection of the top support dam 18 on the upper surface of the transparent block structure 13 is distributed around the periphery of the projection of the external optical element 16 on the upper surface of the transparent block structure 13.

[0120] For example, if Figure 1 As shown, the top support dam 18 and the top transparent connector structure 17 are provided on the upper surface of the transparent block structure 13, and the top support dam 18 covers the side of the top transparent connector structure 17. On the one hand, it is convenient to control the thickness of the top transparent connector structure 17; on the other hand, it can also prevent the liquid colloid from overflowing onto the surface of the electronic chip 12 during the formation of the top transparent connector structure 17.

[0121] In one example, the material of the top support dam 18 can be a rigid material or a flexible material that can be formed through a curing process, such as photoresist, PI (Polyimide) glue, bonding glue, epoxy molding compound, bottom filler, dam glue, DAF film or high temperature resistant tape.

[0122] In one example, the top support dam 18 is a continuously distributed annular structure, and the projection of the annular top support dam 18 on the upper surface of the transparent block structure 13 is distributed around the periphery of the projection of the external optical element 16 on the upper surface of the transparent block structure 13. In another example, the top support dam 18 includes a plurality of top support pillars arranged at intervals, and the projections of the plurality of top support pillars on the upper surface of the transparent block structure 13 are distributed around the periphery of the projection of the external optical element 16 on the upper surface of the transparent block structure 13. The top support pillars may be cylinders or prisms.

[0123] In other embodiments, Figure 3 As shown, the top support dam 18 is not provided on the upper surface of the transparent block structure 13 , thereby further simplifying the manufacturing process of the optoelectronic co-packaging structure and improving the manufacturing efficiency of the optoelectronic co-packaging structure.

[0124] Figure 2is another structural diagram of the optoelectronic co-packaging structure in a specific embodiment of the present invention, Figure 4 FIG. 1 is another structural diagram of the optoelectronic co-packaging structure according to a specific embodiment of the present invention. Figure 2 or Figure 4 As shown, the plurality of electronic chips are arranged at intervals on the front surface of the optical integrated chip 10 at least along the second direction D2;

[0125] At least one of the electronic chips is a control chip 121 , and a surface of the control chip 121 facing away from the optical integrated chip 10 is flush with the upper surface of the transparent block structure 13 .

[0126] For example, if Figure 2 or Figure 4 As shown, the plurality of electronic chips are arranged at intervals on the front surface of the optical integrated chip 10 at least along the second direction D2. At least one of the plurality of electronic chips is a control chip 121, and at least another one is a memory chip 122. In one example, the control chip 121 is an ASIC (Application-Specific Integrated Circuit), and the memory chip 122 is an HBM (High Bandwidth Memory) chip. By making the surface of the control chip 121 facing away from the optical integrated chip 10 flush with the upper surface of the transparent block structure 13, it is convenient to simultaneously expose the control chip 121 and the transparent block structure 13 during the thinning process after plastic packaging, thereby further optimizing the manufacturing process of the optoelectronic co-packaging structure.

[0127] In other embodiments, Figure 1 or Figure 3 As shown, the multiple electronic chips 12 are arranged at intervals on the front of the optical integrated chip 10 at least along the second direction D2, and the multiple electronic chips 12 have the same height along the first direction D1, and the surfaces of the multiple electronic chips 12 facing away from the optical integrated chip 10 are all flush with the upper surface of the transparent block structure 13.

[0128] This specific embodiment also provides a method for manufacturing an optoelectronic co-packaging structure. Figure 5 This is a flow chart of the method for manufacturing the optoelectronic co-packaging structure in a specific embodiment of the present invention. The schematic diagram of the optoelectronic co-packaging structure manufactured by the method for manufacturing the optoelectronic co-packaging structure can be found in Figures 1-4 .like Figure 1-Figure 5 As shown, the manufacturing method of the optoelectronic co-packaging structure includes the following steps:

[0129] Step S51, forming an optical integrated chip 10, wherein the optical integrated chip 10 includes a front surface and a back surface that are oppositely distributed along a first direction D1, the optical integrated chip 10 includes an optical element region and an electrical chip region located outside the optical element region along a second direction D2, the optical element region is provided with a built-in optical element 11, and the second direction D2 is parallel to the front surface of the optical integrated chip 10;

[0130] Step S52 , mounting the electronic chip 12 on the electrical chip region on the front side of the optical integrated chip 10 , and electrically connecting the electronic chip 12 to the optical integrated chip 10 ;

[0131] Step S53, mounting a transparent block structure 13 on the optical element region of the optical integrated chip 10, wherein the transparent block structure 13 includes a lower surface facing the optical integrated chip 10 and an upper surface opposite to the lower surface along the first direction D1;

[0132] Step S54 , forming a plastic sealing layer 19 on the front surface of the optical integrated chip 10 to seal the electronic chip 12 and the transparent block structure 13 , wherein the plastic sealing layer 19 exposes the upper surface of the transparent block structure 13 .

[0133] In some embodiments, the specific steps of mounting the transparent block structure 13 on the optical element region of the optical integrated chip 10 include:

[0134] The transparent block structure 13 is mounted on the optical element region of the optical integrated chip 10 via a bottom transparent connector structure 14 .

[0135] Figure 6 is a schematic structural diagram after a bottom support dam is formed on an optical integrated chip in a specific embodiment of the present invention. Figure 7 Schematic diagram of the structure after the bottom transparent colloid material is dotted on the optical integrated chip in a specific embodiment of the present invention. Figure 8 This is a schematic diagram of the structure after the transparent block structure is mounted on the bottom support dam and the bottom transparent connector structure in a specific embodiment of the present invention. In some embodiments, the specific steps of mounting the transparent block structure 13 to the optical element area of ​​the optical integrated chip 10 via a bottom transparent connector structure 14 include:

[0136] forming a bottom support dam 15 on the front surface of the optical integrated chip 10 , wherein the projection of the bottom support dam 15 on the front surface of the optical integrated chip 10 is distributed around the periphery of the optical element area;

[0137] Applying a bottom transparent colloid material 70 to the area enclosed by the bottom support dam 15;

[0138] Mounting the transparent block structure 13 onto the bottom transparent colloid material 70;

[0139] The bottom transparent colloid material 70 is cured to form the bottom transparent connector structure 14 .

[0140] In some embodiments, the plurality of electronic chips 12 are arranged at intervals on the front surface of the optical integrated chip 10 at least along the second direction D2;

[0141] At least one of the electronic chips 12 is a control chip 121 , and a surface of the control chip 121 facing away from the optical integrated chip 10 is flush with the upper surface of the transparent block structure 13 .

[0142] For example, specifically, the optical integrated chip 10 includes a front side and a back side relatively distributed along the first direction D1. The optical integrated chip 10 includes the optical element area and the electrical chip area located outside the optical element area along the second direction D2. In one example, the projection of the optical element area on the front side of the optical integrated chip 10 can be circular, rectangular or elliptical. The built-in optical element 11 is embedded in the optical element area of ​​the optical integrated chip 10. The light sensing surface of the built-in optical element 11 is exposed on the front side of the optical integrated chip 10, that is, the light sensing surface of the built-in optical element 11 is flush with the front side of the optical integrated chip 10. In one example, the built-in optical element 11 includes a grating coupler, an end coupler, etc.

[0143] After the control chip 121 and the memory chip 122 are mounted on the electrical chip area of ​​the optical integrated chip 10, a bottom support material is applied to the periphery of the optical element area of ​​the optical integrated chip 10 using a dispensing process, and the bottom support dam 15 is formed after curing. Figure 6 As shown. The bottom support material can be a rigid material or a flexible material, such as photoresist, PI (Polyimide) glue, bonding glue, epoxy molding compound, bottom filler, dam glue, DAF film or high temperature resistant tape. The projection of the bottom support dam 15 on the front surface of the optical integrated chip 10 is distributed around the periphery of the optical element area. Afterwards, the liquid bottom transparent colloidal material 70 is applied to the area enclosed by the bottom support dam 15, as shown in FIG. Figure 7 As shown. The bottom transparent colloid material 70 can be epoxy molding compound, bottom filling material, edge dam glue or bonding glue. Then, the transparent block structure 13 is mounted on the bottom transparent colloid material 70, and the bottom transparent colloid material 70 is cured to form the bottom transparent connector structure 14, as shown. Figure 8 As shown. The bottom transparent connector structure 14 has double-sided adhesive, so that the two opposite sides of the bottom transparent connector structure 14 are bonded to the front surface of the optical integrated chip 10 and the lower surface of the transparent block structure 13, respectively. This stably fixes the transparent block structure 13 to the front surface of the optical integrated chip 10 and prevents the position of the transparent block structure 13 from shifting during the plastic encapsulation process. In one example, the bottom transparent connector structure 14 has a light transmittance of over 90%.

[0144] The bottom support dam 15 and the bottom transparent connector structure 14 are arranged between the transparent block structure 13 and the front of the optical integrated chip 10, and the bottom support dam 15 is located inside the bottom transparent connector structure 14 or covers the side of the bottom transparent connector structure 14. On the one hand, it can control the height of the bottom transparent connector structure 14 and ensure the thickness uniformity of the bottom transparent connector structure 14, thereby improving the flatness of the entire package surface and ensuring the transmission quality of the optical signal; on the other hand, it can jointly support the transparent block structure 13 with the bottom transparent connector structure 14, thereby further improving the stability of the transparent block structure 13.

[0145] In one example, the bottom support dam 15 is a continuously distributed annular structure, and the projection of the annular bottom support dam 15 on the front surface of the optical integrated chip 10 surrounds the periphery of the optical element area. In another example, the bottom support dam 15 includes a plurality of bottom support pillars arranged at intervals, and the projections of the plurality of bottom support pillars on the front surface of the optical integrated chip 10 surround the periphery of the optical element area. The bottom support pillars can be cylinders or prisms.

[0146] Figure 11 1 is a schematic diagram of the structure after the bottom transparent connector structure is mounted on the front surface of the optical integrated chip in a specific embodiment of the present invention. Figure 12 Schematic diagram of the structure after the transparent block structure is attached to the bottom transparent connector structure in a specific embodiment of the present invention. Figure 11 and Figure 12 As shown, the specific steps of attaching the transparent block structure 13 to the optical element area of ​​the optical integrated chip 10 through a bottom transparent connector structure 14 include:

[0147] Mounting the bottom transparent connector structure 14 on the front surface of the optical integrated chip 10;

[0148] The transparent block structure 13 is mounted on the bottom transparent connector structure 14 .

[0149] For example, a transparent DAF, a thermal peeling film or a DAF is directly mounted on the optical element region of the optical integrated chip 10 as the bottom transparent connector structure 14, such as Figure 11 Next, the transparent block structure 13 is mounted on the bottom transparent connector structure 14, as shown. Figure 12 Since there is no need to form the bottom support dam 15 and no need to perform a curing process for the bottom transparent connector structure 14, the manufacturing process of the optoelectronic co-packaging structure is simplified and the manufacturing efficiency of the optoelectronic co-packaging structure is improved.

[0150] In some embodiments, the transparent block structure 13 is a hexahedral structure, and the light transmittance of the transparent block structure 13 is above 90%.

[0151] In other embodiments, the transparent block structure 13 is in the shape of a polygonal prism structure or a cylindrical structure to meet the requirements of specific optical devices.

[0152] In some embodiments, the material of the transparent block structure 13 includes any one of silicon oxide, optical quartz, polymethyl methacrylate, and polystyrene, or a combination of two or more thereof.

[0153] For example, the transparent block structure 13 is a rectangular parallelepiped structure or a cube structure, which not only further simplifies the manufacturing process of the transparent block structure 13, but also facilitates the formation of a flat plastic package surface, which helps to smoothly implement subsequent processes. The light transmittance of the transparent block structure 13 is more than 90%, which means that the transmittance of the transparent block structure 13 to the incident light from the outside (such as the external optical element 16) entering the light sensing surface of the built-in optical element 11 is more than 90%. Alternatively, the light transmittance of the transparent block structure 13 is more than 90%, which means that the transmittance of the transparent block structure 13 to the outgoing light emitted from the light sensing surface of the built-in optical element 11 is more than 90%.

[0154] Figure 9 is a structural schematic diagram after the plastic sealing layer is formed in a specific embodiment of the present invention, Figure 10 1 is a structural diagram of a specific embodiment of the present invention after the plastic sealing layer is thinned. Figure 13 is another structural schematic diagram after the plastic sealing layer is formed in a specific embodiment of the present invention, Figure 14 This is another structural diagram of the present invention after the plastic layer is thinned. Figures 1-4 、 Figure 9 、 Figure 10 、 Figure 13 and Figure 14As shown, in some embodiments, the specific steps of forming the plastic sealing layer 19 on the front surface of the optical integrated chip 10 to plastic seal the electronic chip 12 and the transparent block structure 13 include:

[0155] Injecting a molding compound onto the front surface of the optical integrated chip 10 to form the molding layer 19 covering the electronic chip 12 and the transparent block structure 13;

[0156] The plastic sealing layer 19 is thinned to expose the upper surface of the transparent block structure 13 and the surface of the control chip 121 facing away from the optical integrated chip 10 .

[0157] For example, after the transparent block structure 13 is mounted above the optical integrated chip 10, the control chip 121 and the memory chip 122 are sealed by a plastic sealing process, and the thickness of the plastic sealing layer 19 is controlled so that the plastic sealing layer 19 also covers the upper surface of the transparent block structure 13 and the top surface of the control chip 121 (i.e., the surface of the control chip 121 facing away from the optical integrated chip 10) and the top surface of the memory chip 122 (i.e., the surface of the memory chip 122 facing away from the optical integrated chip 10), as shown in FIG. Figure 9 or Figure 13 Afterwards, the thickness of the plastic layer 19 can be reduced by a thinning process such as grinding, so as to expose at least the upper surface of the transparent block structure 13 and the top surface of the control chip 121, as shown. Figure 10 or Figure 14 As shown. Since the transparent block structure 13 is directly adhered to the optical element area of ​​the optical integrated chip through the bottom connector structure 14, it can prevent the plastic encapsulation material from overflowing to the optical element area during the plastic encapsulation process, thereby protecting the optical element area and avoiding contamination of the optical element area. Moreover, the transparent block structure 13 can transmit the optical signal and will not affect the transmission of the optical signal. Therefore, after the plastic encapsulation process is completed, there is no need to remove the transparent block structure 13, thereby avoiding the problems of plastic encapsulation material diffusion and abnormal falling of particles when removing the plastic sacrificial cover in the traditional process, and avoiding the contamination of the built-in optical element 11 by the removal process. At the same time, since the manufacturing process of the transparent block structure 13 is simple and the processing process is highly controllable, it can not only be effectively applied to production operations, but also can improve the matching with the external optical element, increase the controllability of the process of the optoelectronic co-packaging structure, and reduce the manufacturing cost of the optoelectronic co-packaging structure.

[0158] In some embodiments, after forming a plastic encapsulation layer 19 on the front surface of the optical integrated chip 10 to encapsulate the electronic chip and the transparent block structure 13, the following steps are further included:

[0159] An external optical element 16 is mounted on the upper surface of the transparent block structure 13 .

[0160] In some embodiments, the external optical element 16 is a laser array element.

[0161] In some embodiments, before mounting the external optical element 16 on the upper surface of the transparent block structure 13, the following steps are further included:

[0162] The roughness of the upper surface of the transparent block structure 13 is reduced to below 100 nm.

[0163] In some embodiments, the specific steps of reducing the roughness of the upper surface of the transparent block structure 13 to below 100 nm include:

[0164] The upper surface of the transparent block structure 13 is processed by any one of a physical polishing process, a laser surface treatment process and a chemical mechanical grinding process, or a combination of two or more processes, so that the roughness of the upper surface of the transparent block structure 13 is reduced to below 100 nm.

[0165] Specifically, after the upper surface of the transparent block structure 13 is exposed through a thinning process, the upper surface of the transparent block structure 13 is processed by any one of a physical polishing process, a laser surface treatment process, and a chemical mechanical grinding process, or a combination of two or more processes, so that the roughness of the upper surface of the transparent block structure 13 is reduced to below 100 nm, thereby avoiding excessive scattering and diffuse reflection of the light signal when it is incident on the upper surface of the transparent block structure 13 or emitted from the upper surface of the transparent block structure 13, thereby ensuring the transmission quality of the light signal.

[0166] In some embodiments, the specific steps of mounting the external optical element 16 on the upper surface of the transparent block structure 13 include:

[0167] The external optical element 16 is mounted on the upper surface of the transparent block structure 13 via a top transparent connector structure 17 .

[0168] In some embodiments, the specific steps of attaching the external optical element 16 to the upper surface of the transparent block structure 13 via a top transparent connector structure 17 include:

[0169] forming a top support dam 18 on the upper surface of the transparent block structure 13;

[0170] Applying a spot of the top transparent colloid material to the area enclosed by the top support dam 18;

[0171] Mounting the external optical element 16 onto the top transparent colloid material;

[0172] The top transparent colloid material is solidified to form the top transparent connector structure 17 .

[0173] For example, after reducing the roughness of the upper surface of the transparent block structure 13 to below 100nm, a dam glue is applied to the periphery of the optical element area of ​​the optical integrated chip 10 using a dispensing process, and the top support dam 18 is formed after curing. Thereafter, a top transparent colloid material is applied to the area enclosed by the top support dam 18. Then, the external optical element 16 is mounted on the top transparent colloid material, and the top transparent colloid material is cured to form the top transparent connector structure 17, as shown in FIG. Figure 2 As shown. The top transparent connector structure 17 has double-sided adhesive, so that the two opposite sides of the top transparent connector structure 17 are bonded to the upper surface of the transparent block structure 13 and the external optical element 16, respectively, to stably fix the external optical element 16 on the upper surface of the transparent block structure 13, ensure that the position of the external optical element 16 is aligned with the position of the internal optical element 11 in the optical integrated chip 10, and ensure smooth and high-quality transmission of light between the external optical element 16 and the internal optical element 11. In one example, the transmittance of the top transparent connector structure 17 to the light is also above 90%.

[0174] Since the transparent block structure 13 is mounted on the optical area component area of ​​the optical integrated chip 10, and the transparent block structure 13 is not removed after the plastic packaging process, the external optical element 16 can be directly mounted on the upper surface of the transparent block structure 13. Not only does it not need to use an inserted external optical element, it further simplifies the manufacturing process of the optoelectronic co-packaging structure, and it is easy to align the external optical element 16 with the built-in optical element 11, avoiding the problem in traditional processes that the external optical element cannot match the built-in optical element due to the poor controllability of the processing technology of the plastic sacrificial cover.

[0175] In other embodiments, the specific steps of attaching the external optical element 16 to the upper surface of the transparent block structure 13 via a top transparent connector structure 17 include:

[0176] Mounting the top transparent connector structure 17 on the upper surface of the transparent block structure 13;

[0177] The external optical element 16 is mounted on the top transparent connector structure 17 .

[0178] For example, a transparent DAF is directly mounted on the upper surface of the transparent block structure 13 to serve as the top transparent connector structure 17. Next, the external optical element 16 is mounted on the top transparent connector structure 17, as shown in FIG. Figure 4 Since there is no need to form the top support dam 18 and no need to perform a curing process for the top transparent connector structure 17, the manufacturing process of the optoelectronic co-packaging structure is simplified and the manufacturing efficiency of the optoelectronic co-packaging structure is improved.

[0179] The optoelectronic co-packaging structure and manufacturing method provided in this embodiment achieve co-packaging of the optical chip and the electronic chip by providing an optical element region and an electronic chip region located outside the optical element region on an optical integrated chip, wherein the optical element is provided in the optical element region, and the electronic chip is mounted on the electronic chip region of the optical integrated chip. A transparent block structure is mounted on the optical element region, and the plastic encapsulation layer of the electronic chip and the transparent block structure exposes the upper surface of the transparent block structure. Thus, the transparent block structure protects the optical element located in the optical foreseeable region during the plastic encapsulation process. Furthermore, since the transparent block structure does not need to be removed after the plastic encapsulation process, exposure of the optical element is avoided, thereby preventing contamination of the optical element by plastic encapsulation particles after the plastic encapsulation process. Furthermore, this embodiment utilizes a transparent block structure to protect the optical element. The processing of this transparent block structure is highly controllable, ensuring that the external optical element subsequently mounted on the upper surface of the transparent block structure matches the optical element in the optical integrated chip. This improves the controllability of the entire co-package structure manufacturing process, thereby enhancing the performance stability and reliability of the optoelectronic co-package structure. This embodiment is compatible with both 2.5D and 3D advanced packaging processes and can be widely applied to a variety of optoelectronic co-package structures.

[0180] It should be noted that the terms "including," "having," and their variations, as used in this document, are intended to cover non-exclusive inclusions. Terms such as "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a specific order or precedence, unless the context clearly indicates otherwise. Such usage should be understood to be interchangeable where appropriate. The term "one or more" may be used to describe a feature, structure, or characteristic in the singular, or in the plural, depending at least in part on the context, to describe a feature, structure, or combination of features. The term "based on" should be understood as not necessarily intended to express an exclusive set of factors, but may alternatively, also depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, the embodiments of the present invention and the features therein may be combined with one another, unless there is a conflict. Furthermore, descriptions of well-known components and technologies have been omitted from the above description to avoid unnecessary confusion regarding the concepts of the present invention. In each of the above embodiments, each embodiment focuses on its differences from the other embodiments, and reference may be made to the same or similar parts between the embodiments.

[0181] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A photoelectric co-packaging structure, characterized in that: include: An optical integrated chip comprising a front surface and a back surface that are oppositely distributed along a first direction, the optical integrated chip comprising an optical element region and an electrical chip region located outside the optical element region along a second direction, wherein a built-in optical element is disposed in the optical element region, and the second direction is parallel to the front surface of the optical integrated chip; an electronic chip mounted on the electrical chip region on the front side of the optical integrated chip, and electrically connected to the optical integrated chip; a transparent block structure mounted on the optical element region of the optical integrated chip, the transparent block structure comprising a lower surface facing the optical integrated chip and an upper surface opposite to the lower surface along the first direction; A plastic sealing layer is located on the front surface of the optical integrated chip and plastic seals the electronic chip and the transparent block structure, and the plastic sealing layer exposes the upper surface of the transparent block structure.

2. The optoelectronic co-packaging structure according to claim 1, characterized in that: Also includes: An external optical element is mounted on the upper surface of the transparent block structure.

3. The optoelectronic co-packaging structure according to claim 2, characterized in that: The external optical element is a laser array element.

4. The optoelectronic co-packaging structure according to claim 1, wherein: The transparent block structure is a hexahedral structure, and the light transmittance of the transparent block structure is above 90%.

5. The optoelectronic co-packaging structure according to claim 1, characterized in that: The material of the transparent block structure includes any one of silicon oxide, optical quartz, polymethyl methacrylate and polystyrene, or a combination of two or more thereof.

6. The optoelectronic co-packaging structure according to claim 1, characterized in that: The roughness of the upper surface of the transparent block structure is below 100 nm.

7. The optoelectronic co-packaging structure according to claim 1, characterized in that: Also includes: The bottom transparent connector structure is located on the front side of the optical integrated chip, and one end of the bottom transparent connector structure is connected to the optical integrated chip, and the other end is connected to the transparent block structure.

8. The optoelectronic co-packaging structure according to claim 7, characterized in that: Also includes: A bottom support dam is connected to the optical integrated chip at one end and to the transparent block structure at the other end. The projection of the bottom support dam on the front surface of the optical integrated chip is distributed around the periphery of the optical element area.

9. The optoelectronic co-packaging structure according to claim 8, characterized in that: The bottom support dam is located inside the bottom transparent connector structure; or, The bottom support dam covers the side surfaces of the bottom transparent connector structure.

10. The optoelectronic co-packaging structure according to claim 2, characterized in that: Also includes: The top transparent connector structure is located on the upper surface of the transparent block structure, and one end of the top transparent connector structure is connected to the transparent block structure, and the other end is connected to the external optical element.

11. The optoelectronic co-packaging structure according to claim 10, characterized in that: Also includes: A top support dam is located on the upper surface of the transparent block structure, and a projection of the top support dam on the upper surface of the transparent block structure is distributed around the periphery of a projection of the external optical element on the upper surface of the transparent block structure.

12. The optoelectronic co-packaging structure according to claim 1, wherein: The plurality of electronic chips are arranged at intervals on the front surface of the optical integrated chip at least along the second direction; At least one of the electronic chips is a control chip, and a surface of the control chip facing away from the optical integrated chip is flush with the upper surface of the transparent block structure.

13. A method for manufacturing an optoelectronic co-packaging structure, characterized in that: The steps include: forming an optical integrated chip, the optical integrated chip comprising a front surface and a back surface opposite to each other along a first direction, the optical integrated chip comprising an optical element region and an electrical chip region located outside the optical element region along a second direction, the optical element region being provided with a built-in optical element, the second direction being parallel to the front surface of the optical integrated chip; Mounting an electronic chip on the electrical chip region on the front side of the optical integrated chip, and electrically connecting the electronic chip and the optical integrated chip; Mounting a transparent block structure on the optical element region of the optical integrated chip, wherein the transparent block structure includes a lower surface facing the optical integrated chip and an upper surface opposite to the lower surface along the first direction; A plastic sealing layer for sealing the electronic chip and the transparent block structure is formed on the front surface of the optical integrated chip, wherein the plastic sealing layer exposes the upper surface of the transparent block structure.

14. The method for manufacturing a photovoltaic co-packaging structure according to claim 13, wherein: The specific step of mounting the transparent block structure on the optical element region of the optical integrated chip includes: mounting the transparent block structure on the optical element region of the optical integrated chip through a bottom transparent connector structure.

15. The method for manufacturing an optoelectronic co-packaging structure according to claim 14, wherein: The specific steps of attaching the transparent block structure to the optical element area of ​​the optical integrated chip through a bottom transparent connector structure include: forming a bottom support dam on the front surface of the optical integrated chip, wherein the projection of the bottom support dam on the front surface of the optical integrated chip is distributed around the periphery of the optical element area; Applying a bottom transparent colloid material to the area enclosed by the bottom support dam; Mounting the transparent block structure onto the bottom transparent colloid material; The bottom transparent colloid material is solidified to form the bottom transparent connector structure.

16. The method for manufacturing an optoelectronic co-packaging structure according to claim 14, wherein: The specific steps of attaching the transparent block structure to the optical element area of ​​the optical integrated chip through a bottom transparent connector structure include: Mounting the bottom transparent connector structure on the front surface of the optical integrated chip; The transparent block structure is mounted on the bottom transparent connector structure.

17. The method for manufacturing an optoelectronic co-packaging structure according to claim 16, wherein: The plurality of electronic chips are arranged at intervals on the front surface of the optical integrated chip at least along the second direction; at least one of the electronic chips is a control chip, and the surface of the control chip facing away from the optical integrated chip is flush with the upper surface of the transparent block structure.

18. The method for manufacturing an optoelectronic co-packaging structure according to claim 13, wherein: The transparent block structure is a hexahedral structure, and the light transmittance of the transparent block structure is above 90%.

19. The method for manufacturing an optoelectronic co-packaging structure according to claim 13, wherein: The material of the transparent block structure includes any one of silicon oxide, optical quartz, polymethyl methacrylate and polystyrene, or a combination of two or more thereof.

20. The method for manufacturing an optoelectronic co-packaging structure according to claim 17, wherein: The specific steps of forming a plastic sealing layer on the front surface of the optical integrated chip to plastic seal the electronic chip and the transparent block structure include: Injecting a molding compound onto the front surface of the optical integrated chip to form the molding layer covering the electronic chip and the transparent block structure; The plastic sealing layer is thinned to expose the upper surface of the transparent block structure and the surface of the control chip facing away from the optical integrated chip.

21. The method for manufacturing an optoelectronic co-packaging structure according to claim 13, wherein: After forming a plastic sealing layer on the front surface of the optical integrated chip to seal the electronic chip and the transparent block structure, the method further includes the following steps: An external optical element is mounted on the upper surface of the transparent block structure.

22. The method for manufacturing an optoelectronic co-packaging structure according to claim 21, wherein: The external optical element is a laser array element.

23. The method for manufacturing an optoelectronic co-packaging structure according to claim 21, wherein: Before mounting an external optical element on the upper surface of the transparent block structure, the method further includes the following steps: The roughness of the upper surface of the transparent block structure is reduced to below 100 nm.

24. The method for manufacturing an optoelectronic co-packaging structure according to claim 23, wherein: The specific steps of reducing the roughness of the upper surface of the transparent block structure to below 100 nm include: The upper surface of the transparent block structure is processed by any one of a physical polishing process, a laser surface treatment process and a chemical mechanical grinding process, or a combination of two or more processes, so that the roughness of the upper surface of the transparent block structure is reduced to below 100 nm.

25. The method for manufacturing an optoelectronic co-packaging structure according to claim 21, wherein: The specific steps of mounting an external optical element on the upper surface of the transparent block structure include: The external optical element is mounted on the upper surface of the transparent block structure through a top transparent connector structure.

26. The method for manufacturing an optoelectronic co-packaging structure according to claim 25, wherein: The specific steps of attaching the external optical element to the upper surface of the transparent block structure through a top transparent connector structure include: forming a top support dam on the upper surface of the transparent block structure; Applying a top transparent colloid material to the area enclosed by the top support dam; Mounting the external optical element onto the top transparent colloid material; The top transparent colloid material is solidified to form the top transparent connector structure.

27. The method for manufacturing an optoelectronic co-packaging structure according to claim 25, wherein: The specific steps of attaching the external optical element to the upper surface of the transparent block structure through a top transparent connector structure include: Mounting the top transparent connector structure on the upper surface of the transparent block structure; Mount the external optical element on the top transparent connector structure.

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