Low-power wake-up device and integrated control system

Abstract

The application provides a low-power wake-up device and an integrated control system, and relates to the technical field of low power consumption. The low-power wake-up device comprises an output module and an analog-digital power consumption control module. The analog-digital power consumption control module comprises a power consumption control circuit and at least one analog-digital converter. The application can trigger the analog-digital converter in a dormant state to receive the digital signal transmitted by the analog-digital converter through the power consumption control circuit in a low-power working state. Whether the digital signal is abnormal is judged according to preset parameters to adjust the working state of the current low-power wake-up device. Meanwhile, when the digital signal is in an abnormal state, the result abnormal signal is sent to an external detection module through the output module, so that the detection function of the external analog signal is guaranteed. Therefore, the application can reduce the design difficulty and application cost without additionally designing a low-power ADC and a corresponding subsystem or using an off-chip detection circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of low power consumption, in particular to a low power consumption wake-up device and an integrated control system. BACKGROUND

[0002] In the field of integrated circuits, as the transistor density and clock frequency continue to rise, the device power consumption also increases significantly, and technicians often reduce device power consumption through clock gating and power switching. On this basis, technicians also set up low power consumption circuits, external analog detection circuits to ensure the normal operation of the system, wherein the low power consumption circuit can be used to ensure the normal switching state of low power consumption and high power consumption, and the external analog detection circuit is used to accurately monitor the external analog circuit.

[0003] The low power consumption circuit with external analog detection function in the prior art often wakes up through internal timing logic, and then collects external analog signals according to software enablement, and compares the normal working state based on the external analog signals. However, in order to timely capture the abnormal situation of the external analog signal and the circuit, the wake-up period cannot be set too short, which undoubtedly increases the dynamic average power consumption to some extent. Although a chip integrated low power consumption subsystem can also be used, the low power consumption ADC in the subsystem is enabled periodically by software to collect external analog signals to achieve comparison purposes, but this method greatly increases the device cost.

[0004] Therefore, there is an urgent need for a low power consumption circuit with external analog detection function, which can reduce device cost while meeting low power consumption. SUMMARY

[0005] The purpose of the embodiment of the present application is to provide a low power consumption wake-up device and an integrated control system, which can reduce design difficulty and application cost without additional design of low power consumption ADC and corresponding subsystem or use of off-chip detection circuit.

[0006] In a first aspect, the present application provides a low power consumption wake-up device applied to an integrated control system, which comprises an output module and an analog-digital power consumption control module; the analog-digital power consumption control module comprises a power consumption control circuit and at least one analog-digital converter;

[0007] The input end of the power consumption control circuit is connected with the output end of each analog-digital converter; the output end of the power consumption control circuit is connected with the enable end of the analog-digital converter and the input end of the output module; wherein the analog-digital power consumption control module comprises at least two working states;

[0008] The power consumption control circuit is configured to trigger the analog-to-digital converter in the sleep state to receive the digital signal transmitted by the analog-to-digital converter when the analog power consumption control module is in the low-power consumption state, and determine whether the digital signal is abnormal according to the preset parameter, and if so, generate a result abnormal signal, and if not, generate a result normal signal and keep the low-power consumption state of the analog power consumption control module for the next working cycle.

[0009] The output module is configured to receive and send the result abnormal signal to an external detection module.

[0010] Optionally, the low-power consumption wake-up device further comprises a system power consumption controller connected with the output end of the power consumption control circuit and the enable end of the power consumption control circuit.

[0011] When the system power consumption controller receives the result abnormal signal, the system power consumption controller is configured to switch the analog power consumption control module from the low-power consumption state to a high-power consumption state according to the result abnormal signal to participate in the abnormal processing of the integrated control system.

[0012] The system power consumption controller is further configured to adjust the analog power consumption control module to the low-power consumption state after the abnormal processing is completed.

[0013] Optionally, the system power consumption controller is configured to receive and send an enable control instruction to the power consumption control circuit according to an external sleep / wake-up request to adjust the working state of the analog power consumption control module and reduce the power consumption of the integrated control system.

[0014] Optionally, the power consumption control circuit comprises a timer, a clock controller and a result comparison module, the output end of the timer is connected with the input end of the clock controller, the output end of the clock controller is connected with the clock end of the result comparison module, the output end of the result comparison module is connected with the input end of the clock controller and the input end of the output module, and the input end of the result comparison module is connected with the output end of the analog-to-digital converter.

[0015] When the analog power consumption control module is in the low-power consumption state, the result comparison module is in the sleep state.

[0016] Optionally, the timer is configured to generate a wake-up signal to drive the clock controller to generate a clock signal to enable the result comparison module and the analog-to-digital converter when the preset value is reached at the current sampling time.

[0017] The analog-to-digital converter is configured to acquire and convert the analog signal into the digital signal.

[0018] The result comparison module is configured to determine whether the digital signal is abnormal based on the preset parameter, and if so, generate a result abnormal signal, and if not, generate a result normal signal.

[0019] Optionally, when the result normal signal is generated, the result comparison module is further configured to send a comparison completion signal to the clock controller after the comparison is completed;

[0020] The clock controller is configured to stop generating the clock signal after receiving the comparison completion signal until receiving the next wake-up signal.

[0021] Optionally, the result comparison module comprises a processing unit, at least one result comparator, each result comparator corresponding to one analog-to-digital converter; the input end of the result comparator is connected with the output end of each channel under the corresponding analog-to-digital converter; the output end of the clock controller is connected with the enable end of each result comparator; the output end of each result comparator is connected with the input end of the processing unit; the output end of the processing unit is connected with the input end of the clock controller and the input end of the output module;

[0022] For any result comparator, the result comparator is configured to receive the digital signals of each preset channel under the current analog-to-digital converter, and compare the digital signals with preset parameters to obtain a judgment result of each preset channel;

[0023] The processing unit is configured to obtain a result abnormal signal or a result normal signal according to the judgment result of each preset channel.

[0024] Optionally, the power consumption control circuit further comprises a flip-flop, the input end of the flip-flop is connected with the output end of the clock controller; the output end of the flip-flop is connected with the input end of the analog-to-digital converter;

[0025] The flip-flop is configured to receive and generate a trigger signal according to the clock signal to enable the analog-to-digital converter;

[0026] The analog-to-digital converter is configured to convert the analog signal into the digital signal when in the working state.

[0027] Optionally, the low-power wake-up device further comprises an input module, the input module comprises a plurality of input channels; each input module comprises a plurality of input channels; each input module corresponds to one analog-to-digital converter, and the output end of each input channel is connected with the input end of the corresponding analog-to-digital converter.

[0028] For any analog-to-digital converter, the analog-to-digital converter is configured to, when in the working state, send a control signal to the corresponding input module to adjust the on-off state of each input channel under the current input module, obtain the analog signal in the preset sampling sequence, and convert the analog signal into the digital signal;

[0029] The analog-to-digital converter is further configured to enter the dormant state after obtaining the digital signal.

[0030] In a second aspect, the application further provides an integrated control system comprising the low-power wake-up device of any one of the first aspect.

[0031] The low-power wake-up device and the integrated control system have the following beneficial effects:

[0032] The low-power wake-up device and the integrated control system have the following beneficial effects: BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced as follows. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0034] Figure 1 Structure diagram of the low-power wake-up device provided by the embodiments of the present application;

[0035] Figure 2 Structure diagram of the low-power wake-up device provided by the embodiments of the present application;

[0036] Figure 3 Structure diagram of the power consumption control circuit provided by the embodiments of the present application;

[0037] Figure 4 Structure diagram of the power consumption control circuit provided by the embodiments of the present application;

[0038] Figure 5 Structure diagram of the result comparison module provided by the embodiments of the present application;

[0039] Figure 6 Structure diagram of the result comparison module provided by the embodiments of the present application;

[0040] Figure 7 Structure diagram of the low-power wake-up device provided by the embodiments of the present application;

[0041] Icon: 10 - low power wake-up device; 101 - analog-digital power consumption control module; 102 - output module; 103 - system power consumption controller; 104 - input module; 201 - power consumption control circuit; 202 - analog-digital converter; 301 - timer; 302 - clock controller; 303 - result comparison module; 304 - flip-flop; 401 - result comparator; 401A - first result comparator; 401B - second result comparator; 402 - processing unit. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0043] Please refer to Figure 1 , Figure 1 The structure of the low power wake-up device in the embodiments of the present application is shown in the schematic diagram, which is applied to an integrated control system and includes an output module 102 and an analog-digital power consumption control module 101. For any analog-digital power consumption control module 101, the analog-digital power consumption control module 101 includes a power consumption control circuit 201 and a plurality of analog-digital converters 202.

[0044] The input end of the power consumption control circuit 201 is connected with the output end of each analog-digital converter 202, and the output end of the power consumption control circuit 201 is connected with the enable end of the analog-digital converter 202 and the input end of the output module 102.

[0045] The analog-digital power consumption control module 101 includes at least two working states.

[0046] For any working period, when the analog-digital power consumption control module 101 is in a low power working state, the power consumption control circuit 201 is used to trigger the analog-digital converter in a sleep state to receive the digital signal transmitted by the analog-digital converter, and to determine whether the digital signal is abnormal according to a preset parameter. If yes, a result abnormal signal is generated; if not, a result normal signal is generated, and the analog-digital power consumption control module remains in the low power working state and enters the next working period.

[0047] The output module 102 is used to receive and send the result abnormal signal to an external detection module.

[0048] It should be noted that the analog-digital power consumption control module in the embodiments includes a low power working state and a high power working state, and the working states of the modules are different in each working state.

[0049] Taking the low-power working state as an example, each high-power module in the analog-digital power consumption control module, such as the analog-digital converter and the power consumption control circuit, is in the low-power working state, that is, in the sleep state, and is awakened at a fixed time. When in the high-power working state, each module is in the normal working mode and does not need to be awakened at a fixed time.

[0050] For any analog-digital power consumption control module, when the analog-digital power consumption control module is in the low-power working state, the analog-digital converter in the sleep state can be triggered by the power consumption control circuit at a fixed time, and when it is determined that the current digital signal is in the normal state, the analog-digital power consumption control module remains in the current low-power working state and enters the next working period.

[0051] It should be noted that the power consumption control circuit includes but is not limited to the functions of fixed triggering and digital signal determination. Based on this, the power consumption control circuit in this embodiment is triggered in a partial triggering manner, that is, only when the analog-digital power consumption control module is in the low-power working state, the analog-digital converter is triggered to convert the digital signal in a fixed wake-up manner, and the power consumption control circuit itself only performs the functions of fixed triggering and digital signal determination, rather than awakening all power modules to normally perform all working functions as in the normal working mode.

[0052] The number of analog-digital converters in the analog-digital power consumption control module is not limited in this embodiment, so as to support flexible and self-definable analog-digital converter acquisition sequences and corresponding comparison references, and to meet the range monitoring of external analog signals in various application scenarios.

[0053] On this basis, the application can also realize periodic detection of the analog signal and monitoring output through the output module.

[0054] Please refer to Figure 1 on this basis, refer to Figure 2 , Figure 2 Another structural schematic diagram of the low-power wake-up device in this embodiment is shown; the low-power wake-up device 10 further includes a system power consumption controller 103; the system power consumption controller 103 is connected with the output end and the enable end of the power consumption control circuit 201.

[0055] When the system power consumption controller receives the result exception signal, the system power consumption controller 103 is used for receiving and sending an enable control instruction to the power consumption control circuit according to the result exception signal, so as to switch the analog-digital power consumption control module from the low-power working state to the high-power working state to participate in the exception processing of the integrated control system.

[0056] The system power consumption controller 103 is also used for switching the analog-digital power consumption control module from the high-power working state to the low-power working state after the exception processing is completed.

[0057] Based on this, the application also sends an enable control to the enable end of the power consumption control circuit when the result exception signal is received, switches the working mode of the analog-digital power consumption control module, i.e., switches from the low-power working state to the high-power working state, to participate in the exception detection of the integrated control system, and ensures the normal working of the integrated control system. Meanwhile, after the exception processing is finished, the system power consumption controller also switches the analog-digital power consumption control module from the high-power working state to the low-power working state, to ensure the low-power process of the integrated control system.

[0058] It should be noted that the embodiment does not limit the processing mode of the integrated control system after the system power consumption controller receives the result exception signal, as long as the system power consumption controller adjusts the working state of the analog-digital power consumption control module after receiving the result exception signal, so that the power consumption control circuit and the analog-digital converter enter the normal working state, i.e., from the low-power state to the high-power state, to participate in the exception processing process.

[0059] In the embodiment, the system power consumption controller 103 is also used for receiving and sending an enable control instruction to the power consumption control circuit according to an external sleep / wakeup request, to adjust the working state of the analog-digital power consumption control module itself and reduce the power consumption of the integrated control system.

[0060] In the embodiment, the external sleep / wakeup request can be a control request of the integrated control system MCU level, or a sleep / wakeup request from the user side.

[0061] Please refer to Figure 1 on the basis of Figure 3 , Figure 3 Fig. 1 shows the structure of the power consumption control circuit in the embodiment; the power consumption control circuit 201 in the embodiment includes a timer 301, a clock controller 302, and a result comparison module 303; the output end of the timer 301 is connected with the input end of the clock controller 302; the output end of the clock controller 302 is connected with the clock end of the result comparison module 303; the output end of the result comparison module 303 is connected with the input end of the clock controller 302 and the input end of the output module 102; the input end of the result comparison module 303 is connected with the output end of the analog-digital converter 202.

[0062] When the analog-digital power consumption control module 101 is in the low-power working state, the result comparison module 303 is in the sleep state.

[0063] In the embodiment, the timer 301 is used for generating a wakeup signal after the preset value at the current sampling time is reached, to drive the clock controller to generate a clock signal, to enable the result comparison module and the analog-digital converter.

[0064] It should be noted that the clock signal generated by the clock controller in this embodiment indirectly triggers the power supply of the analog-digital converter 202, that is, after receiving the clock signal, the analog-digital converter 202 enters a working mode: acquires and converts the analog signal into a digital signal, and sends the digital signal to the result comparison module.

[0065] Subsequently, the result comparison module 303 judges whether the above-mentioned digital signal is abnormal based on the preset parameters, and if so, generates a result abnormal signal; if not, generates a result normal signal.

[0066] In this embodiment, when the result normal signal is generated, in order to further ensure the low-power operation of the integrated control system, the power consumption control circuit and the analog-digital converter need to be timely cut off.

[0067] In one possible implementation, after the result comparison module completes the comparison of all digital signals, it will send a comparison completion signal to the clock controller, at this time, the analog-digital converter and the result comparison module can enter a sleep state. The clock controller stops generating the clock signal after receiving the comparison completion signal until the next wake-up signal is received.

[0068] Based on this, the power consumption control circuit in this embodiment can periodically wake up itself and the analog-digital converter to perform a group of sampling conversion and obtain a group of conversion results, and generate a result abnormal signal according to the conversion results, and control itself and the analog-digital converter to enter a low-power state again after all result detection is completed.

[0069] Please refer to Figure 4 , Figure 4 The structure schematic diagram of the power consumption control circuit in this embodiment is shown; the power consumption control circuit 201 further includes a flip-flop 304, the input end of the flip-flop 304 is connected with the output end of the clock controller 302; the output end of the flip-flop 304 is connected with the input end of the analog-digital converter 202.

[0070] The flip-flop 304 is used for receiving and generating a trigger signal according to the clock valid signal sent by the clock controller, so as to enable the analog-digital converter.

[0071] The analog-digital converter 202 is used for converting the analog signal into a digital signal when in a working state.

[0072] In this embodiment, the clock controller further sends a clock valid signal to the flip-flop, so that after the flip-flop receives the clock signal, it further generates a trigger signal to enable the analog-digital converter, so as to control the power supply of the analog-digital converter.

[0073] The trigger signal in the embodiment drives the analog reference power supply in the analog-digital converter and other high-power analog circuits to work, provides power for the conversion process of the analog-digital converter, and thus completes the sampling and conversion of the analog signal.

[0074] In the embodiment, when the analog-digital power consumption control module is in the low-power consumption state, the clock or power supply of the high-power consumption module is in the closed state, that is, the clock controller, the result comparator module, the flip-flop and other structures in the power consumption control circuit, and the analog-digital converter are in the dormant state. After the timer reaches the preset time, the partial wake-up signal is sent to the clock controller, and then the clock signal is sent to the flip-flop, the result comparator and the like through the clock controller, the analog-digital converter is driven to work, and the result comparator performs digital signal comparison.

[0075] The specific working principle can be that the timer can generate a periodic partial wake-up signal and send it to the clock controller to wake up the clock controller to generate a clock signal, which can be used as the working clock of the analog-digital converter and the result comparator. When the clock signal is generated, the clock valid signal is output to the flip-flop, the flip-flop further generates a trigger signal and sends it to the analog-digital converter to enable the analog reference power supply and other high-power analog circuits, so that the analog-digital converter works in the working state and completes the analog signal acquisition and conversion.

[0076] It should be noted that, in order to further ensure the low-power consumption operation of the integrated control system, when the analog-digital converter 202 completes a group of sampling conversion, that is, after completing the corresponding analog signal acquisition in a sampling period, the above-mentioned analog reference power supply and other high-power analog circuits will enter the dormant state, waiting for the next clock signal trigger.

[0077] Correspondingly, when the result comparator completes the digital signal comparison, a comparison completion signal is generated, at this time, the clock controller stops sending the clock signal, waiting for the corresponding wake-up signal in the next period.

[0078] Please refer to Figure 4 , Figure 5 , Figure 5 The structure of the result comparison module in the embodiment is shown in the structure diagram; the result comparison module 303 in the embodiment includes a processing unit 402 and at least one result comparator 401. Each result comparator 401 corresponds to an analog-digital converter 202. The input end of each result comparator 401 is connected with the output end of the corresponding analog-digital converter 202.

[0079] The output end of the clock controller 302 is connected with the enable end of each result comparator 401; the output end of each result comparator 401 is connected with the input end of the processing unit 402; the output end of the processing unit 402 is connected with the input end of the clock controller 302 and the input end of the output module 102.

[0080] The result comparator 401 is configured to receive the digital signal of each preset channel under the current analog-to-digital converter and compare the digital signal with the preset parameter to obtain a judgment result of each preset channel.

[0081] The processing unit 402 is configured to obtain a result abnormal signal or a result normal signal according to the judgment result of each preset channel.

[0082] When the result comparison module includes two result comparators, please refer to Figure 5 , Figure 6 , Figure 6 Fig. 6 shows another structural schematic diagram of the result comparison module in the embodiment; the result comparison module 303 includes a first result comparator 401A and a second result comparator 401B; the input end of the first result comparator 401A is connected with the output end of the corresponding analog-to-digital converter 202; the input end of the second result comparator 401B is connected with the output end of the corresponding analog-to-digital converter 202; the output end of the first result comparator 401A and the output end of the second result comparator 401B are connected with the input end of the processing unit 402; the output end of the processing unit 402 is connected with the input end of the clock controller 302 and the input end of the output module 102.

[0083] In a possible implementation manner, the analog-to-digital converter includes a plurality of data channels, and the preset channel is used to represent the output channel of the digital signal in the current acquisition process; the embodiment does not limit the number of the preset channel, that is, the corresponding analog-to-digital converter can use the digital signal of one data channel, or can acquire the results of a plurality of different data channels, so that the result comparator can compare the results of each preset channel respectively to obtain the data information that the digital signal of the current data channel is in an abnormal state or a normal state.

[0084] Correspondingly, the processing unit receives and records all comparison results and compares all comparison results to obtain a final result abnormal signal or a result normal signal.

[0085] After the processing unit in the embodiment performs the final processing judgment, the processing unit will also send a comparison completion signal to the clock controller 302 to make the clock controller 302 stop sending the clock signal to the outside. Meanwhile, in order to further ensure the low-power operation of the integrated control system, each result comparator in the embodiment will automatically enter a sleep state after completing the current result comparison processing, waiting for the clock signal to trigger in the next sampling period.

[0086] It should be noted that the embodiment is not limited to the plurality of configurable reference digital quantities predefined in each result comparator. That is, the digital reference quantity corresponding to each conversion result can be different or the same according to application requirements, and can be predefined by software. The comparison direction (greater than or less than) corresponding to each conversion result can also be predefined by software to achieve flexible range or size detection.

[0087] In one possible implementation, when the result comparison module 303 includes only two digital quantities, which are defined as a high reference value (HT) and a low reference value (LT), it is assumed that any result comparator 401 can support a set of up to 8 comparison threshold values, which can be defined as TSEL0, TSEL1,..., TSEL7, respectively. Among them, TSELx=0 indicates that the high reference value HT is selected as the comparison reference, and TSELx=1 indicates that the low reference value LT is selected as the comparison reference. Correspondingly, the result comparison module 303 in the embodiment also supports a set of up to 8 comparison directions, i.e., value size judgment, and the above 8 comparison directions can be defined as FSEL0,..., FSEL7. Among them, FSELx=0 indicates greater than or equal to, i.e., ">="; and FSELx=1 indicates less than or equal to, i.e., "<".

[0088] Based on this, the result comparison module 303 in the embodiment can flexibly configure the comparison reference value and / or the comparison direction used for judgment according to application requirements to obtain the comparison results between the digital signals.

[0089] The processing unit 402 in the embodiment records each comparison result of each result comparator 401 in turn, and compares it with the predefined normal result (for example, the normal result is all 0) to finally determine whether there is an abnormal conversion result. If there is an abnormal result (any comparison result is 1), an abnormal result signal will be generated. Whether the final result is abnormal or not, a comparison completion signal will be given when all comparisons are completed.

[0090] In summary, the result comparison module 303 in the embodiment uses a hardware implementation to achieve result comparison, and only stores the comparison results instead of the conversion results, thereby avoiding the additional power consumption caused by waking up the entire system for software comparison. At the same time, the result comparison module 303 can also combine the self-defined sequential acquisition of the external multiple analog signals and the plurality of configurable reference digital quantities, or even combine multiple sets of analog-to-digital converters 202 and result comparators 401 to flexibly achieve boundary detection of a specific analog signal, such as whether it is overvoltage, undervoltage, within a range, or outside a range.

[0091] Please refer to Figure 7 , Figure 7Fig. 7 shows another structural schematic diagram of the low-power wake-up device in the embodiment; the low-power wake-up device 10 further comprises input modules 104, each of which comprises a plurality of input channels; each input module corresponds to an analog-to-digital converter 202, and the output end of each input channel is connected to the input end of the corresponding analog-to-digital converter 202.

[0092] Taking any analog-to-digital converter as an example, the analog-to-digital converter 202 is configured to, when in the working state, send a control signal to the corresponding input module 104 to adjust the on-off state of each input channel under the current input module 104, and obtain analog signals in a preset sampling sequence; and convert the analog signals into digital signals.

[0093] The analog-to-digital converter 202 is further configured to, after obtaining the digital signals, enter the sleep state.

[0094] It should be noted that the embodiment does not limit the conversion length and conversion channel that the analog-to-digital converter 202 can implement, and the setting and selection, i.e., the corresponding preset sampling sequence, depend on the application requirements.

[0095] In a possible implementation manner, when the analog-to-digital converter 202 in the embodiment can support a group of maximum 8 sequential analog signal conversions, the input module 104 correspondingly comprises 8 input channels, and the corresponding numbers of the input channels are represented as CH0, CH1,..., CH7. If it is assumed that the digital conversion length is 4, at this time, the analog-to-digital converter 202 can simultaneously convert the analog signals of the input channels numbered CH0, CH1, CH2, and CH3, or convert the channels numbered CH0, CH0, CH1, and CH1, at this time, the analog-to-digital converter 202 is configured to continuously sample the input channels numbered CH0 and CH1, and the sampling number is 2.

[0096] On this basis, it is assumed that the analog-to-digital converter 202 converts the input channels numbered CH0, CH1, CH2, and CH3, when the result comparison module 303 only comprises the above two digital parameters, this group of comparisons can be defined as 4 comparisons, and the comparison results can be CH0 >= HT, CH1 >= HT, CH2 >= LT, and CH3 >= LT, respectively, that is, the over-range detection of the four analog inputs of the channels numbered CH0, CH1, CH2, and CH3 can be constituted.

[0097] Similar to the previous embodiment, assuming that the input channel numbers of the analog-to-digital converter 202 include CH0, CH0, CH1, CH1, this set of comparisons can be defined as 4 comparisons, and the comparison results can be: CH0 >= HT, CH0 < LT, CH1 >= HT, CH1 < LT, that is, the over-limit detection of the two analog inputs of the channel numbered CH0 and the channel numbered CH1 is formed.

[0098] In summary, on the basis of Figure 7 The working principle of the low-power wake-up device in the embodiment is as follows:

[0099] The system power consumption controller receives and enables the low-power wake-up device to enter the sleep mode according to the external sleep request; at this time, the clock or power supply of the high-power module is turned off, and the corresponding analog-to-digital converter and result comparison module stop working.

[0100] The power consumption control circuit enters the working mode, and after counting to the specified time, generates a partial wake-up signal; the clock controller receives and sends the clock signal to the result comparison module and the clock valid signal to the flip-flop according to the partial wake-up signal, on the basis of which the analog-to-digital converter and the result comparison module enter the normal working state, wherein the analog-to-digital converter will gate the collection channel according to the preset rule to receive the analog signal in the preset order, and convert the analog signal into a digital signal. At the same time, the result comparison module will receive the above-mentioned digital signal, make an abnormality judgment, and obtain the conversion abnormality / normality judgment result.

[0101] When in normal conversion, the result comparison module will send a comparison completion signal to the clock controller, and correspondingly, the analog-to-digital converter and the result comparison module will enter the sleep state after completing their own work, waiting for the arrival of the clock signal in the next cycle.

[0102] When in abnormal conversion, the result comparison module will send a result abnormality signal to the output module and the system power consumption controller, and correspondingly, the output module will output the result abnormality signal to the outside, and the system power consumption controller will send an enable signal to the power consumption control circuit to switch the analog power consumption control module from the low-power working state to the high-power working state, participate in the abnormality processing of the integrated control system, and then switch the analog power consumption control module from the high-power working state to the low-power working state after the abnormality processing is completed.

[0103] Based on the same inventive concept, the embodiment of the present application also provides a low-power wake-up system, which includes the low-power wake-up device of any one of the first aspect.

[0104] Based on this, the application uses the partial wake-up analog-digital converter and the result comparison module timed by the power consumption control circuit instead of the entire integrated control system, and can realize the periodic monitoring of the multiple analog signals from the outside by setting multiple analog-digital converters, and only wakes up the entire integrated control system when an abnormality is detected, greatly reducing the average power consumption of the integrated control system. Based on this, the application can reduce the design difficulty and application cost without additionally designing a low-power ADC and the corresponding subsystem or using an off-chip detection circuit.

[0105] In the embodiments provided by the present application, it should be understood that the disclosed device and method can be implemented in other manners. The described device embodiments are merely schematic, and the division of units is merely a logical function division. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0106] In addition, the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. In actual implementation, some or all of the units can be selected according to the actual needs to achieve the purposes of the embodiments of the present application.

[0107] In addition, each functional module in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0108] It should be noted that if the functions are realized in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0109] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0110] The above description is merely illustrative of the application and not in limitation of the principles of the application. Numerous modifications and adaptations thereof will be readily apparent to those skilled in the art without departing from the spirit and scope of the application as defined in the following claims.

Claims

1. A low-power wake-up device applied to an integrated control system, characterized in that, The low-power wake-up device comprises an output module and an analog-digital power consumption control module; the analog-digital power consumption control module comprises a power consumption control circuit and at least one analog-digital converter; an input end of the power consumption control circuit is connected with an output end of each of the analog-digital converters; an output end of the power consumption control circuit is connected with an enable end of the analog-digital converter and an input end of the output module; wherein the analog-digital power consumption control module comprises at least two working states; for any working period, when the analog-digital power consumption control module is in a low-power working state, the power consumption control circuit is configured to trigger the analog-digital converter in a dormant state at a regular time to receive a digital signal transmitted by the analog-digital converter; and determine whether the digital signal is abnormal according to a preset parameter, if yes, generate a result abnormal signal; if not, generate a result normal signal, and keep the low-power working state of the analog-digital power consumption control module, and enter the next working period; the output module is configured to receive and send the result abnormal signal to an external detection module; the low-power wake-up device further comprises a system power consumption controller; the system power consumption controller is connected with the output end of the power consumption control circuit and the enable end of the power consumption control circuit; when the system power consumption controller receives the result abnormal signal, the system power consumption controller is configured to receive and switch the analog-digital power consumption control module from the low-power working state to a high-power working state according to the result abnormal signal, to participate in abnormal processing of the integrated control system; the system power consumption controller is further configured to adjust the analog-digital power consumption control module to the low-power working state after the abnormal processing is completed.

2. The low-power wake-up device according to claim 1, wherein the system power consumption controller is configured to receive and send an enable control instruction to the power consumption control circuit according to an external sleep / wake-up request, to adjust the working state of the analog-digital power consumption control module itself, and reduce the power consumption of the integrated control system.

3. The low power wake-up device of claim 1, wherein, the power consumption control circuit comprises a timer, a clock controller and a result comparison module; an output end of the timer is connected with an input end of the clock controller; an output end of the clock controller is connected with a clock end of the result comparison module; an output end of the result comparison module is connected with an input end of the clock controller and an input end of the output module; an input end of the result comparison module is connected with an output end of the analog-digital converter; wherein, when the analog-digital power consumption control module is in the low-power working state, the result comparison module is in a dormant state.

4. The low-power wake-up device according to claim 3, wherein the timer is configured to generate a wake-up signal after a preset value is reached at a current sampling time, to drive the clock controller to generate a clock signal, to enable the result comparison module and the analog-digital converter; the analog-digital converter is configured to acquire and convert an analog signal into a digital signal; the result comparison module is configured to acquire and determine whether the digital signal is abnormal based on a preset parameter, if yes, generate a result abnormal signal; if not, generate a result normal signal.

5. The low-power wake-up device of claim 4, wherein, when the result normal signal is generated, the result comparison module is further configured to send a comparison completion signal to the clock controller after completion of the comparison; the clock controller is configured to stop generating the clock signal after receiving the comparison completion signal until receiving a next wake-up signal.

6. The low power wake-up device of claim 3, wherein, The result comparison module comprises a processing unit, at least one result comparator, each result comparator corresponding to one analog-to-digital converter; the input end of the result comparator is connected with the output end of each channel under the corresponding analog-to-digital converter; the output end of the clock controller is connected with the enable end of each result comparator; the output end of each result comparator is connected with the input end of the processing unit; the output end of the processing unit is connected with the input end of the clock controller and the input end of the output module; For any result comparator, the result comparator is configured to receive digital signals of each preset channel under the current analog-to-digital converter, and compare the digital signals with preset parameters to obtain a judgment result of each preset channel; the processing unit is configured to obtain the judgment result of each preset channel and obtain a result abnormal signal or a result normal signal according to the judgment result.

7. The low power wake-up device of claim 3, wherein, The power consumption control circuit further comprises a flip-flop, the input end of the flip-flop is connected with the output end of the clock controller; the output end of the flip-flop is connected with the input end of the analog-to-digital converter; the flip-flop is configured to receive and generate a trigger signal according to the clock signal output by the clock controller to enable the analog-to-digital converter; the analog-to-digital converter is configured to convert the analog signal into the digital signal when in the working state.

8. The low power wake-up device of claim 1, wherein, The low-power wake-up device further comprises a plurality of input modules, each input module comprising a plurality of input channels; each input module corresponds to one analog-to-digital converter, and the output end of each input channel is connected with the input end of the corresponding analog-to-digital converter; for any analog-to-digital converter, the analog-to-digital converter is configured to, when in the working state, send a control signal to the corresponding input module to adjust the on-off state of each input channel under the current input module, obtain analog signals in a preset sampling sequence, and convert the analog signals into digital signals; the analog-to-digital converter is further configured to enter a dormant state after obtaining the digital signals.

9. An integrated control system, characterized by The low-power wake-up device comprises the low-power wake-up device of any one of claims 1 to 8.

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