Branch prediction processing system, method for reducing branch prediction power consumption, and storage medium

Abstract

The application relates to a branch prediction processing system, a method for reducing branch prediction power consumption and a storage medium, the system and the method comprising a first-stage multiplexer, a multi-stage branch target buffer module, a path prediction judgment module and a second-stage multiplexer, the multi-stage branch target buffer module comprising a plurality of branch target buffer sub-modules, each of the branch target buffer sub-modules being provided with an additional preset path prediction mark field. In the application, the branch target buffer is split into a plurality of small-size branch target buffer sub-modules, only the branch target buffer sub-modules corresponding to the marks are activated to be in a normal power consumption mode and in a read mode in the path prediction process, and the remaining sub-modules remain in a low power consumption state, so that the invalid cache access power consumption can be reduced, the overall circuit activity rate can be reduced, and the power consumption optimization of a processor system can be realized.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of processor technology, and particularly relates to a branch prediction processing system, a method for reducing branch prediction power consumption and a storage medium. BACKGROUND

[0002] Branch prediction is a technique used in modern processors to improve execution efficiency. Since conditional branches can cause the processor to be unable to determine the address of the next instruction until the branch instruction is executed, this can cause the processor to wait, reducing execution efficiency. Branch prediction technology allows the processor to fetch and execute subsequent instructions in advance by predicting the result of the branch instruction. If the prediction is correct, the processor can seamlessly continue execution; if the prediction is incorrect, it needs to roll back to the correct path. The accuracy of branch prediction is crucial to processor performance.

[0003] When a high-performance central processing unit (CPU) front-end fetch pipeline encounters a branch instruction, in order to improve performance, it will predict the jump target address / jump direction based on branch history information and speculatively execute the branch instruction. After obtaining the branch jump address, the address will be passed to the instruction fetch module, which reads the instruction from the instruction cache and passes it to the instruction decoding module, which is handed over to the instruction execution module (also known as the execution back-end). If the branch prediction result is correct, the processor performance will be improved; otherwise, when the branch prediction is incorrect, the processor pipeline needs to clear the incorrectly executed instructions and revert to the execution state before the branch, which will cause the pipeline to stall for several clock cycles. Therefore, reducing the processor stall time after branch prediction failure will help improve performance.

[0004] Branch Target Buffer (BTB) is a hardware component used in modern processors to optimize branch prediction, and is one of the important techniques to improve branch prediction accuracy and reduce branch overhead. By storing and quickly retrieving branch target addresses, branch target cache helps improve processor performance and efficiency. Its core role is to store the target address of each branch instruction to avoid the processor having to recalculate the target address every time a branch jump is executed.

[0005] Generally, the common structure of branch target buffer is to include a large capacity, deep static random access memory (SRAM). According to the existing branch target buffer design, when the processor reads the branch target buffer, each time of reading data, the entire static random access memory is read, which causes each part of the static random access memory to be in a powered-on state, resulting in a large power consumption of the processor system in the branch prediction process, and having a certain influence on the PPA (Power, Performance, Area) performance of the central processor system as a whole. SUMMARY

[0006] The present application provides a branch prediction processing system, a method for reducing branch prediction power consumption and a storage medium, aiming at solving the technical problem of large power consumption of the existing branch target buffer architecture.

[0007] To solve the above technical problems, in a first aspect, the present application provides a branch prediction processing system, comprising a first level multiplexer, a multi-level branch target buffer module, a path prediction judgment module and a second level multiplexer, the multi-level branch target buffer module comprising a plurality of branch target buffer sub-modules, each branch target buffer sub-module having an additional preset path prediction marker field, wherein:

[0008] The first level multiplexer is used to obtain instruction address information and branch target buffer path prediction information transmitted from the processor pipeline, and set the branch target buffer sub-module having the corresponding preset path prediction marker field to a normal power consumption mode and open the read mode according to the branch target buffer path prediction information and the re-reading marker information, and then transmit the instruction address information to the branch target buffer sub-module, the re-reading marker information being generated by the second level multiplexer; the first level multiplexer is also used to transmit the table lookup result returned by the multi-level branch target buffer module to the path prediction judgment module;

[0009] The multi-level branch target buffer module is used to perform table lookup of branch target address in the corresponding branch target buffer sub-module according to the instruction address information, obtain the table lookup result, and return the table lookup result to the first level multiplexer;

[0010] The path prediction judgment module is used to compare the instruction address information and the table lookup result, obtain the path prediction result about whether the instruction address information and the table lookup result are equal, and transmit the path prediction result to the second level multiplexer;

[0011] The second-stage multiplexer is used to output the path prediction result or the lookup table result to the first-stage multiplexer or the processor pipeline based on the path prediction result, wherein: if the path prediction result indicates that the instruction address information and the lookup table result are equal, then the lookup table result is output to the processor pipeline; if the path prediction result indicates that the instruction address information and the lookup table result are not equal, then the path prediction result and the reread flag information are output to the first-stage multiplexer, and a reread is performed.

[0012] Furthermore, in the multi-level branch target cache module, the number of branch target cache sub-modules is defined as N1, N1≥2, and N1 is an integer. The lowest N2 bits of the branch target address stored in each branch target cache sub-module are used as a preset path prediction mark field to identify address alias conflicts, N2≥log2(N1), and N2 is an integer.

[0013] Define the bit width of each branch target cache submodule as N3, where N3 > N2 and N3 is an integer. Use (N3-N2) bits from the branch target address stored in each branch target cache submodule as the retrieval address bit width. The cache depth of each branch target cache submodule is less than or equal to 2. (N3-N2) .

[0014] Furthermore, when the path prediction and determination module compares the instruction address information with the lookup table result, it compares the lowest N2 bits of the address corresponding to the instruction address information and the lookup table result.

[0015] Furthermore, the multi-level branch target cache module is also used for:

[0016] Based on the highest (N3-N2) bits of the instruction address information, a lookup table is performed in the corresponding branch target cache submodule to find the highest (N3-N2) bits of the branch target address.

[0017] Each piece of data read contains an alias identification field, which has N2 bits.

[0018] The least N2 bits of the instruction address information are compared with the N2 bits of the alias identification field read from the branch target cache submodule, where:

[0019] The least N2 bits of the instruction address information are compared with the N2 bits of the alias identification field read from the lookup table in the branch target cache submodule:

[0020] If the two are the same, the corresponding branch target address will be output as the lookup result.

[0021] If the two are different, a missing data marker is generated and output as the lookup result.

[0022] Furthermore, the first-stage multiplexer is also used for:

[0023] Based on the branch target cache path prediction information, one of the branch target cache sub-modules with the corresponding path prediction flag field is set to normal power mode, and the remaining branch target cache sub-modules are set to low power mode.

[0024] Furthermore, the first-stage multiplexer is also used for:

[0025] Upon initial read, the instruction address information is sent to the corresponding multi-level branch target cache module. If the initial read fails, subsequent reads will simultaneously perform a lookup of the branch target address in all branch target cache submodules based on the instruction address information.

[0026] Furthermore, the first-stage multiplexer is also used for:

[0027] It simultaneously receives data from the processor pipeline and the second-stage multiplexer, and prioritizes processing data transmitted from the second-stage multiplexer.

[0028] Secondly, the present invention also provides a method for reducing branch prediction power consumption, the method being implemented based on the branch prediction processing system described above, the method for reducing branch prediction power consumption comprising the following steps:

[0029] The branch predictor obtains the instruction address information and branch target cache path prediction information transmitted from the processor pipeline, and transmits the instruction address information and the branch target cache path prediction information to the first-stage multiplexer.

[0030] The first-stage multiplexer obtains the instruction address information and branch target cache path prediction information transmitted from the processor pipeline. Based on the branch target cache path prediction information and reread flag information, the branch target cache submodule with the corresponding preset path prediction flag field is set to read mode. Then, the instruction address information is transmitted to the branch target cache submodule. The reread flag information is generated by the second-stage multiplexer.

[0031] The multi-level branch target cache module performs a lookup of the branch target address in the corresponding branch target cache sub-module based on the instruction address information, obtains the lookup result, and returns the lookup result to the first-level multiplexer.

[0032] The lookup result returned by the multi-level branch target cache module is transmitted to the path prediction and determination module through the first-level multiplexer;

[0033] The path prediction determination module compares the instruction address information with the lookup table result to obtain a path prediction result regarding whether the instruction address information and the lookup table result are equal, and then transmits the path prediction result to the second-level multiplexer.

[0034] The second-stage multiplexer outputs either the path prediction result or the lookup table result to the first-stage multiplexer or the processor pipeline based on the path prediction result. Specifically: if the path prediction result indicates that the instruction address information and the lookup table result are equal, then the lookup table result is output to the processor pipeline; if the path prediction result indicates that the instruction address information and the lookup table result are not equal, then the path prediction result and the reread flag information are output to the first-stage multiplexer, and a reread is performed.

[0035] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a program for reducing branch prediction power consumption stored in the memory and executable on the processor, wherein the processor, when executing the program for reducing branch prediction power consumption, implements the steps of the method for reducing branch prediction power consumption as described in any of the above embodiments.

[0036] Fourthly, the present invention also provides a storage medium storing a program for reducing branch prediction power consumption, wherein when the program for reducing branch prediction power consumption is executed by a processor, it implements the steps of the method for reducing branch prediction power consumption as described in any of the above embodiments.

[0037] The beneficial effect achieved by this invention is that it proposes a branch prediction processing system based on a multi-level branch target cache. This system divides the branch target cache into multiple small-sized branch target cache sub-modules. During the path prediction process, only the corresponding marked branch target cache sub-module is activated in normal power consumption mode and read mode is enabled, while the other sub-modules remain in low power consumption state. This can reduce the power consumption of invalid cache access, reduce the overall circuit activity, and achieve power optimization of the processor system. Attached Figure Description

[0038] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0039] Figure 1 This is a schematic diagram of the branch prediction processing system provided in an embodiment of the present invention;

[0040] Figure 2 This is a flowchart of the steps of the method for reducing branch prediction power consumption provided in the embodiments of the present invention;

[0041] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0043] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the branch prediction processing system provided in an embodiment of the present invention. The branch prediction processing system 100 includes a first-level multiplexer 101, a multi-level branch target cache module 102, a path prediction determination module 103, and a second-level multiplexer 104. The multi-level branch target cache module 102 includes multiple branch target cache sub-modules 1021 (…). Figure 1 (Taking three as an example), each of the branch target cache submodules 1021 has an additional preset path prediction tag field, wherein:

[0044] The first-stage multiplexer 101 is used to acquire instruction address information and branch target cache path prediction information transmitted from the processor pipeline, and set the branch target cache submodule 1021 with the corresponding preset path prediction flag field to normal power consumption mode and enable read mode according to the branch target cache path prediction information and reread flag information. Then, the instruction address information is transmitted to the branch target cache submodule 1021. The reread flag information is generated by the second-stage multiplexer 104. The first-stage multiplexer 101 is also used to transmit the lookup result returned by the multi-stage branch target cache module to the path prediction determination module 103.

[0045] The multi-level branch target cache module 102 is used to perform a lookup of the branch target address in the corresponding branch target cache sub-module 1021 according to the instruction address information, obtain the lookup result, and return the lookup result to the first-level multiplexer 101;

[0046] The path prediction determination module 103 is used to compare the instruction address information with the lookup table result to obtain a path prediction result regarding whether the instruction address information and the lookup table result are equal, and transmit the path prediction result to the second-level multiplexer 104;

[0047] The second-stage multiplexer 104 is used to output the path prediction result or the lookup table result to the first-stage multiplexer 101 or the processor pipeline based on the path prediction result, wherein: if the path prediction result indicates that the instruction address information and the lookup table result are equal, then the lookup table result is output to the processor pipeline; if the path prediction result indicates that the instruction address information and the lookup table result are not equal, then the path prediction result and the reread flag information are output to the first-stage multiplexer 101 and reread.

[0048] Specifically, in the multi-level branch target cache module 102, the number of branch target cache sub-modules 1021 is defined as N1, N1≥2, and N1 is an integer. The lowest N2 bits of the branch target address stored in each branch target cache sub-module 1021 are used as a preset path prediction mark field to identify address alias conflicts, N2≥log2(N1), and N2 is an integer.

[0049] The bit width of each branch target cache submodule 1021 is defined as N3, where N3 > N2 and N3 is an integer. The (N3-N2) bits of the branch target address stored in each branch target cache submodule 1021 are used as the retrieval address bit width. The cache depth of each branch target cache submodule 1021 is less than or equal to 2. (N3-N2) .

[0050] When the path prediction and determination module 103 compares the instruction address information and the lookup table result, it compares the lowest N2 bits of the address corresponding to the instruction address information and the lookup table result.

[0051] Based on the design in the above embodiments, when the path prediction determination module 103 performs the comparison, it first reads data based on the predicted preset path prediction mark field and verifies whether the prediction is correct. If the first prediction fails, it reads all branch target cache submodules 1021 in parallel to obtain data from the correct block. Since the lowest N2 bits of the address are used during the comparison, and the lowest N2 bits of the instruction address determine which branch target cache submodule 1021 the instruction's branch target should be stored in, it can be ensured that data can be read from the correct branch target cache submodule 1021 when the prediction is correct.

[0052] The multi-level branch target cache module 102 is also used for:

[0053] Based on the highest (N3-N2) bits of the instruction address information, a lookup table is performed in the corresponding branch target cache submodule 1021 to retrieve the highest (N3-N2) bits of the branch target address, and the read data containing the N2-bit alias identification field is retrieved, wherein:

[0054] The least N2 bits of the instruction address information are compared with the N2 bits of the alias identification field read from the lookup table in the branch target cache submodule 1021:

[0055] If the two are the same, the corresponding branch target address will be output as the lookup result.

[0056] If the two are different, a missing data marker is generated and output as the lookup result.

[0057] In this embodiment of the invention, the multi-level branch target cache module 102 has a two-level lookup strategy, wherein, based on the design in the above embodiment, the branch target address is divided into two parts:

[0058] The high-order bits (N3-N2) are used for quickly locating possible cache entries;

[0059] The lower-order N2 bits are used for precise matching and resolving alias conflicts.

[0060] Specifically, the above table lookup strategy works similarly to cache lookup in practice. First, data is read from the multi-way set-associative structure based on a partial address, and then a match is made.

[0061] The first-stage multiplexer 101 is also used for:

[0062] If the rereading flag information is empty, then according to the branch target cache path prediction information, one of the branch target cache submodules 1021 with the corresponding path prediction flag field is set to normal power mode, and the remaining branch target cache submodules 1021 are set to low power mode.

[0063] Based on the rereading tag information, the dynamic power consumption optimization strategy of the multi-level branch target cache module 102 in this embodiment of the invention can be realized. In most cases, since the path prediction of the system is correct, only the predicted branch target cache sub-module 1021 needs to be activated, and other blocks can enter a low-power mode to save energy.

[0064] Preferably, when path prediction errors occur (a rare occurrence), all branch target cache submodules 1021 need to be read in parallel. In this case, all blocks need to enter normal power consumption mode to ensure speed. By dynamically controlling the power consumption mode of each branch target cache submodule, the system can minimize power consumption while ensuring performance.

[0065] In this embodiment of the invention, the additionally set preset path prediction flag field has an arbitrary bit width. During system initialization, all fields can be configured to the same initial value, or they can be manually defined as any initial value. After each access to the branch target cache is completed, the access order is recorded using a lookup table. This lookup table is indexed by instruction address, and the table entries contain the number of the branch target cache submodule for the next instruction.

[0066] When a path prediction failure occurs, the branch target cache submodule 1021 of the next instruction is retrieved from the lookup table, and the data is written to the preset path prediction flag field, thereby realizing the dynamic update of the preset path prediction flag field.

[0067] The first-stage multiplexer 101 is also used for:

[0068] Upon first reading, the instruction address information is sent to the corresponding multi-level branch target cache module 102.

[0069] If the initial read fails and a subsequent read is performed, the branch target address is simultaneously looked up in all the branch target cache submodules 1021 based on the instruction address information.

[0070] In this embodiment of the invention, the reread flag information is set by the second-level multiplexer 104 when path prediction fails, to indicate that a second read is required. As described in the above embodiment, when path prediction is incorrect, the second-level multiplexer 104 needs to return information for rereading to read all branch target cache submodules in parallel to achieve data query.

[0071] The first-stage multiplexer 101 is also used for:

[0072] Simultaneously, it receives data from the processor pipeline and the second-stage multiplexer 104, prioritizing data from the second-stage multiplexer 104. This design implements data flow priority control in the branch prediction processing system 100, a key mechanism for ensuring system correctness and performance. Specifically, the first-stage multiplexer 101, as the data distribution hub of the branch prediction system, needs to handle two types of requests: normal prediction requests from the processor pipeline and error correction requests from the second-stage multiplexer 104. Error correction requests must be prioritized over normal prediction requests because branch prediction errors can cause pipeline churn and severe performance loss. Quickly processing error correction requests from the second-stage multiplexer 104 can minimize this loss, ensuring rapid recovery and reducing the performance degradation caused by branch prediction errors.

[0073] The beneficial effect achieved by this invention is that it proposes a branch prediction processing system based on a multi-level branch target cache. This system divides the branch target cache into multiple small-sized branch target cache sub-modules. During the path prediction process, only the corresponding marked branch target cache sub-module is activated in normal power consumption mode and read mode is enabled, while the other sub-modules remain in low power consumption state. This can reduce the power consumption of invalid cache access, reduce the overall circuit activity, and achieve power optimization of the processor system.

[0074] This invention also provides a method for reducing branch prediction power consumption. This method is implemented based on the branch prediction processing system described above. Please refer to [link / reference]. Figure 2 , Figure 2 This is a flowchart illustrating the steps of a method for reducing branch prediction power consumption provided in an embodiment of the present invention. The method for reducing branch prediction power consumption includes the following steps:

[0075] S201. Obtain instruction address information and branch target cache path prediction information transmitted from the processor pipeline through the first-stage multiplexer, and set the branch target cache submodule with the corresponding preset path prediction flag field to normal power consumption mode and enable read mode according to the branch target cache path prediction information and reread flag information. Then, transmit the instruction address information to the branch target cache submodule. The reread flag information is generated by the second-stage multiplexer.

[0076] S202. The multi-level branch target cache module performs a lookup of the branch target address in the corresponding branch target cache sub-module according to the instruction address information, obtains the lookup result, and returns the lookup result to the first-level multiplexer.

[0077] S203. The lookup result returned by the multi-level branch target cache module is transmitted to the path prediction and determination module through the first-level multiplexer.

[0078] S204. The path prediction determination module compares the instruction address information with the lookup table result to obtain a path prediction result regarding whether the instruction address information and the lookup table result are equal, and transmits the path prediction result to the second-level multiplexer.

[0079] S205. Based on the path prediction result, the second-stage multiplexer outputs the path prediction result or the lookup table result to the first-stage multiplexer or the processor pipeline, wherein: if the path prediction result indicates that the instruction address information and the lookup table result are equal, the lookup table result is output to the processor pipeline; if the path prediction result indicates that the instruction address information and the lookup table result are not equal, the path prediction result and the reread flag information are output to the first-stage multiplexer, and a reread is performed.

[0080] The method for reducing branch prediction power consumption can implement the corresponding functional steps based on the system for reducing branch prediction power consumption as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0081] This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a program for reducing branch prediction power consumption stored in the memory 302 and executable on the processor 301.

[0082] The processor 301 calls the program for reducing branch prediction power consumption stored in the memory 302 and executes the steps in the method for reducing branch prediction power consumption provided in this embodiment of the invention. Please refer to... Figure 3 Specifically, it includes the following steps:

[0083] S201. Obtain instruction address information and branch target cache path prediction information transmitted from the processor pipeline through the first-stage multiplexer, and set the branch target cache submodule with the corresponding preset path prediction flag field to normal power consumption mode and enable read mode according to the branch target cache path prediction information and reread flag information. Then, transmit the instruction address information to the branch target cache submodule. The reread flag information is generated by the second-stage multiplexer.

[0084] S202. The multi-level branch target cache module performs a lookup of the branch target address in the corresponding branch target cache sub-module according to the instruction address information, obtains the lookup result, and returns the lookup result to the first-level multiplexer.

[0085] S203. The lookup result returned by the multi-level branch target cache module is transmitted to the path prediction and determination module through the first-level multiplexer.

[0086] S204. The path prediction determination module compares the instruction address information with the lookup table result to obtain a path prediction result regarding whether the instruction address information and the lookup table result are equal, and transmits the path prediction result to the second-level multiplexer.

[0087] S205. Based on the path prediction result, the second-stage multiplexer outputs the path prediction result or the lookup table result to the first-stage multiplexer or the processor pipeline, wherein: if the path prediction result indicates that the instruction address information and the lookup table result are equal, the lookup table result is output to the processor pipeline; if the path prediction result indicates that the instruction address information and the lookup table result are not equal, the path prediction result and the reread flag information are output to the first-stage multiplexer, and a reread is performed.

[0088] The computer device 300 provided in this embodiment of the invention can implement the steps in the method for reducing branch prediction power consumption as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0089] This invention also provides a storage medium storing a program for reducing branch prediction power consumption. When the program for reducing branch prediction power consumption is executed by a processor, it implements the various processes and steps in the method for reducing branch prediction power consumption provided in this invention and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0090] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by instructing related hardware (such as mobile phones, computers, servers, air conditioners, or network devices, etc.) through a program that reduces branch prediction power consumption. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0091] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0092] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A branch prediction processing system, characterized in that, It includes a first-level multiplexer, a multi-level branch target cache module, a path prediction determination module, and a second-level multiplexer. The multi-level branch target cache module includes multiple branch target cache sub-modules, each of which has an additional preset path prediction flag field, wherein: The first-stage multiplexer is used to acquire instruction address information and branch target cache path prediction information transmitted from the processor pipeline, and set the branch target cache submodule with the corresponding preset path prediction flag field to normal power mode and enable read mode according to the branch target cache path prediction information and reread flag information. Then, the instruction address information is transmitted to the branch target cache submodule. The reread flag information is generated by the second-stage multiplexer. The first-stage multiplexer is also used to transmit the lookup result returned by the multi-stage branch target cache module to the path prediction determination module. The multi-level branch target cache module is used to perform a lookup of the branch target address in the corresponding branch target cache submodule according to the instruction address information, obtain the lookup result, and return the lookup result to the first-level multiplexer; The path prediction determination module is used to compare the instruction address information with the lookup table result to obtain a path prediction result regarding whether the instruction address information and the lookup table result are equal, and transmit the path prediction result to the second-level multiplexer; The second-stage multiplexer is used to output the path prediction result or the lookup table result to the first-stage multiplexer or the processor pipeline based on the path prediction result, wherein: if the path prediction result indicates that the instruction address information and the lookup table result are equal, then the lookup table result is output to the processor pipeline; if the path prediction result indicates that the instruction address information and the lookup table result are not equal, then the path prediction result and the reread flag information are output to the first-stage multiplexer, and a reread is performed.

2. The branch prediction processing system according to claim 1, characterized in that, In the multi-level branch target cache module, the number of branch target cache sub-modules is defined as N1, N1≥2, and N1 is an integer. The lowest N2 bits of the branch target address stored in each branch target cache sub-module are used as a preset path prediction mark field to identify address alias conflicts, N2≥log2(N1), and N2 is an integer. Define the bit width of each branch target cache submodule as N3, where N3 > N2 and N3 is an integer. Use (N3-N2) bits from the branch target address stored in each branch target cache submodule as the retrieval address bit width. The cache depth of each branch target cache submodule is less than or equal to 2. (N3-N2) .

3. The branch prediction processing system according to claim 2, characterized in that, When the path prediction and determination module compares the instruction address information with the lookup table result, it compares the lowest N2 bits of the address corresponding to the instruction address information and the lookup table result.

4. The branch prediction processing system according to claim 2, characterized in that, The multi-level branch target cache module is also used for: Based on the highest (N3-N2) bits of the instruction address information, a lookup table is performed in the corresponding branch target cache submodule to retrieve the highest (N3-N2) bits of the branch target address, and the read data containing the N2-bit alias identification field is retrieved, wherein: The least N2 bits of the instruction address information are compared with the N2 bits of the alias identification field read from the lookup table in the branch target cache submodule: If the two are the same, the corresponding branch target address will be output as the lookup result. If the two are different, a missing data marker is generated and output as the lookup result.

5. The branch prediction processing system according to claim 1, characterized in that, The first-stage multiplexer is also used for: If the rereading flag information is empty, then according to the branch target cache path prediction information, one of the branch target cache sub-modules with the corresponding path prediction flag field is set to normal power mode, and the remaining branch target cache sub-modules are set to low power mode.

6. The branch prediction processing system according to claim 5, characterized in that, The first-stage multiplexer is also used for: Upon first read, the instruction address information is sent to the corresponding multi-level branch target cache module. If the initial read fails and a subsequent read is performed, the branch target address is simultaneously looked up in all the branch target cache submodules based on the instruction address information.

7. The branch prediction processing system according to claim 1, characterized in that, The first-stage multiplexer is also used for: It simultaneously receives data from the processor pipeline and the second-stage multiplexer, and prioritizes processing data transmitted from the second-stage multiplexer.

8. A method for reducing branch prediction power consumption, characterized in that, The method is implemented based on the branch prediction processing system according to any one of claims 1-7, and the method for reducing branch prediction power consumption includes the following steps: The first-stage multiplexer obtains the instruction address information and branch target cache path prediction information transmitted from the processor pipeline. Based on the branch target cache path prediction information and reread flag information, the branch target cache submodule with the corresponding preset path prediction flag field is set to normal power consumption mode and enabled read mode. Then, the instruction address information is transmitted to the branch target cache submodule. The reread flag information is generated by the second-stage multiplexer. The multi-level branch target cache module performs a lookup of the branch target address in the corresponding branch target cache sub-module based on the instruction address information, obtains the lookup result, and returns the lookup result to the first-level multiplexer. The lookup result returned by the multi-level branch target cache module is transmitted to the path prediction and determination module through the first-level multiplexer; The path prediction determination module compares the instruction address information with the lookup table result to obtain a path prediction result regarding whether the instruction address information and the lookup table result are equal, and then transmits the path prediction result to the second-level multiplexer. The second-stage multiplexer outputs either the path prediction result or the lookup table result to the first-stage multiplexer or the processor pipeline based on the path prediction result. Specifically: if the path prediction result indicates that the instruction address information and the lookup table result are equal, then the lookup table result is output to the processor pipeline; if the path prediction result indicates that the instruction address information and the lookup table result are not equal, then the path prediction result and the reread flag information are output to the first-stage multiplexer, and a reread is performed.

9. A computer device, characterized in that, include: The method for reducing branch prediction power consumption includes a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor, when executing the program for reducing branch prediction power consumption, implements the steps of the method for reducing branch prediction power consumption as described in claim 8.

10. A storage medium, characterized in that, The storage medium stores a program for reducing branch prediction power consumption, which, when executed by a processor, implements the steps in the method for reducing branch prediction power consumption as described in claim 8.

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