Prediction method and device for test project loading result, equipment and storage medium

Abstract

The invention provides a test project loading result prediction method and device, equipment and a storage medium, file index information used for representing the distribution condition of each sub-file in a test board card memory chip is generated based on configuration parameters of a to-be-loaded test project file, and a memory model is generated based on the file index information and the memory chip. According to the method, project file loading is simulated in an off-line mode, file loading prediction information and a file loading prediction result are obtained, if file simulation loading succeeds, the test project file is sent to the test board card for file loading, whether loading succeeds or not can be judged in advance without actual file loading, and the file loading efficiency is improved. And configuration parameter adjustment is carried out when file simulation loading fails, so that configuration parameter adjustment and secondary file loading after actual loading are avoided, the hardware loss of the test board card is reduced, the file loading efficiency can be improved, and the chip test efficiency is further improved.

Description

Technical Field

[0001] The present disclosure relates to automated testing technology, and in particular to a method, apparatus, device, and storage medium for predicting test engineering loading results. Background Art

[0002] The integrated circuit (IC) testing process primarily involves test project creation, test project file debugging, test project loading, and dynamic test project file modification and debugging. Test project files typically include files describing the input values ​​and expected output values ​​of the chip under test (e.g., pattern files), files describing the electrical configuration parameters of the chip under test (e.g., level files), and files describing the timing configuration parameters of test signals (e.g., timing files). Together, these files describe the complete test environment and test tasks.

[0003] Before chip testing, the test system must parse the test project file according to specified rules and load it into the corresponding memory chip on the test board. During chip testing, due to the need to adapt to certain special timing requirements, it is often necessary to dynamically adjust the test project file based on the chip test situation and reload the modified test project file into the test board's memory chip.

[0004] However, some test projects carry a lot of project data, and their test project files have the characteristics of a large number of files and a single file occupies a large amount of memory. The file loading time is long, and there may be a situation where the file loading fails due to insufficient allocated memory space. At this time, technicians need to manually calculate the distribution of the test project files on each memory chip, reallocate the memory and reload the test project files. The above situation results in a large workload for file loading, low chip testing efficiency, and a large loss of hardware resources such as memory chips in the test board. Summary of the Invention

[0005] The embodiments of the present disclosure provide a method, apparatus, device, and storage medium for predicting test engineering loading results, which can reduce hardware loss of test boards and improve chip testing efficiency.

[0006] One aspect of an embodiment of the present disclosure provides a method for predicting a test engineering loading result, comprising: Get the test project file to be loaded; generating file index information based on configuration parameters in the test project file, wherein the file index information is used to represent the distribution of each sub-file in the test project file in at least one memory chip of the test board after the test project file is loaded into the test board; Performing a file loading simulation based on a memory model of the at least one memory chip and the file index information to obtain file loading prediction information and a file loading prediction result, wherein the memory model represents a memory space proportion corresponding to at least one sub-file in the memory chip, and the file loading prediction information represents a memory space occupation status of each sub-file in the at least one memory chip; In response to the file loading prediction result indicating that the file simulation loading is successful, sending the test engineering file to the test board; In response to the file loading prediction result indicating that the file simulation loading fails, the configuration parameters of the test engineering file are adjusted.

[0007] Optionally, the performing file loading simulation based on the memory model of the at least one memory chip and the file index information to obtain file loading prediction information includes: Based on the file index information, the test engineering file is written into the memory model of the at least one memory chip to generate first file loading information, where the first file loading information includes at least one of the following: memory space occupancy information of the memory chip, memory space occupancy information corresponding to various sub-files in the memory chip, the number of sub-files of a first preset type in the memory chip and the memory space occupancy information of each sub-file of the first preset type, and memory space occupancy information of preset attribute data in the memory chip; Based on the correspondence between the memory chip and the test channel and slot in the test board and the first file loading information, a memory space integration calculation is performed to generate second file loading information, and the second file loading information includes at least one of the following: memory space occupancy information of the sub-file corresponding to each slot in the memory chip, memory space occupancy information of the sub-file corresponding to each test channel in the memory chip, and memory space occupancy information of the sub-file of the second preset type corresponding to each test channel in the memory chip.

[0008] Optionally, the performing file loading simulation based on the memory model of the at least one memory chip and the file index information to obtain file loading prediction information and a file loading prediction result includes: Based on the file index information, writing the sub-file in the test project file into the memory model of the at least one memory chip; Based on the file compilation rule, the sub-files in each memory model are compiled, and the file loading prediction information and the file loading prediction result are obtained based on the compiled sub-files.

[0009] Optionally, the method further includes: In response to the file loading prediction result indicating that the file simulation loading is successful, generating file extension prediction information, the file extension prediction information including at least one of the following: remaining memory space information corresponding to each sub-file type, and the number of expandable files corresponding to each sub-file type; In response to the file loading prediction result indicating that the file simulation loading fails, adjusting the configuration parameters of the test engineering file includes: In response to the file loading prediction result indicating a file simulation loading failure, generating file loading strategy information based on the file loading prediction information and information about free memory chips in the test board, the file loading strategy information including file index information after adjusting at least one sub-file to the free memory chip; The configuration parameters of the test project file are adjusted based on the file loading strategy information.

[0010] Optionally, the method further includes: During the running of the test project corresponding to the test project file, in response to a file reload prediction operation, obtaining a target sub-file input by the file reload prediction operation, the target sub-file being obtained by modifying the test project file; A file reloading simulation is performed on the target sub-file, and a file reloading prediction result is obtained based on memory space occupation information of the target sub-file in the corresponding target memory chip after the file reloading.

[0011] Optionally, performing a file reloading simulation on the target sub-file and obtaining a file reloading prediction result based on memory space occupation information of the target sub-file in the corresponding target memory chip after the file reloading includes: Performing a file reloading simulation on the target sub-file based on the target sub-file and the configuration parameters to obtain memory space occupation information of the target sub-file in the corresponding target memory chip; Based on the file loading prediction information, determining remaining memory space information corresponding to the file type to which the target sub-file belongs in the target memory chip; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, generating a file reloading prediction result of successful file reloading; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result indicating file reloading failure is generated.

[0012] Optionally, performing a file reloading simulation on the target sub-file and obtaining a file reloading prediction result based on memory space occupation of the target sub-file in the corresponding target memory chip after the file reloading includes: Performing a file reloading simulation on the target sub-file based on the target sub-file and the sub-file configuration parameters of the target sub-file to obtain memory space occupation information of the target sub-file in the corresponding target memory chip; Online reading of remaining memory space information corresponding to the file type of the target sub-file in the target memory chip; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, generating a file reloading prediction result of successful file reloading; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result indicating file reloading failure is generated.

[0013] Another aspect of the embodiments of the present disclosure provides a device for predicting test engineering loading results, comprising: The first acquisition module is used to obtain the test project file to be loaded; a first generating module, configured to generate file index information based on configuration parameters in the test project file, wherein the file index information is used to represent the distribution of each sub-file in the test project file in at least one memory chip of the test board after the test project file is loaded into the test board; a first prediction module, configured to perform a file loading simulation based on a memory model of the at least one memory chip and the file index information to obtain file loading prediction information and a file loading prediction result, wherein the memory model represents a memory space proportion corresponding to at least one sub-file in the memory chip, and the file loading prediction information represents a memory space occupation status of each sub-file in the at least one memory chip; A sending module, configured to send the test engineering file to the test board in response to the file loading prediction result indicating that the file simulation loading is successful; The adjustment module is configured to adjust the configuration parameters of the test engineering file in response to the file loading prediction result indicating that the file simulation loading fails.

[0014] Another aspect of the present disclosure provides an electronic device, including: Memory for storing computer programs; The processor is configured to execute the computer program stored in the memory, and when the computer program is executed, the method described in the above aspects is implemented.

[0015] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in the above aspects is implemented.

[0016] Another aspect of the embodiments of the present disclosure provides a computer program product, including computer program instructions, which implement the method described in the above aspects when executed by a processor.

[0017] Based on the embodiment of the present disclosure, file index information for characterizing the distribution of each sub-file in the memory chip of the test board is generated based on the configuration parameters of the test project file to be loaded. Based on the file index information and the memory model of the memory chip, the project file loading is simulated in an offline manner to obtain file loading prediction information and file loading prediction results. If the file simulation loading is successful, the test project file is sent to the test board for file loading. If the file simulation loading fails, the configuration parameters of the test project file are adjusted to adjust the distribution of the file in the memory chip of the test board, so that the adjusted test project file can be successfully loaded. It is possible to judge in advance whether the loading is successful without actually loading the file, and to adjust the configuration parameters when the file simulation loading fails, to avoid adjusting the configuration parameters and loading the file again after the actual loading, thereby reducing the hardware loss of the test board, and improving the file loading efficiency and thus improving the chip testing efficiency.

[0018] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which: Figure 1 A flowchart of a test engineering file loading process in related technology; Figure 2 A flowchart of an embodiment of a method for predicting test engineering loading results disclosed herein; Figure 3 A schematic diagram of a file loading simulation process shown in one embodiment of the present disclosure; Figure 4 A flowchart of another embodiment of the method for predicting test engineering loading results disclosed herein; Figure 5A flowchart of another embodiment of the method for predicting test engineering loading results disclosed herein; Figure 6 A flowchart of another embodiment of the method for predicting test engineering loading results disclosed herein; Figure 7 A flowchart of another embodiment of the method for predicting test engineering loading results disclosed herein; Figure 8 A schematic structural diagram of an embodiment of a device for predicting test engineering loading results disclosed herein; Figure 9 The figure is a schematic structural diagram of an application embodiment of the electronic device disclosed herein. DETAILED DESCRIPTION

[0021] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0022] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, and do not represent any specific technical meanings, nor do they indicate a necessary logical order between them.

[0023] It should also be understood that in the embodiments of the present disclosure, “a plurality of” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0024] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0025] In addition, the term "and / or" in this disclosure is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this disclosure generally indicates that the related objects are in an "or" relationship.

[0026] It should also be understood that the description of the various embodiments in this disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced with each other. For the sake of brevity, they will not be described one by one.

[0027] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0028] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0029] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0030] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0031] Figure 1 This article shows a common test project file loading process in related technologies. After creating a test project and adjusting various sub-files based on the test requirements of the chip to be tested, the complete test project file is loaded into the memory chip of the test board to obtain the file loading result. If the storage space of the memory chip is insufficient to store the corresponding file, the loading will fail. In this case, the technician needs to manually calculate the distribution of the test project file on each memory chip, modify the corresponding sub-file or adjust the file distribution method to distribute the test project file to more memory chips. After the modification is completed, the test project file is loaded again to obtain the file loading result. After the file is successfully loaded, the test project is run.

[0032] However, some test projects often correspond to a large amount of project data. The test project files of such test projects have the following characteristics: 1. There are too many Pattern files. One test channel may correspond to millions of Pattern files. 2. The Pattern files are rich in content, and a single file occupies a large amount of memory space. 3. The Level files and Timing files are rich in content and occupy a large amount of memory space. In the above cases, the project file loading often fails due to insufficient onboard memory. During the file loading process, the time it takes to load the test project file into the test board memory chip is too long. Moreover, after the project loading is completed, if the chip under test has special timing requirements, the technician needs to dynamically adjust the test project file and load the modified file into the test board memory chip. If the remaining memory of the memory chip is insufficient to load the modified file, the distribution of the test project file also needs to be readjusted. The above cases often result in the need to load test project files with large amounts of data multiple times, which makes file loading inefficient and causes significant damage to hardware such as memory chips.

[0033] Figure 2A flowchart of a method for predicting test project loading results according to an exemplary embodiment of the present disclosure is provided. The method for predicting test project loading results according to the embodiment of the present disclosure can be implemented by an electronic device in a chip test system that is equipped with file loading prediction software.

[0034] like Figure 2 As shown, the method includes the following steps: Step 201: Obtain the test project file to be loaded.

[0035] A test project file is a file containing test data related to the chip test project. After the test project is created, the test board loads the test project file into the memory chip and runs the test program based on the test project file to complete the test task of the chip to be tested.

[0036] In one possible implementation, the electronic device may be a host computer in a chip testing system, and the test project file is a file stored locally on the electronic device. Alternatively, the electronic device may be a user's terminal device, and the test project file is a file stored locally on the electronic device or a file retrieved from a remote server. When a file load prediction operation is received, the test project file specified by the file load prediction operation is obtained.

[0037] Step 202: Generate file index information based on the configuration parameters in the test project file.

[0038] The file index information is used to represent the distribution of each sub-file in the test project file in at least one memory chip of the test board after the test project file is loaded into the test board.

[0039] Optional, such as Figure 3 As shown, the test project file contains at least one sub-file, and different types of sub-files contain test data for different purposes. For example, the test data in the Pattern file is mainly used to describe the input vectors and expected output vectors of each pin of the chip under test in each cycle. Furthermore, the Pattern file is divided into two file forms: the cap file is a manually edited readable and writable Pattern text file, and the cbp file is a binary Pattern file converted from the cap file and recognizable by the hardware in the test board; the test data in the Level file corresponds to the electrical characteristics of the test signal, and is mainly used to describe the electrical parameter configuration of the power supply, signal drive, etc. during the chip test process to ensure that the chip under test operates under the correct voltage and current conditions; the test data in the Timing file corresponds to the timing characteristics of the test signal, and is mainly used to describe the timing parameter configuration of the test signal, which is used to control the signal edge, sampling point and sampling period, etc., to ensure that the input signal to the chip under test is within the correct time window and the output signal of the chip under test is captured within the correct time window.

[0040] Memory chips are hardware used to provide storage space in test boards, such as Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate (DDR) SDRAM chips.

[0041] In one possible implementation, the configuration parameters in the test engineering file include channel attributes corresponding to each subfile, which characterize the type of test channel to which the subfile corresponds. A test board typically includes different types of test channels, each of which transmits test data from the corresponding subfile to the chip under test. Optionally, each test channel has a corresponding memory chip. Therefore, based on the configuration parameters in the test engineering file, the test channel corresponding to each subfile can be determined. Furthermore, based on the correspondence between the test channels and the memory chips, the memory chip corresponding to the subfile can be determined, thereby generating file index information.

[0042] Step 203 : Perform file loading simulation based on the memory model of at least one memory chip and the file index information to obtain file loading prediction information and a file loading prediction result.

[0043] The memory model represents a memory space ratio corresponding to at least one sub-file in a memory chip, and the file loading prediction information represents a memory space occupancy of each sub-file in at least one memory chip.

[0044] Instructively, a corresponding memory model can be set in advance for each memory chip in the test board. For example, in the memory model of a certain memory chip, 40% of the memory space can be used to store Pattern files, 30% of the memory space can be used to store Level files and Timing files, and 30% of the memory space can be used to store other files and dynamically loaded data generated by file modifications during the test.

[0045] In another possible implementation, the user can select some sub-files in the test project file for file loading simulation based on actual needs. For example, if the data volume of the pattren file in a test project file is large and the data volume of other types of sub-files is small, you can choose to perform file loading simulation on the pattren file alone to improve computing efficiency and save the time consumed by file preloading.

[0046] Step 204 : In response to the file loading prediction result indicating that the file simulation loading is successful, the test project file is sent to the test board.

[0047] In one possible implementation, if the memory space of the memory model can store the test project file, the file simulation loading is successful, and the electronic device can send the test project file to the test board online, or send the file loading prediction result to the host computer to trigger the host computer to send the test project file to the test board, so that the test board loads the test project file into the memory chip and starts the test project.

[0048] Step 205 : In response to the file loading prediction result indicating that the file simulation loading fails, the configuration parameters of the test project file are adjusted.

[0049] In one possible implementation, if the memory model's memory space is insufficient to store the test project file, the file simulation loading fails. Optionally, in response to the file loading prediction result indicating a file simulation loading failure, a method for adjusting the memory distribution of the test project file can be automatically determined based on the memory model and the file loading prediction information, generating new configuration parameters. Alternatively, the file loading prediction information can be sent to a user terminal, a configuration parameter adjustment operation from the user is received, and the configuration parameters of the test project file are adjusted based on the configuration parameter adjustment operation, so that the test project file after the configuration parameter adjustment can be successfully loaded.

[0050] Based on the embodiment of the present disclosure, file index information for characterizing the distribution of each sub-file in the memory chip of the test board is generated based on the configuration parameters of the test project file to be loaded. Based on the file index information and the memory model of the memory chip, the project file loading is simulated in an offline manner to obtain file loading prediction information and file loading prediction results. If the file simulation loading is successful, the test project file is sent to the test board for file loading. If the file simulation loading fails, the configuration parameters of the test project file are adjusted to adjust the distribution of the file in the memory chip of the test board, so that the adjusted test project file can be successfully loaded. It is possible to judge in advance whether the loading is successful without actually loading the file, and to adjust the configuration parameters when the file simulation loading fails, to avoid adjusting the configuration parameters and loading the file again after the actual loading, thereby reducing the hardware loss of the test board, and improving the file loading efficiency and thus improving the chip testing efficiency.

[0051] In a possible implementation, the file loading prediction information may include at least one of the following information: the memory space occupied by each sub-file, the number of files, the memory space occupied by files of a preset type, etc., and the memory space occupied by the sub-files corresponding to each test channel may also be obtained by integrated calculation, such as Figure 4 As shown, the process of determining the file loading prediction information in step 203 may include the following steps: Step 401: Based on the file index information, write the test project file into the memory model of at least one memory chip to generate first file loading information.

[0052] The first file loading information includes at least one of the following: memory space occupancy information of the memory chip, memory space occupancy information corresponding to each type of sub-file in the memory chip, the number of sub-files of the first preset type in the memory chip and the memory space occupancy information of each sub-file of the first preset type, and memory space occupancy information of preset attribute data in the memory chip.

[0053] Illustratively, the memory space occupancy information of the memory chip includes the size of the occupied memory space of each memory chip; the memory space occupancy information corresponding to each type of sub-file in the memory chip may, for example, include the size of the memory space occupied by the Pattern file, the size of the memory space occupied by the Level file, the size of the memory space occupied by the Timing file, and the size of the memory space occupied by other files in each memory chip (or designated memory chip); the number of sub-files of the first preset type in the memory chip includes, for example, the number of cap files in each memory chip; the memory space occupancy information of each sub-file of the first preset type includes, for example, the size of the memory space occupied by each cap file in each memory chip; the memory space occupancy information of the preset attribute data in the memory chip may, for example, include the size of the memory space occupied by all vectors in the cap file in each memory chip.

[0054] Step 402 : performing memory space integration calculation based on the correspondence between the memory chips and the test channels and slots in the test board and the first file loading information to generate second file loading information.

[0055] The second file loading information includes at least one of the following: memory space occupancy information of the sub-files corresponding to each slot in the memory chip, memory space occupancy information of the sub-files corresponding to each test channel in the memory chip, and memory space occupancy information of the sub-files of the second preset type corresponding to each test channel in the memory chip.

[0056] Optionally, after calculating the first file loading information, a memory space integration calculation can be further performed based on the correspondence between the memory chips and test channels and slots in the test board and the first file loading information to obtain the memory space occupied by the sub-files corresponding to each slot and each test channel in the memory chip. This is so that when the sub-file data volume corresponding to the same slot or the same test channel is large and the memory space of the corresponding memory chip is insufficient to load the corresponding sub-file, more memory chips can be set for this type of slot or test channel and the file distribution can be adjusted.

[0057] In a possible implementation, the test project file is usually a manually edited readable and writable text file. When the simulation file is loaded, the file is first compiled into a file that can be recognized by the test board, such as Figure 5As shown, the above step 203 specifically includes the following steps: Step 501: Write the sub-files in the test project file into the memory model of at least one memory chip based on the file index information.

[0058] Step 502 : compile the sub-files in each memory model based on the file compilation rule, and obtain file loading prediction information and file loading prediction results based on the compiled sub-files.

[0059] Based on the file index information, each sub-file in the test project file can be written into the corresponding memory model according to the correspondence between the sub-files and at least one memory chip. The sub-files in each memory model are then compiled according to the file compilation rules. For example, a CBP file is compiled based on a CAP file. After the file compilation is complete, file load prediction information and a file load prediction result are generated based on the pre-compiled and compiled sub-files stored in the memory model.

[0060] In one possible implementation, after generating the file loading simulation results, if the loading is successful, the scalable file information of each memory chip is further predicted; if the loading fails, corresponding file loading strategy information is generated to adjust the file layout. The test engineering loading result prediction method provided by the embodiment of the present disclosure may also include the following steps: In response to the file loading prediction result indicating that the file simulation loading is successful, file extension prediction information is generated, and the file extension prediction information includes at least one of the following: remaining memory space information corresponding to each sub-file type, and the number of expandable files corresponding to each sub-file type.

[0061] In principle, the remaining memory space information corresponding to each sub-file can be calculated based on the available memory space information corresponding to each sub-file in the memory model and the occupied memory space information of each sub-file after the file simulation is loaded, and the number of expandable files corresponding to each sub-file can be predicted based on the memory space information occupied by each sub-file in the loaded sub-files.

[0062] The above step 205 may include the following steps: Step 205a: in response to the file loading prediction result indicating that the file simulation loading fails, generate file loading strategy information based on the file loading prediction information and the free memory chip information in the test board.

[0063] The file loading strategy information includes file index information after adjusting at least one sub-file to a free memory chip.

[0064] Step 205b: Adjust the configuration parameters of the test project file based on the file loading strategy information.

[0065] Optionally, the information about the sub-files that have not been loaded and the memory space of the free memory chips in the test board may be input into the prediction model, and the file loading strategy information may be obtained through the prediction model.

[0066] Optionally, the configuration parameters of the test project file may be automatically adjusted directly based on the file loading strategy information, or, after receiving a configuration parameter modification operation from the user, the configuration parameters of the test project file may be adjusted based on the parameter modification method indicated by the configuration parameter modification operation.

[0067] Based on the embodiments of the present disclosure, when the file simulation is successfully loaded, file extension prediction information is generated so that the user can confirm the remaining memory space information and estimate the number of expandable files in advance, which is convenient for file modification and adjustment during subsequent chip testing, thereby reducing the failure of file reloading. When the file simulation loading fails, file loading strategy information is generated to assist in adjusting the configuration parameters so that the adjusted file layout can enable the test project file to be successfully loaded, thereby improving file loading efficiency.

[0068] In a possible implementation, after the test board actually loads the test project file and during the test project execution for chip testing, if some sub-files are modified, a file reload prediction can be performed to avoid dynamic data loading failure. Figure 6 As shown, the method for predicting the test engineering loading result provided by the embodiment of the present disclosure may further include the following steps: Step 601 : During the execution of the test project corresponding to the test project file, in response to a file reloading prediction operation, obtaining a target sub-file inputted by the file reloading prediction operation.

[0069] The target sub-file is obtained by modifying the test project file.

[0070] Step 602 : Perform a file reloading simulation on the target sub-file, and obtain a file reloading prediction result based on the memory space occupation information of the target sub-file in the corresponding target memory chip after the file reloading.

[0071] During the chip testing process, due to some special timing requirements, it is usually necessary to modify the data of some sub-files or add new data. The target sub-file obtained by the file modification needs to be reloaded into the memory chip of the test board. In the case of a large amount of file data, there may be insufficient remaining memory space in the memory chip, resulting in a failure to reload the target file. Therefore, during the operation of the test project corresponding to the test project file, the target sub-file input of the file reloading prediction operation can be obtained, and a file reloading simulation can be performed on the target sub-file. Based on the memory space occupancy information of the target sub-file in the corresponding target memory chip after the file reloading, the file reloading prediction result is obtained. If the file reloading prediction result indicates that the file reloading is successful, the control test board directly reloads the target sub-file and performs the subsequent chip testing process. If the file reloading prediction result indicates that the file reloading fails, the configuration parameters of the target sub-file are adjusted. For example, the target sub-file and other related sub-files can be migrated to an idle memory chip.

[0072] Optionally, the file reloading simulation of the target sub-file may be performed offline, and the above step 602 may specifically include the following steps: Step 602a: performing a file reloading simulation on the target sub-file based on the target sub-file and the configuration parameters to obtain memory space occupation information of the target sub-file in the corresponding target memory chip.

[0073] Based on the configuration parameters obtained when predicting file loading for the complete test project file, the target memory chip corresponding to the target sub-file can be determined and a file reloading simulation can be performed to obtain the memory space occupancy information of the target sub-file in the corresponding target memory chip.

[0074] Step 602b: Based on the file loading prediction information, determine the remaining memory space information corresponding to the file type to which the target sub-file belongs in the target memory chip.

[0075] Based on the file loading prediction information obtained from the previous file loading simulation of the complete test project file and the memory model of the target memory chip, the remaining memory space information corresponding to the file type of the target sub-file in the target memory chip can be determined. For example, if the target sub-file is a CAP file, the remaining memory space information corresponding to the CAP file is determined based on the memory space used to store the CAP file in the memory model and the memory space occupied by the CAP file in the file loading prediction information.

[0076] Step 602c: in response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, a file reloading prediction result indicating successful file reloading is generated.

[0077] Step 602d: In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result indicating file reloading failure is generated.

[0078] Optionally, if the file reloading prediction result indicates that the file reloading is successful, the test board can be instructed to load the target sub-file, and at the same time, the remaining memory space information of the corresponding type of sub-file in the target memory chip, the number of expandable files of the corresponding type of sub-file and other data can be updated; if the file reloading prediction result indicates that the file reloading fails, the configuration parameters of the target sub-file can be adjusted based on the memory space occupancy information of the target sub-file in the corresponding target memory chip, for example, the target sub-file and other related sub-files can be migrated to an idle memory chip.

[0079] Optionally, in another possible implementation, the file reloading simulation of the target sub-file may be performed online, and the above step 602 may specifically include the following steps: Step 602e: performing a file reloading simulation on the target sub-file based on the target sub-file and the sub-file configuration parameters of the target sub-file to obtain memory space occupation information of the target sub-file in the corresponding target memory chip.

[0080] Step 602f: online reading the remaining memory space information corresponding to the file type of the target sub-file in the target memory chip.

[0081] For the method of online file reloading simulation, the target sub-file can be simulated by separately obtaining the sub-file configuration parameters of the target sub-file, obtaining the memory space occupancy information of the target sub-file in the corresponding target memory chip, and reading the actual remaining memory space information of the target memory chip online to determine whether the remaining memory space of the target memory chip can support the loading of the target sub-file.

[0082] Step 602g: In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, a file reloading prediction result indicating successful file reloading is generated.

[0083] Step 602h: In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result indicating file reloading failure is generated.

[0084] Optionally, if the file reloading prediction result indicates that the file reloading is successful, the test board can be instructed to load the target sub-file, and at the same time, the remaining memory space information of the corresponding type of sub-file in the target memory chip, the number of expandable files of the corresponding type of sub-file and other data can be updated; if the file reloading prediction result indicates that the file reloading fails, the configuration parameters of the target sub-file can be adjusted based on the memory space occupancy information of the target sub-file in the corresponding target memory chip, for example, the target sub-file and other related sub-files can be migrated to an idle memory chip.

[0085] Based on the embodiments of the present disclosure, by performing file reloading simulation in an offline manner, it is possible to predict in advance whether the remaining memory space of the target memory chip supports reloading the target sub-file. If it cannot be loaded, the file can be reallocated, avoiding repeated file loading processes, reducing the number of data writes to the hardware memory, reducing hardware loss, and reducing the complexity of the debugger's operations. Alternatively, by performing file reloading simulation in an online manner, it is possible to calculate in real time whether the actual remaining memory space of the current target memory chip supports reloading the target sub-file, thereby improving the accuracy of the file reloading prediction results, thereby reducing hardware loss and improving chip testing efficiency.

[0086] In combination with the above embodiments, Figure 7 A loading prediction process of a test engineering file is shown. Figure 7 As shown, the entire file loading prediction process can be performed offline. The result of loading the test project file into the test board can be predicted without the actual file loading. If the predicted loading fails, the file can be adjusted in advance. Figure 1 The corresponding related technology repeatedly loads to obtain the loading results and reloads the file after modification, which can reduce the hardware loss of the test board, speed up the chip testing process, and improve the testing efficiency.

[0087] Figure 8 The following is a block diagram of a device for predicting test engineering loading results provided by an exemplary embodiment of the present disclosure. The device for predicting test engineering loading results includes: The first acquisition module 801 is used to acquire the test project file to be loaded; A first generating module 802 is configured to generate file index information based on the configuration parameters in the test project file obtained by the first obtaining module 801. The file index information is used to represent the distribution of each sub-file in the test project file in at least one memory chip of the test board after the test project file is loaded into the test board; A first prediction module 803 is configured to perform a file loading simulation based on a memory model of at least one memory chip and the file index information generated by the generation module 802 to obtain file loading prediction information and a file loading prediction result, wherein the memory model represents a memory space usage of at least one sub-file in the memory chip, and the file loading prediction information represents a memory space usage of each sub-file in the at least one memory chip; A sending module 804 is configured to send a test project file to a test board in response to the file loading prediction result obtained by the prediction module 803 indicating that the file simulation loading is successful; The adjustment module 805 is configured to adjust configuration parameters of the test project file in response to the file loading prediction result obtained by the prediction module 803 indicating that the file simulation loading has failed.

[0088] Optionally, in a possible implementation manner, the first prediction module 803 is further configured to: Based on the file index information, the test project file is written into a memory model of at least one memory chip to generate first file loading information, where the first file loading information includes at least one of the following: memory space occupancy information of the memory chip, memory space occupancy information corresponding to various sub-files in the memory chip, the number of sub-files of a first preset type in the memory chip and the memory space occupancy information of each sub-file of the first preset type, and memory space occupancy information of preset attribute data in the memory chip; Based on the correspondence between the memory chip and the test channel and slot in the test board and the first file loading information, a memory space integration calculation is performed to generate second file loading information, and the second file loading information includes at least one of the following: memory space occupancy information of the sub-file corresponding to each slot in the memory chip, memory space occupancy information of the sub-file corresponding to each test channel in the memory chip, and memory space occupancy information of the sub-file of the second preset type corresponding to each test channel in the memory chip.

[0089] Optionally, in a possible implementation manner, the first prediction module 803 is further configured to: Based on the file index information, writing the sub-files in the test project file into the memory model of at least one memory chip; Based on the file compilation rules, the sub-files in each memory model are compiled, and the file loading prediction information and the file loading prediction results are obtained based on the compiled sub-files.

[0090] Optionally, in a possible implementation manner, the device for predicting the test engineering loading result may further include: a second generating module, configured to generate file extension prediction information in response to the file loading prediction result indicating successful file simulation loading, wherein the file extension prediction information includes at least one of the following: remaining memory space information corresponding to each sub-file type, and the number of expandable files corresponding to each sub-file type; The adjustment module 805 is further configured to: In response to the file loading prediction result indicating that the file simulation loading has failed, generating file loading strategy information based on the file loading prediction information and information about free memory chips in the test board, the file loading strategy information including file index information after adjusting at least one sub-file to the free memory chip; Adjust the configuration parameters of the test project file based on the file loading strategy information.

[0091] Optionally, in a possible implementation manner, the device for predicting the test engineering loading result may further include: a second acquisition module, configured to, during the execution of the test project corresponding to the test project file, in response to the file reload prediction operation, acquire a target sub-file input by the file reload prediction operation, the target sub-file being obtained by modifying the test project file; The second prediction module is used to perform file reloading simulation on the target sub-file, and obtain a file reloading prediction result based on the memory space occupation information of the target sub-file in the corresponding target memory chip after the file reloading.

[0092] Optionally, in a possible implementation manner, the second prediction module is further configured to: Perform file reloading simulation on the target sub-file based on the target sub-file and configuration parameters to obtain the memory space occupation information of the target sub-file in the corresponding target memory chip; Based on the file loading prediction information, determining the remaining memory space information corresponding to the file type of the target sub-file in the target memory chip; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, generating a file reloading prediction result of successful file reloading; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result of file reloading failure is generated.

[0093] Optionally, in a possible implementation manner, the second prediction module is further configured to: Performing a file reloading simulation on the target sub-file based on the target sub-file and the sub-file configuration parameters of the target sub-file to obtain memory space occupation information of the target sub-file in the corresponding target memory chip; Online reading of the remaining memory space information corresponding to the file type of the target sub-file in the target memory chip; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, generating a file reloading prediction result of successful file reloading; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result of file reloading failure is generated.

[0094] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The parts of the embodiments that are the same, similar, or corresponding can be referred to each other. Since the method, device, system, and equipment embodiments are basically corresponding, the relevant parts can be referred to the description of the corresponding parts. The methods, devices, systems, and equipment of the embodiments of the present disclosure also correspond to each other in terms of specific implementation methods and beneficial technical effects. The relevant contents can be referenced to each other and will not be repeated here.

[0095] In addition, an embodiment of the present disclosure further provides an electronic device, including: Memory for storing computer programs; The processor is configured to execute the computer program stored in the memory, and when the computer program is executed, the method for predicting the test engineering loading result described in any one of the above embodiments of the present disclosure is implemented.

[0096] Figure 9 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Figure 9 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be either or both of the first device and the second device, or a standalone device independent of them, and the standalone device may communicate with the first device and the second device to receive collected input signals from them.

[0097] like Figure 9 As shown, the electronic device includes one or more processors and memory.

[0098] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0099] The memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the test engineering load result prediction method of the various embodiments of the present disclosure described above and / or other desired functions.

[0100] In one example, the electronic device may further include an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0101] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0102] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0103] Of course, to simplify, Figure 9 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, the electronic device may further include any other appropriate components according to specific application scenarios.

[0104] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method for predicting test engineering loading results according to various embodiments of the present disclosure described in the above part of this specification.

[0105] The computer program product may be written in any combination of one or more programming languages ​​to implement the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0106] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the method for predicting the test engineering loading results according to various embodiments of the present disclosure described in the above part of this specification.

[0107] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0108] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk, etc. Various media that can store program codes.

[0109] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be construed as necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0110] Each embodiment in this specification is described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. References to the same or similar parts between the various embodiments are sufficient. For system embodiments, since they largely correspond to method embodiments, their description is relatively simple. For relevant parts, references to the description of the method embodiments are sufficient.

[0111] The block diagrams of the devices, devices, equipment, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0112] The methods and apparatus of the present disclosure may be implemented in many ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specified. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers recording media that store programs for executing the methods according to the present disclosure.

[0113] It should also be noted that in the apparatus, device, and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0114] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0115] The above description has been provided for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for predicting loading results of a test project, characterized in that: include: Get the test project file to be loaded; generating file index information based on configuration parameters in the test project file, wherein the file index information is used to represent the distribution of each sub-file in the test project file in at least one memory chip of the test board after the test project file is loaded into the test board; Performing a file loading simulation based on a memory model of the at least one memory chip and the file index information to obtain file loading prediction information and a file loading prediction result, wherein the memory model represents a memory space proportion corresponding to at least one sub-file in the memory chip, and the file loading prediction information represents a memory space occupation status of each sub-file in the at least one memory chip; In response to the file loading prediction result indicating that the file simulation loading is successful, sending the test engineering file to the test board; In response to the file loading prediction result indicating that the file simulation loading fails, the configuration parameters of the test engineering file are adjusted.

2. The method according to claim 1, characterized in that The performing file loading simulation based on the memory model of the at least one memory chip and the file index information to obtain file loading prediction information includes: Based on the file index information, the test engineering file is written into the memory model of the at least one memory chip to generate first file loading information, where the first file loading information includes at least one of the following: memory space occupancy information of the memory chip, memory space occupancy information corresponding to various sub-files in the memory chip, the number of sub-files of a first preset type in the memory chip and the memory space occupancy information of each sub-file of the first preset type, and memory space occupancy information of preset attribute data in the memory chip; Based on the correspondence between the memory chip and the test channel and slot in the test board and the first file loading information, a memory space integration calculation is performed to generate second file loading information, and the second file loading information includes at least one of the following: memory space occupancy information of the sub-file corresponding to each slot in the memory chip, memory space occupancy information of the sub-file corresponding to each test channel in the memory chip, and memory space occupancy information of the sub-file of the second preset type corresponding to each test channel in the memory chip.

3. The method according to claim 1, characterized in that The performing file loading simulation based on the memory model of the at least one memory chip and the file index information to obtain file loading prediction information and a file loading prediction result includes: Based on the file index information, writing the sub-file in the test project file into the memory model of the at least one memory chip; Based on the file compilation rule, the sub-files in each memory model are compiled, and the file loading prediction information and the file loading prediction result are obtained based on the compiled sub-files.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: In response to the file loading prediction result indicating that the file simulation loading is successful, generating file extension prediction information, the file extension prediction information including at least one of the following: remaining memory space information corresponding to each sub-file type, and the number of expandable files corresponding to each sub-file type; In response to the file loading prediction result indicating that the file simulation loading fails, adjusting the configuration parameters of the test engineering file includes: In response to the file loading prediction result indicating a file simulation loading failure, generating file loading strategy information based on the file loading prediction information and information about free memory chips in the test board, the file loading strategy information including file index information after adjusting at least one sub-file to the free memory chip; The configuration parameters of the test project file are adjusted based on the file loading strategy information.

5. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: During the running of the test project corresponding to the test project file, in response to a file reload prediction operation, obtaining a target sub-file input by the file reload prediction operation, the target sub-file being obtained by modifying the test project file; A file reloading simulation is performed on the target sub-file, and a file reloading prediction result is obtained based on memory space occupation information of the target sub-file in the corresponding target memory chip after the file reloading.

6. The method according to claim 5, characterized in that The performing of the file reloading simulation on the target sub-file and obtaining a file reloading prediction result based on the memory space occupation information of the target sub-file in the corresponding target memory chip after the file reloading includes: Performing a file reloading simulation on the target sub-file based on the target sub-file and the configuration parameters to obtain memory space occupation information of the target sub-file in the corresponding target memory chip; Based on the file loading prediction information, determining remaining memory space information corresponding to the file type to which the target sub-file belongs in the target memory chip; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, generating a file reloading prediction result of successful file reloading; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result indicating file reloading failure is generated.

7. The method according to claim 5, characterized in that The performing of the file reloading simulation on the target sub-file and obtaining a file reloading prediction result based on the memory space occupied by the target sub-file in the corresponding target memory chip after the file reloading includes: Performing a file reloading simulation on the target sub-file based on the target sub-file and the sub-file configuration parameters of the target sub-file to obtain memory space occupation information of the target sub-file in the corresponding target memory chip; Online reading of remaining memory space information corresponding to the file type of the target sub-file in the target memory chip; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is sufficient to load the target sub-file, generating a file reloading prediction result of successful file reloading; In response to the remaining memory space information and the memory space occupation information of the target sub-file indicating that the target memory chip is insufficient to load the target sub-file, a file reloading prediction result indicating file reloading failure is generated.

8. A device for predicting loading results of a test project, characterized in that: include: The first acquisition module is used to obtain the test project file to be loaded; a first generating module, configured to generate file index information based on configuration parameters in the test project file, wherein the file index information is used to represent the distribution of each sub-file in the test project file in at least one memory chip of the test board after the test project file is loaded into the test board; a first prediction module, configured to perform a file loading simulation based on a memory model of the at least one memory chip and the file index information to obtain file loading prediction information and a file loading prediction result, wherein the memory model represents a memory space proportion corresponding to at least one sub-file in the memory chip, and the file loading prediction information represents a memory space occupation status of each sub-file in the at least one memory chip; A sending module, configured to send the test engineering file to the test board in response to the file loading prediction result indicating that the file simulation loading is successful; The adjustment module is configured to adjust the configuration parameters of the test engineering file in response to the file loading prediction result indicating that the file simulation loading fails.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is configured to execute a computer program stored in the memory, and when the computer program is executed, implements the method described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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