Test system, method and device, electronic equipment, medium and product

Abstract

The invention discloses a test system, method and device, electronic equipment, a medium and a product, and relates to the technical field of hardware testing, an input end component and an output end component of a memory are integrated on the test system to test a power manager, and a test scheme does not depend on a complex structure of a mainboard, so that the test complexity is reduced.

Description

Technical Field

[0001] The present application relates to the field of hardware testing technology, and in particular to testing systems, methods, devices, electronic equipment, media, and products. Background Art

[0002] Memory is a component that temporarily stores data and programs while a computer system is running. Memory provides high-speed, random access data storage. The proper functioning of memory depends on the proper power supply from the power manager. The stability of the power supply from the power manager is crucial to ensuring stable memory operation.

[0003] In the related art, testing the power manager needs to rely on the components of the motherboard. However, the structure of the motherboard is complex, which leads to the problem of complex testing. Summary of the Invention

[0004] The present application provides a testing system, method, device, electronic device, medium and product to at least solve the problem of complex testing in related technologies.

[0005] The present application provides a test system, comprising: multiple input end interfaces, multiple input end components, a power manager slot, multiple output end components, and multiple output end interfaces; wherein the input end interface is connected to a first power supply, and the input end interface is used to receive an input voltage; the power manager slot is connected to the power manager through multiple pins, and the power manager is connected to multiple input end components and multiple output end components to form multiple test circuits, and the test circuit includes a circuit between the power manager and at least one input end component and at least one output end component; multiple test circuits are connected to the input end interface and the output end interface, the input end interface is used to receive an input voltage, and the multiple test circuits are used to process the input voltage and output it through the output end interface to obtain multiple output voltages, so as to test the compatibility of the power manager with the input end components and the output end components based on the input voltage and the multiple output voltages.

[0006] The present application also provides a testing method, which is applied to a testing system, the testing system including multiple input end interfaces, multiple input end components, a power manager card slot, multiple output end components, and multiple output end interfaces; the method includes: receiving a test request, the test request including a target identifier of the power manager; determining multiple test circuits corresponding to the target identifier according to the test request, the test circuit including a circuit between the power manager and at least one input end component and at least one output end component; receiving an input voltage of a first power supply through the input end interface; processing the input voltage respectively through multiple test circuits, and outputting it through the output end interface to obtain multiple output voltages; determining the compatibility between the power manager and the input end component and the output end component according to the input voltage and the multiple output voltages.

[0007] The present application also provides a testing device, which is applied to a testing system, wherein the testing system includes multiple input interfaces, multiple input components, a power manager slot, multiple output components, and multiple output interfaces; the device includes: a receiving module for receiving a test request, the test request including a target identifier of the power manager; a determination module for determining, based on the test request, multiple test circuits corresponding to the target identifier, the test circuit including a circuit between the power manager and at least one input component and at least one output component; a processing module for receiving an input voltage of a first power supply through the input interface; a testing module for processing the input voltage respectively through multiple test circuits and outputting it through the output interface to obtain multiple output voltages; a calculation module for determining the compatibility between the power manager and the input components and the output components based on the input voltage and the multiple output voltages.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned testing methods when executing the computer program.

[0009] The present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned testing methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned testing methods when executed by a processor.

[0011] Through this application, the input and output components of the memory are integrated on the test system to test the power manager. The test solution does not rely on the complex structure of the motherboard, thereby reducing the complexity of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of an application scenario of a test system provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of the structure of a test system provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of the test system provided in an embodiment of the present application;

[0016] Figure 4 A schematic diagram of the structure of the test system provided in an embodiment of the present application;

[0017] Figure 5 A schematic diagram of the structure of the test system provided in an embodiment of the present application;

[0018] Figure 6 A flow chart of a testing method provided in an embodiment of the present application;

[0019] Figure 7 A flow chart of a testing method provided in an embodiment of the present application;

[0020] Figure 8 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0021] Figure 9 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0022] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0025] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0026] For example, memory is a component that temporarily stores data and programs during a computer system's operation. Memory provides high-speed, random-access data storage. Modern memory is primarily based on semiconductor technology and is divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM uses capacitors to store charge to represent data ("1" or "0") and is periodically refreshed to maintain data integrity. This application uses DRAM as an example. SRAM uses flip-flop circuits to store data, requiring no refresh and offering faster access speeds but higher costs.

[0027] For example, DRAM includes the fourth-generation Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4) and the fifth-generation Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5). Both DDR4 and DDR5 require a power manager to operate. The power manager manages the distribution, conversion, regulation, and monitoring of electrical energy, ensuring that the memory receives the rated voltage and current, thereby ensuring proper operation. Therefore, the proper operation of the power manager is crucial to ensuring the proper operation of the memory. Testing the power manager to determine whether it is functioning properly is crucial for memory operation.

[0028] In related technologies, a power manager is installed on the motherboard, working in conjunction with other motherboard components to implement power management. During testing, the power manager, installed on the motherboard, is also tested in-situ, testing both the power manager and the motherboard components. This testing relies on the motherboard's components, which are complex in structure, leading to high testing complexity.

[0029] This application designs a test system that integrates the components required for memory operation on the test system, installs the power manager to be tested on the motherboard to test the working conditions of the power manager and the components of the test system without relying on a complex motherboard, thereby reducing the complexity of the test.

[0030] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] Combined with the specific application environment architecture that the test system execution depends on, the specific application environment architecture is described here. Figure 1 , Figure 1 The power manager is installed on the test system, and the installed test system is tested to obtain the test results of the power manager.

[0032] For example, a motherboard has many interfaces and circuits to support host operation, resulting in a complex structure. However, a test system specifically designed for testing power managers has a simpler structure. Therefore, using a test system to test power managers can effectively reduce testing complexity.

[0033] Figure 2 A schematic diagram of the structure of the test system provided in the embodiment of the present application is shown in FIG. Figure 2As shown, an embodiment of the present application provides a test system, comprising: a plurality of input end interfaces, a plurality of input end components, a power manager card slot, a plurality of output end components, and a plurality of output end interfaces; wherein,

[0034] The input terminal interface is connected to the first power supply, and the input terminal interface is used to receive an input voltage;

[0035] The power manager card slot is connected to the power manager through a plurality of pins, and the power manager is connected to a plurality of input-end components and a plurality of output-end components to form a plurality of test circuits, wherein the test circuit includes a circuit between the power manager and at least one input-end component and at least one output-end component;

[0036] Multiple test circuits are connected to the input interface and the output interface. The input interface is used to receive an input voltage. The multiple test circuits are used to process the input voltage and output it through the output interface to obtain multiple output voltages, so as to test the adaptability of the power manager with the input components and the output components based on the input voltage and the multiple output voltages.

[0037] Exemplarily, the test system integrates multiple circuits, and electrical connections between structures on the test system are achieved through the multiple circuits.

[0038] Exemplarily, the power manager slot is used to install the power manager. The power manager slot includes a plurality of pins, and an electrical connection between the test system and the power manager is achieved through the plurality of pins.

[0039] Exemplarily, the power manager may be a power management integrated circuit (PMIC for short).

[0040] For example, the power manager receives voltage and converts it to a voltage suitable for components on the memory (e.g., memory chips). Testing the power manager is used to evaluate whether the power manager's voltage conversion function can meet the memory requirements.

[0041] Exemplarily, the input-end component and the output-end component are used to control the voltage and work together with the power manager to achieve voltage conversion.

[0042] Optionally, the component (i.e., input-end component or output-end component) includes, but is not limited to, at least one of the following structures: a capacitor, an inductor, a sensor, or a resistor. The function of the component includes, but is not limited to, at least one of the following: filtering, voltage regulation, protection circuit, feedback, or level conversion.

[0043] In this scenario example, in DDR4, the power manager is installed and runs on the motherboard. In DDR5, the power manager is installed and runs on the memory. Testing the DDR5 power manager should be done off the motherboard to ensure that the test results match the actual operating conditions of the DDR5 power manager, thereby improving test accuracy.

[0044] Exemplarily, the multiple input-end components correspond to different models or types. The multiple output-end components correspond to different models or types. The test system is used to perform tests to determine the compatibility between the power manager to be tested and the different input-end components and output-end components.

[0045] For example, during the test system test process, the power manager is combined with some components of multiple input-end components and some components of multiple output-end components to obtain multiple test circuits. The voltage conversion results of the multiple test circuits are tested separately to obtain the adaptability between power managers and components in different combinations.

[0046] Using scenario examples, we can illustrate that different companies produce different memory, and different models of memory produced by the same company can also differ. Different memory components also differ. The power manager and components work together during memory use, so testing requires verifying the compatibility of the power manager and components to accurately reflect the memory's test performance. By testing compatibility, we can correctly combine the power manager and components during memory development, thereby improving overall memory performance.

[0047] Exemplarily, the first power supply is an external power supply of the test system, which is used to power the test system. The voltage output by the output interface of the test system can be used to determine the voltage conversion performance of the power manager and components working together, thereby obtaining a test result.

[0048] Using a scenario example, when the memory is in use, the input voltage includes multiple voltages, which are used to power different memory components. These power-consuming components include, but are not limited to, the memory core, charge pump, register clock driver, serial presence detect controller, or sensor. Multiple input interfaces are used to receive multiple voltages. Multiple output interfaces are used to output multiple voltages to simulate actual memory operation, where the power manager separately powers different memory components. Test results are determined based on whether the multiple voltages output by the power manager meet the requirements of the memory components.

[0049] The test system provided in the embodiment of the present application integrates the input and output components of the memory on the test system to test the power manager. The test solution does not rely on the complex structure of the motherboard, thereby reducing the complexity of the test.

[0050] A feasible implementation method is Figure 3 As shown, Figure 3 The diagram below shows the structure of the test system. Multiple input components are connected in parallel. For any input interface, the input interface is connected to multiple input components.

[0051] Exemplarily, each input-end interface is connected to a plurality of input-end components respectively, that is, a plurality of input-end components share a plurality of input-end interfaces.

[0052] In this scenario example, multiple input components are used to form multiple test circuits. These multiple input interfaces receive different voltages to perform different tests on the test circuits. By sharing multiple input interfaces across multiple input components, multiple input interfaces can be used to input voltages to multiple test circuits, achieving input interface reuse.

[0053] Optionally, the input terminal components can be used to filter, stabilize, and protect the input voltage.

[0054] In this feasible implementation, the input end interface is multiplexed to enable the input end interface to input voltages to multiple test circuits, thereby reducing the number of components in the test system and lowering the complexity of the test.

[0055] A feasible implementation method is Figure 4 As shown, Figure 4 This is a schematic diagram of the test system. The test system also includes multiple first dip switches, each with its first end connected to the input interface and its second end connected one-to-one with the multiple input components. The multiple first dip switches are used to switch the connectivity between the multiple input components to test the compatibility between the power manager and the multiple input components.

[0056] Illustratively, the first dip switch is used to switch the connectivity between the input interface and the input component. When the first dip switch is closed, the corresponding input interface and the input component are connected, and the corresponding test circuit is connected and tested. When the first dip switch is open, the corresponding input interface and the input component are disconnected, and the corresponding test circuit is disconnected.

[0057] Exemplarily, the plurality of first dip switches are independently controlled, and the connection state of any one first dip switch does not affect the connection state of other first dip switches.

[0058] Optionally, a test circuit may include at least one input terminal component. If a test circuit includes one input terminal component, a corresponding first dip switch is closed during testing. If a test circuit includes multiple input terminal components, multiple corresponding first dip switches are closed during testing.

[0059] In this feasible implementation, by independently controlling the plurality of first dip switches, the test circuit can be switched with a simple structure, thereby reducing the complexity of the test system.

[0060] In a feasible implementation manner, multiple output end components are connected in parallel; for any output end interface, the output end interface is respectively connected to multiple output end components.

[0061] Exemplarily, each output-end interface is connected to a plurality of output-end components respectively, that is, a plurality of output-end components share a plurality of output-end interfaces.

[0062] Optionally, the output terminal components can be used to filter, provide feedback, and perform load regulation on the output voltage.

[0063] In this scenario example, multiple output components are used to form multiple test circuits. These multiple output interfaces receive different voltages to perform different tests on the test circuits. By sharing multiple output interfaces across multiple output components, these interfaces can output voltages to multiple test circuits, enabling output interface reuse.

[0064] In this feasible implementation, the output end interface is multiplexed to enable the output end interface to output voltages to multiple test circuits, thereby reducing the number of components in the test system and lowering the complexity of the test.

[0065] In a feasible implementation method, the test system also includes multiple second dip switches, wherein the first ends of the multiple second dip switches are all connected to the output end interface, and the second ends of the multiple second dip switches are connected one-to-one with the multiple output end components. The multiple second dip switches are used to switch the connectivity status of the multiple output end components to test the compatibility between the power manager and the multiple output end components respectively.

[0066] Illustratively, the second dip switch is used to switch the connection state between the output interface and the output component. When the second dip switch is closed, the corresponding output interface and the output component are connected, and the corresponding test circuit is connected and tested. When the second dip switch is open, the corresponding output interface and the output component are disconnected, and the corresponding test circuit is disconnected.

[0067] Exemplarily, the plurality of second dip switches are independently controlled, and the connection state of any second dip switch does not affect the connection state of other second dip switches.

[0068] Optionally, a test circuit may include at least one output terminal component. If a test circuit includes one output terminal component, a corresponding second dip switch is closed during testing. If a test circuit includes multiple output terminal components, multiple corresponding second dip switches are closed during testing.

[0069] Combined with the scenario example, the test circuit includes a power manager and components. For the test of a power manager, multiple test circuits are switched by a dip switch to test the adaptability of the power management in multiple test circuits.

[0070] In this feasible implementation, by independently controlling the plurality of second dip switches, the test circuit can be switched with a simple structure, thereby reducing the complexity of the test system.

[0071] A feasible implementation method is Figure 5 As shown, Figure 5 This is a schematic diagram of the test system. The test system also includes input test points and output test points. The input test points are connected to the power manager card slot and input terminal assembly and are used to connect to multiple first test devices to perform various tests on the power manager. The output test points are connected to the power manager card slot and output terminal assembly and are used to connect to multiple second test devices to perform various tests on the power manager.

[0072] Exemplarily, the input test points and the output test points are used for external test equipment.

[0073] Combined with the scenario example, the performance of the power management card includes multiple dimensions. The power management card can be tested from multiple dimensions through external test equipment to fully determine the performance of the power management card.

[0074] Optionally, the test items include but are not limited to at least one of the following: conversion efficiency test, input linearity adjustment test, load adjustment test, load dynamic response test, or ripple voltage test, etc.

[0075] In this feasible implementation, the performance of the power management card can be comprehensively evaluated through multiple test items, thereby improving the accuracy of the test.

[0076] In a feasible implementation, the first test device includes but is not limited to at least one of the following: a first load meter, a second power supply, or a first oscilloscope; the second test device includes but is not limited to at least one of the following: a second load meter, or a second oscilloscope.

[0077] Exemplarily, a load meter is a device used to simulate a real load, and simulates load conditions of different powers and power factors by adjusting the values ​​of components such as resistance, inductance or capacitance.

[0078] For example, an oscilloscope is used to display the waveform of an electrical signal, and the characteristics of the electrical signal, such as frequency, amplitude, phase, and distortion, can be analyzed based on the waveform.

[0079] Exemplarily, the second power supply is configured to provide direct current.

[0080] In this feasible implementation, multiple test items can be executed through multiple test devices, thereby improving the comprehensiveness of the test.

[0081] Figure 6 A flow chart of the test method provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, the embodiment of the present application provides a testing method, which is described in detail as follows:

[0082] S601: Receive a test request, where the test request includes a target identifier of a power manager.

[0083] The testing method is applied to a testing system, which includes a plurality of input-end interfaces, a plurality of input-end components, a power manager card slot, a plurality of output-end components, and a plurality of output-end interfaces.

[0084] Exemplarily, the target identifier may be a serial number, code, or name of the power manager. The target identifier is used to accurately identify the power manager to be tested, thereby accurately determining the corresponding test strategy.

[0085] Illustratively, the test request is used to trigger a test on the power manager.

[0086] S602: Determine, according to the test request, a plurality of test circuits corresponding to the target identifier, where the test circuits include circuits between the power manager and at least one input-end component and at least one output-end component.

[0087] Exemplarily, the plurality of test circuits are test circuits whose compatibility with the power manager is to be determined. The compatibility between the plurality of test circuits and the power manager is determined by the test method, thereby assisting the research and development of the memory.

[0088] In this scenario example, each test circuit includes a combination of a power manager and input and output components. The test determines the most compatible combination, and memory is developed based on the input and output components in this combination.

[0089] S603: Receive an input voltage from a first power source through an input interface.

[0090] Exemplarily, the input voltage corresponds to an input voltage of a memory corresponding to the power manager.

[0091] In combination with the scenario example, the input voltages of the memory corresponding to the power manager in actual working conditions include 12V and 3.3V, and the input voltages received by the input interface of the test system are 12V and 3.3V.

[0092] S604 , processing the input voltages respectively through multiple test circuits, and outputting the voltages through output end interfaces to obtain multiple output voltages.

[0093] Exemplarily, after each test circuit is tested, a plurality of output voltages corresponding to the test circuit are recorded, and the compatibility between the power manager and the input component and the output component in the corresponding test circuit is determined based on the plurality of output voltages.

[0094] For example, the power manager works in conjunction with the input and output components to perform voltage conversion. In the test system, the input voltage is the voltage before conversion, and the output voltage is the voltage after conversion. The output voltage can be used to determine the conversion effect of the power manager working in conjunction with the input and output components, thereby evaluating whether the power manager's voltage conversion function meets the memory requirements.

[0095] In this scenario, the voltage output by the power manager is used to power multiple memory components. The rated operating conditions of these memory components are fixed values. By comparing multiple output voltages and multiple rated operating conditions, we can determine whether the power manager's voltage conversion function can meet the memory requirements.

[0096] S605: Determine compatibility between the power manager and the input-end component and the output-end component according to the input voltage and the multiple output voltages.

[0097] Exemplarily, multiple input end interfaces respectively receive multiple input voltages, and multiple output end interfaces respectively output multiple output voltages. Through the input voltage and output voltage, the conversion result of the power manager for each input voltage can be determined, thereby evaluating the adaptability between the power manager and the input end components and the output end components.

[0098] The test method provided in an embodiment of the present application includes receiving a test request, the test request including a target identifier of a power manager; determining, based on the test request, multiple test circuits corresponding to the target identifier, the test circuits including circuits between the power manager and at least one input component and at least one output component; receiving an input voltage of a first power supply through an input interface; processing the input voltage through multiple test circuits and outputting it through an output interface to obtain multiple output voltages; and determining the compatibility between the power manager and the input component and the output component based on the input voltage and the multiple output voltages. The above scheme uses a simple test system to simulate the working environment of the power management for testing, does not rely on the complex structure of the motherboard, and thus reduces the complexity of the test.

[0099] Based on any of the above embodiments, Figure 7 , the detailed process of the test method is described.

[0100] Figure 7 A flow chart of a test method provided in an embodiment of the present application. Figure 7 As shown, the method includes:

[0101] S701: Receive a test request, where the test request includes a target identifier of a power manager.

[0102] It should be noted that the execution process of S701 refers to S601 and will not be repeated here.

[0103] S702: Determine a pre-trained circuit prediction model, where the circuit prediction model is trained based on a plurality of sample memory information, where the sample memory information includes a power manager identifier and a component identifier of the sample memory.

[0104] Exemplarily, the sample memory information is determined from multiple sample memories, and the sample memory information includes identifiers of the power manager, input components, and output components in each sample memory. Based on the multiple sample memory information, a mapping relationship between the power manager and the input components and the output components can be determined.

[0105] For example, through model training, the circuit prediction model can learn the abstract mapping relationship between the power manager and the input components and output components, thereby predicting the input components and output components corresponding to the power manager.

[0106] S703: Input the target identifier into the circuit prediction model to obtain multiple target component identifier combinations.

[0107] Exemplarily, the multiple target component identifiers correspond to multiple target component combinations, and each target component combination includes an identifier of at least one input-end component and an identifier of at least one output-end component.

[0108] Exemplarily, the circuit prediction model outputs multiple feasible combinations of target component identifiers based on the target identifier, and the multiple target component identifier combinations are all feasible combinations verified on the sample memory.

[0109] S704: Determine multiple test circuits according to multiple target component identification combinations, where the test circuits include at least one input-end component and at least one output-end component corresponding to one target component identification combination.

[0110] Exemplarily, based on a plurality of target component identification combinations, a plurality of input-end components and a plurality of output-end components on the test system are combined to obtain a plurality of test circuits, each test circuit including one combination.

[0111] Combined with the scenario example, the circuit prediction model outputs feasible combinations to narrow the scope of the test. Next, the corresponding test circuit is determined based on the feasible combinations for testing.

[0112] Based on the above implementations, the circuit prediction model can accurately determine a combination of feasible test circuits, thereby narrowing the scope of the test and improving the efficiency of the test.

[0113] S705: Receive an input voltage from a first power source through an input interface.

[0114] For example, it should be noted that the execution process of S705 refers to S603 and will not be repeated here.

[0115] S706. Switch the connectivity status of multiple input end components through multiple first dip switches, and / or switch the connectivity status of multiple output end components through multiple second dip switches to switch multiple test circuits, so as to process the input voltage respectively through the multiple test circuits.

[0116] The test system further includes a plurality of first dip switches and a plurality of second dip switches.

[0117] Exemplarily, the plurality of first dip switches are independently controlled, and the plurality of second dip switches are independently controlled.

[0118] Exemplarily, the plurality of first dip switches and the plurality of second dip switches are controlled to be on and off by instructions.

[0119] For example, if any one of the first dip switches is closed by command control, the corresponding input end component is in a connected state. If any one of the first dip switches is opened by command control, the corresponding input end component is in a disconnected state. The same applies to the second dip switch.

[0120] Based on the above implementation, multiple test circuits can be quickly switched through the first dip switch and the second dip switch through instructions, thereby reducing manual operations and improving test efficiency.

[0121] S707 : Determine compatibility between the power manager and the input-end component and the output-end component according to the input voltage and the multiple output voltages.

[0122] In a feasible implementation, the test system also includes an input test point and an output test point; the test method also includes: performing multiple test items on the power manager by switching the first test device connected to the input test point, and / or switching the second test device connected to the output test point to obtain multiple test results; the first test device includes but is not limited to at least one of the following: a first load meter, a second power supply, or a first oscilloscope; the second test device includes but is not limited to at least one of the following: a second load meter, or a second oscilloscope.

[0123] Illustratively, different combinations of the first test device and the second test device can execute different test items.

[0124] Optionally, a plurality of first test devices are connected in parallel to the input test point, and the connection status of the plurality of first test devices is switched to switch the test item. The same applies to the second test device.

[0125] In this feasible implementation, by switching between the first test device and the second test device, different test items can be executed, thereby evaluating the power manager from multiple dimensions to improve the accuracy of the test.

[0126] A feasible implementation method can execute multiple test items and obtain multiple test results by the following method, including: adjusting the first load meter to multiple first preset load values, and determining the first test result through the recording results of the first oscilloscope and the second oscilloscope; adjusting the voltage of the second power supply to multiple first preset voltage ranges, adjusting the second load meter to multiple second preset load values, and determining the second test result through the recording results of the second oscilloscope; adjusting the second load meter to multiple first preset load conditions, and determining the third test result through the recording results of the second oscilloscope; adjusting the second load meter to multiple preset load jump conditions, and determining the fourth test result through the recording results of the second oscilloscope; adjusting the voltage of the second power supply to multiple second preset voltage ranges, adjusting the second load meter to multiple second preset load conditions, and determining the fifth test result through the recording results of the second oscilloscope under a preset bandwidth; determining multiple test results including the first test result, the second test result, the third test result, the fourth test result, and the fifth test result.

[0127] Exemplarily, the first test result is a conversion efficiency test result. The first load meter is adjusted to a first preset load value (e.g., 25%, 50%, 100%, etc.), the input voltage and current are recorded using a first oscilloscope, and the output power and current are recorded using a second oscilloscope. The first test result can be obtained by calculating the ratio of the output voltage / current product to the input voltage / current product.

[0128] Exemplarily, the second test result is an input linearity adjustment test result. The load is adjusted to any second preset load value (e.g., 50%, 100%, etc.) using a second load meter. The load value is fixed, and the input voltage is adjusted within a first preset voltage range (e.g., 4.25V to 13.8V) using a second power supply. The output voltage corresponding to different input voltages is recorded using a second oscilloscope to obtain the second test result. The load value is then switched and voltage adjustment is performed again to obtain multiple second test results.

[0129] Exemplarily, the third test result is a load adjustment test result. The third test result is obtained by performing load adjustment by the second load meter within a load range corresponding to a plurality of first preset load conditions (e.g., 0% to 100%), and recording the output voltage in real time using a second oscilloscope during the adjustment process.

[0130] Exemplarily, the fourth test result is a load dynamic response test result. The fourth test result is obtained by adjusting the load using a second load meter under multiple preset load transition conditions (e.g., 0% to 100% to 0%), and recording the output voltage using a second oscilloscope during the adjustment process.

[0131] Exemplarily, the fifth test result is a ripple voltage test result. The fifth test result is obtained by adjusting the voltage using the second power supply within a second preset voltage range (e.g., 4.25V to 13.8V), adjusting the load within a load range corresponding to a plurality of second preset load conditions (e.g., 0% to 100%), setting the bandwidth of the second oscilloscope to a preset bandwidth (e.g., 20MHz), and recording the output voltage ripple waveform.

[0132] Optionally, the multiple test results are converted into corresponding scores according to a scoring table to obtain multiple scores. Multiple weights corresponding to the multiple test results are determined, and the multiple scores are weighted according to the multiple weights to obtain a target score. The target score is used to identify the performance of the power manager.

[0133] In this feasible implementation, multiple test results are obtained through multiple test items, and the power manager can be comprehensively evaluated from multiple dimensions, thereby improving the test accuracy of the power manager.

[0134] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0135] Figure 8 This is a schematic diagram of the structure of the test device provided in the embodiment of the present application. Figure 8 As shown, an embodiment of the present application further provides a testing device, which may include: a receiving module 81, a determining module 82, a processing module 83, a testing module 84, and a calculating module 85, wherein:

[0136] The receiving module 81 is configured to receive a test request, where the test request includes a target identifier of the power manager.

[0137] The determination module 82 is configured to determine, according to the test request, a plurality of test circuits corresponding to the target identifier, where the test circuits include circuits between the power manager and at least one input-end component and at least one output-end component.

[0138] The processing module 83 is configured to receive an input voltage from the first power source through an input interface.

[0139] The test module 84 is used to process the input voltages respectively through a plurality of test circuits and output them through the output end interface to obtain a plurality of output voltages.

[0140] The calculation module 85 is configured to determine compatibility between the power manager and the input-end component and the output-end component according to the input voltage and the plurality of output voltages.

[0141] Optionally, the receiving module 81 may execute Figure 6 S601 in the embodiment.

[0142] Optionally, the determination module 82 may execute Figure 6 S602 in the embodiment.

[0143] Optionally, the processing module 83 may execute Figure 6 S603 in the embodiment.

[0144] Optionally, the test module 84 may execute Figure 6 S604 in the embodiment.

[0145] Optionally, the calculation module 85 may execute Figure 6 S605 in the embodiment.

[0146] It should be noted that the testing device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0147] In a possible implementation, the determination module 82 is specifically configured to:

[0148] Determining a pre-trained circuit prediction model, where the circuit prediction model is trained based on a plurality of sample memory information, where the sample memory information includes a power manager identifier and a component identifier of the sample memory;

[0149] Inputting the target identification into the circuit prediction model to obtain multiple target component identification combinations;

[0150] A plurality of test circuits are determined according to a plurality of target component identification combinations, wherein the test circuits include at least one input-end component and at least one output-end component corresponding to one target component identification combination.

[0151] In a possible implementation, the test system further includes a plurality of first dip switches and a plurality of second dip switches; and a test module 84, specifically configured to:

[0152] The connectivity states of the multiple input end components are switched by multiple first dip switches, and / or the connectivity states of the multiple output end components are switched by multiple second dip switches to switch multiple test circuits, thereby processing the input voltages respectively through the multiple test circuits.

[0153] Figure 9 A schematic diagram of the structure of a test device provided in an embodiment of the present application. Figure 8 Based on the embodiment shown, Figure 9 As shown, the test device 80 further includes a switching module 86, wherein:

[0154] a switching module 86 configured to execute multiple test items on the power manager by switching the first test device connected to the input test point and / or the second test device connected to the output test point to obtain multiple test results;

[0155] The first test equipment includes but is not limited to at least one of the following: a first load meter, a second power supply, or a first oscilloscope;

[0156] The second testing equipment includes, but is not limited to, at least one of the following: a second load meter, or a second oscilloscope.

[0157] In a possible implementation, the switching module 86 is specifically configured to:

[0158] adjusting the first load meter to a plurality of first preset load values, and determining a first test result through recording results of the first oscilloscope and the second oscilloscope;

[0159] Adjusting the voltage of the second power supply to a plurality of first preset voltage ranges, adjusting the second load meter to a plurality of second preset load values, and determining a second test result through recording results of the second oscilloscope;

[0160] adjusting the second load meter to a plurality of first preset load conditions, and determining a third test result based on the recorded result of the second oscilloscope;

[0161] adjusting the second load meter to a plurality of preset load jump conditions, and determining a fourth test result based on the recorded results of the second oscilloscope;

[0162] adjusting the voltage of the second power supply to a plurality of second preset voltage ranges, adjusting the second load meter to a plurality of second preset load conditions, and determining a fifth test result by recording results of the second oscilloscope at a preset bandwidth;

[0163] Determining the plurality of test results includes a first test result, a second test result, a third test result, a fourth test result, and a fifth test result.

[0164] For the description of the features in the embodiment corresponding to the testing device, please refer to the relevant description of the embodiment corresponding to the testing method, and no further details will be given here.

[0165] Figure 10 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 10 As shown, the electronic device 100 provided in this embodiment includes: at least one processor 1001 and a memory 1002. Optionally, the electronic device 100 further includes a communication component 1003. The processor 1001, the memory 1002 and the communication component 1003 are connected via a bus.

[0166] During the specific implementation process, at least one processor 1001 executes the computer-executable instructions stored in the memory 1002, so that the at least one processor 1001 executes the above-mentioned test method embodiment.

[0167] The specific implementation process of the processor 1001 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0168] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0169] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0170] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0171] An embodiment of the present application further provides a non-volatile computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned test method embodiments when running.

[0172] In an exemplary embodiment, the non-volatile computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0173] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned test method embodiments are implemented.

[0174] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned test method embodiments are implemented.

[0175] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0176] The above is a detailed introduction to a test system, method, device, electronic device, medium and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A testing system, characterized in that: include: Multiple input end interfaces, multiple input end components, a power management card slot, multiple output end components, and multiple output end interfaces; wherein, The input terminal interface is connected to the first power supply, and the input terminal interface is used to receive an input voltage; The power manager card slot is connected to the power manager via a plurality of pins, and the power manager is connected to the plurality of input-end components and the plurality of output-end components to form a plurality of test circuits, wherein the test circuit includes a circuit between the power manager and at least one of the input-end components and at least one of the output-end components; The multiple test circuits are connected to the input end interface and the output end interface, the input end interface is used to receive an input voltage, and the multiple test circuits are used to process the input voltage and output it through the output end interface to obtain multiple output voltages, so as to test the compatibility of the power manager with the input end component and the output end component based on the input voltage and the multiple output voltages.

2. The test system according to claim 1, wherein: The plurality of input terminal components are connected in parallel; For any input end interface, the input end interface is connected to the multiple input end components respectively.

3. The test system according to claim 2, wherein: The test system further includes a plurality of first dial switches, wherein: The first ends of the multiple first dip switches are all connected to the input end interface, and the second ends of the multiple first dip switches are connected one-to-one with the multiple input end components. The multiple first dip switches are used to switch the connectivity status of the multiple input end components to test the compatibility between the power manager and the multiple input end components respectively.

4. The test system according to claim 1, wherein: The plurality of output end components are connected in parallel; For any output end interface, the output end interface is connected to the multiple output end components respectively.

5. The test system according to claim 4, characterized in that: The test system further includes a plurality of second dial switches, wherein: The first ends of the multiple second dip switches are all connected to the output end interface, and the second ends of the multiple second dip switches are connected one-to-one with the multiple output end components. The multiple second dip switches are used to switch the connectivity status of the multiple output end components to test the compatibility between the power manager and the multiple output end components respectively.

6. The test system according to any one of claims 1 to 5, characterized in that: The test system also includes an input test point and an output test point, wherein: The input test point is connected to the power manager card slot and the input terminal component, and the input test point is used to connect a plurality of first test devices to perform a plurality of test items on the power manager; The output test point is connected to the power manager card slot and the output end component, and the output test point is used to connect a plurality of second test devices to perform various test items on the power manager.

7. The test system according to claim 6, characterized in that: The first test equipment includes but is not limited to at least one of the following: a first load meter, a second power supply, or a first oscilloscope; The second testing equipment includes but is not limited to at least one of the following: a second load meter, or a second oscilloscope.

8. A testing method, characterized in that: A test system according to any one of claims 1 to 7, wherein the test system comprises a plurality of input end interfaces, a plurality of input end components, a power manager card slot, a plurality of output end components, and a plurality of output end interfaces; and the method comprises: receiving a test request, the test request including a target identifier of a power manager; Determining, according to the test request, a plurality of test circuits corresponding to the target identifier, the test circuits including circuits between the power manager and at least one of the input-end components and at least one of the output-end components; receiving an input voltage from a first power source via the input interface; Processing the input voltages respectively through the multiple test circuits and outputting them through the output end interface to obtain multiple output voltages; Compatibility between the power manager and the input-end component and the output-end component is determined according to the input voltage and the plurality of output voltages.

9. The testing method according to claim 8, characterized in that: Determining a plurality of test circuits corresponding to the target identifier includes: Determining a pre-trained circuit prediction model, wherein the circuit prediction model is trained based on a plurality of sample memory information, wherein the sample memory information includes a power manager identifier and a component identifier of the sample memory; Inputting the target identification into the circuit prediction model to obtain a plurality of target component identification combinations; The multiple test circuits are determined according to the multiple target component identification combinations, where the test circuits include at least one input-end component and at least one output-end component corresponding to one target component identification combination.

10. The testing method according to claim 8, characterized in that: The test system further includes a plurality of first dip switches and a plurality of second dip switches; Processing the input voltages respectively by the multiple test circuits includes: The connectivity states of the multiple input end components are switched by the multiple first dip switches, and / or the connectivity states of the multiple output end components are switched by the multiple second dip switches to switch the multiple test circuits, so that the input voltages are processed respectively by the multiple test circuits.

11. The testing method according to any one of claims 8 to 10, characterized in that: The test system further includes an input test point and an output test point; and the method further includes: Performing multiple test items on the power manager to obtain multiple test results by switching the first test device connected to the input test point and / or switching the second test device connected to the output test point; The first test equipment includes but is not limited to at least one of the following: a first load meter, a second power supply, or a first oscilloscope; The second testing equipment includes but is not limited to at least one of the following: a second load meter, or a second oscilloscope.

12. The testing method according to claim 11, characterized in that: By switching the first test device connected to the input test point and / or switching the second test device connected to the output test point, multiple test items are performed on the power manager to obtain multiple test results, including: adjusting the first load meter to a plurality of first preset load values, and determining a first test result based on the recorded results of the first oscilloscope and the second oscilloscope; adjusting the voltage of the second power supply to a plurality of first preset voltage ranges, adjusting the second load meter to a plurality of second preset load values, and determining a second test result based on the recorded result of the second oscilloscope; adjusting the second load meter to a plurality of first preset load conditions, and determining a third test result based on the recorded results of the second oscilloscope; adjusting the second load meter to a plurality of preset load jump conditions, and determining a fourth test result based on the recorded results of the second oscilloscope; adjusting the voltage of the second power supply to a plurality of second preset voltage ranges, adjusting the second load meter to a plurality of second preset load conditions, and determining a fifth test result based on the recording result of the second oscilloscope at a preset bandwidth; Determining the plurality of test results includes the first test result, the second test result, the third test result, the fourth test result, and the fifth test result.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the testing method according to any one of claims 8 to 12 when executing the computer program.

14. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the testing method according to any one of claims 8 to 12 when executed by a processor.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the testing method according to any one of claims 8 to 12 are implemented.

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