Cache space adjustment method and electronic device

Abstract

This application provides a cache space adjustment method and electronic device, which can be applied to the field of computer storage technology. The method includes: determining current input information based on a current read instruction, wherein the current input information indicates the access location of the current read instruction, and the access location is in the cache space or memory; processing the current input information using a cache prediction model to obtain target probability distribution information, wherein the target probability distribution information characterizes the probability that the access location of the next read instruction is in memory; and increasing the size of a first cache space and decreasing the size of a second cache space, or decreasing the size of the first cache space and increasing the size of the second cache space, based on the target probability distribution information. This application solves the problem in related technologies where cache space adjustment methods cannot accurately adjust the size of the cache space, leading to a decrease in cache hit rate.

Description

Technical Field

[0001] This application relates to the field of computer storage technology, specifically to a cache space adjustment method and an electronic device. Background Technology

[0002] Caching strategy is a core part of cache management. Based on different caching strategies, the computer determines how to evict data in the cache to store new data when the cache capacity reaches its limit.

[0003] In some examples, the cache contains multiple cache spaces corresponding to different caching strategies. Different types of data are stored in different cache spaces, and the size of the cache space is adaptively adjusted according to the characteristics of the stored data. In related technologies, it is impossible to accurately adjust the size of the cache space, resulting in a decrease in cache hit rate. Summary of the Invention

[0004] This application provides a cache space adjustment method and an electronic device to at least solve the problem that the cache space adjustment methods in the related art cannot accurately adjust the size of the cache space, resulting in a decrease in cache hit rate.

[0005] According to one aspect of an embodiment of this application, a cache space adjustment method is provided, comprising: determining current input information based on a current read instruction, wherein the current input information is used to indicate the access location of the current read instruction, the access location being in a cache space or memory, the cache space including a first cache space and a second cache space, the first cache space being used to store data indicated by the read instruction when it is directed to memory, and the second cache space being used to store data indicated by the read instruction when it is directed to the cache space; processing the current input information using a cache prediction model to obtain target probability distribution information, wherein the cache prediction model is trained from historical input information corresponding to historical read instructions, and the target probability distribution information characterizes the probability that the access location of the next read instruction is in memory; and, based on the target probability distribution information, increasing the size of the first cache space and decreasing the size of the second cache space, or decreasing the size of the first cache space and increasing the size of the second cache space.

[0006] According to another aspect of the embodiments of this application, an electronic device is provided, comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0007] In this embodiment, when the access location of a read instruction is in memory, the data corresponding to the read instruction is stored in the first cache space; when the access location of a read instruction is in the cache space, the data is stored in the second cache space. The cache prediction model is trained using historical input information corresponding to historical read instructions. The target probability distribution information obtained by processing the current input information using the cache prediction model can characterize the probability that the access location of the next read instruction will be in memory. Since the access location of the read instruction is either in the cache space or in memory, the probability that the access location of the next read instruction will be in the cache space can be determined. Based on the target probability distribution information, the probability that the data corresponding to the next read instruction will be stored in the first and second cache spaces can be determined. Therefore, the size of the first and second cache spaces can be adjusted accordingly to ensure that the cache space can meet the caching requirements of the data corresponding to the read instruction, effectively increasing the cache hit rate. Attached Figure Description

[0008] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 The schematic diagram illustrates a hardware environment for a cache space adjustment method according to an embodiment of this application.

[0010] Figure 2 The schematic diagram illustrates the principle of a cache space adjustment method in related technologies.

[0011] Figure 3 A flowchart illustrating a cache space adjustment method according to an embodiment of this application is shown schematically.

[0012] Figure 4 The schematic diagram illustrates the principle of a cache space adjustment method according to an embodiment of this application.

[0013] Figure 5 A schematic diagram of a first cache prediction model according to an embodiment of this application is shown.

[0014] Figure 6 A schematic diagram of a second cache prediction model according to an embodiment of this application is shown.

[0015] Figure 7 A schematic block diagram of a computer system for an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0016] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0018] The methods and embodiments provided in this application can be executed on a server, mobile terminal, computer terminal, or similar computing device. Taking running on a server as an example, Figure 1 A schematic diagram illustrating the hardware environment of a cache space adjustment method according to an embodiment of this application is provided. Figure 1 As shown, a server may include one or more ( Figure 1 Only one is shown in the image. A processor 102 (which may include, but is not limited to, a microprocessor or programmable logic device) and a memory 104 for storing data are also shown. The server may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server described above. For example, the server may also include components that are more complex than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0019] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the cache space adjustment method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0020] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0021] Optionally, the cache space adjustment method in this embodiment can be executed by the server. Here, "server" refers to the entire server, including the relevant components within the server that need to execute the cache space adjustment method, as well as the processor, etc. The cache space adjustment method in this embodiment can also be executed by the processor 102. In some examples of this embodiment, the cache space adjustment method is described using the server as an example.

[0022] Caching strategies (eviction policies) are a core part of cache management. Different caching strategies determine how to evict data from the cache to make room for new data when the cache capacity reaches its limit. Common caching strategies include First-In-First-Out (FIFO), Least Recently Used (LRU), and Least Frequently Used (LFU). These strategies determine how to evict data from the cache to make room for new data when the cache space reaches its capacity limit.

[0023] Adaptive Replacement Cache (ARC) is an eviction algorithm that combines LRU and LFU caching strategies. ARC combines the characteristics of both LRU and LFU, ensuring that the cache does not solely retain the most recently accessed or most frequently accessed data, and adaptively adjusts the size of the ghost list (cache space size) based on hits to increase space utilization.

[0024] Figure 2 The schematic diagram illustrates the principle of a cache space adjustment method in related technologies.

[0025] like Figure 2 As shown, Figure 2 This diagram illustrates the principle of ARC (Archived Access Cache) cache space adjustment. The cache space includes a Most Recently Used (MRU) list and a Most Frequently Used (MFU) list. The MRU list manages the eviction of recently accessed data blocks, corresponding to the LRU (Least Recently Used) cache policy. The MFU list manages the eviction of the most frequently accessed data blocks, corresponding to the LFU (Least Frequently Used) cache policy.

[0026] The read module is used to initiate read commands. Recently, the Ghost MRU linked list has been used to store data to be evicted from the MRU linked list, while the Ghost MFU linked list has been used most frequently to store data to be evicted from the MFU linked list. The evictation module is used to evict data within the Ghost MRU and Ghost MFU linked lists when their evictation conditions are triggered.

[0027] like Figure 2 As shown, the read module initiates a read command, traversing the MRU, MFU, Ghost MRU, and GhostMFU lists. If the data to be accessed does not exist in any of these four lists, the access miss occurs. The disk reader then retrieves the data block from memory, adds it to the MRU list, and increments the access frequency of this data block by 1, initially setting the access frequency to 0.

[0028] If the accessed data is found in the MRU list, increment the access frequency of the data block by 1, move it from the MRU list to the MFU list, and insert it at the beginning of the data blocks with the same access frequency.

[0029] If the accessed data is found in the MFU linked list, increment the access frequency of the data block by 1 and move it to the first position of the data blocks with the same access frequency.

[0030] When the MRU and MFU linked lists trigger the eviction condition (no available space), data blocks are evicted starting from the tail and added to the head of their respective Ghost linked lists, and the access frequency of the data blocks is reset to zero.

[0031] If the accessed data is not found in either the MRU or MFU linked lists, search the Ghost MRU and Ghost MFU linked lists. If a data block is found in the Ghost MRU list, add it to the MRU list; if a data block is found in the Ghost MFU list, add it to the MFU list. The access frequency of the added data block is incremented by 1, it is inserted at the head of the data block with an access frequency of 1, and the space in that linked list is incremented by 1, while the space in the other linked list is decremented by 1. It should be noted that incrementing the linked list space by 1 here refers to adding the space of one data block.

[0032] For example, if a read instruction hits the Ghost MRU list, the data block indicated by the read instruction is moved from the Ghost MRU list to the MRU list, while simultaneously expanding the space of the MRU list and decreasing the space of the MFU list.

[0033] When there is no available space in the Ghost MRU and Ghost MFU linked lists, data blocks can be evicted from the tail of the linked list using the evicting module. The evicted data blocks are then destroyed and returned to disk.

[0034] In some examples, when the read module initiates a read operation, the ARC's four linked lists are accessed in the following order: MRU list, MFU list, Ghost MRU list, and Ghost MFU list. Traversing from the head of the list, in the worst case, if the target is found at the tail of the Ghost MFU list, all four linked lists need to be traversed completely, which incurs a significant time cost.

[0035] The cache space (i.e., cache space) is adjusted based on hits on the Ghost list. Each hit triggers an adjustment (e.g., expanding the MRU list and shrinking the MFU list when a Ghost MRU hit occurs). This mechanism lacks stability and is prone to resource contention due to short-term access fluctuations. For example, frequent hits on the Ghost MRU list can cause the MFU list to be compressed to its minimum size. Subsequently, when access patterns shift to the MRU list, the smaller MFU list triggers frequent evictions, increasing the search frequency of the Ghost MFU list and creating a vicious cycle. These problems reduce cache hit rate and system efficiency.

[0036] This shows that the relevant technology cannot accurately adjust the size of the cache space, resulting in a decrease in cache hit rate.

[0037] To address the aforementioned issues, this application provides a method for adjusting cache space.

[0038] Figure 3 A flowchart illustrating a cache space adjustment method according to an embodiment of this application is shown schematically.

[0039] like Figure 3 As shown, the cache space adjustment method of this embodiment includes operations S310 to S330.

[0040] In operation S310, the current input information is determined according to the current read instruction. The current input information is used to indicate the access location of the current read instruction. The access location is in the cache space or memory. The cache space includes a first cache space and a second cache space. The first cache space is used to store the data indicated by the read instruction when it is directed to memory, and the second cache space is used to store the data indicated by the read instruction when it is directed to the cache space.

[0041] Caches are used to improve the speed at which the Central Processing Unit (CPU) accesses data. Caches are typically composed of faster Static Random Access Memory (SRAM). Main memory is typically composed of Dynamic Random Access Memory (DRAM), which has a larger capacity but is relatively slower.

[0042] Cache and memory work together to optimize system performance. When the CPU processes a read instruction, it first checks the cache for the data specified by the read instruction. If the cache hits, the data is quickly read directly from the cache. If the cache misses, the data needs to be read from memory and copied to the cache so that it can be retrieved faster in subsequent accesses.

[0043] In this embodiment, the current input information is used to indicate the access location of the current read instruction, which is either in the cache space or in memory. The cache space and memory are traversed according to the current read instruction. If a cache hit occurs, it indicates that the access location of the current read instruction is in the cache space; if the data indicated by the current read instruction is stored in memory, it indicates that the access location of the current read instruction is in memory.

[0044] In this embodiment of the application, the cache space includes a first cache space and a second cache space. The first cache space is used to store the data indicated by the read instruction when it is directed to memory, and the second cache space is used to store the data indicated by the read instruction when it is directed to the cache space.

[0045] For example, the first cache space may include an MRU linked list. When the current read instruction's access location is in memory, the data indicated by the current read instruction can be stored in the MRU linked list for faster retrieval in subsequent accesses. The second cache space may include an MFU linked list. When the current read instruction's access location is in a cache space (either the first or second cache space), the data indicated by the current read instruction can be stored in the MFU linked list. When the current read instruction's access location is in the first cache space, the data indicated by the current read instruction can be moved from the MRU linked list to the MFU linked list. When the current read instruction's access location is in the second cache space, the access frequency of the data indicated by the current read instruction in the MFU linked list can be incremented by 1.

[0046] In this embodiment, the data type of the current input information can be a vector. The current input information is determined based on the current read instruction; that is, a corresponding vector is generated based on the access position of the current read instruction. The vector is used to indicate whether the access position of the current read instruction is in the cache space or memory.

[0047] For example, the data type of the current input information can be a two-dimensional vector. If the current input information is (1, 0), it means the current read instruction is accessing memory. If the current input information is (0, 1), it means the current read instruction is accessing a cached location.

[0048] When operating S320, the cache prediction model is used to process the current input information to obtain the target probability distribution information. The cache prediction model is trained by the historical input information corresponding to the historical read instructions, and the target probability distribution information represents the probability that the access location of the next read instruction is in memory.

[0049] In this embodiment, the cache prediction model can be trained using a recurrent neural network (RNN) based on historical input information corresponding to historical read instructions. The cache prediction model can predict the access position of the next read instruction based on the changing patterns of the access positions of historical read instructions and the current input information, thereby obtaining target probability distribution information.

[0050] In this embodiment, the target probability distribution information represents the probability that the access location of the next read instruction is in memory. Since the access location of a read instruction can only be in the cache or memory—that is, if the access location of a read instruction is not in the cache, then the access location of the read instruction is in memory—the target probability distribution information can also represent the probability that the access location of the next read instruction is in the cache.

[0051] For example, based on the target probability distribution information, it can be determined that the probability of the next read instruction accessing a location in memory is 0.7, and the probability of the next read instruction accessing a location in the cache space is also determined to be 0.3.

[0052] In operation S330, based on the target probability distribution information, the size of the first cache space is increased and the size of the second cache space is decreased, or the size of the first cache space is decreased and the size of the second cache space is increased.

[0053] In this embodiment of the application, the data type of the target probability distribution information can be a vector, and the probability that the access location of the next read instruction is in memory can be determined based on the target probability distribution information.

[0054] In this embodiment, based on the target probability distribution information, the probability that the access location of the next read instruction will be in the cache space or memory can be determined. If the access location of the next read instruction is in memory, it indicates that the data indicated by the next read instruction needs to be stored in the first cache space, and the first cache space needs to be increased to store the data. If the access location of the next read instruction is in the cache space, it indicates that the data indicated by the next read instruction needs to be stored in the second cache space, and the second cache space needs to be increased to store the data.

[0055] In this embodiment, the target probability distribution information represents the probability that the access location of the next read instruction is in memory. When the probability that the access location of the next read instruction is in memory meets a preset condition, the size of the first cache space can be increased and the size of the second cache space can be decreased accordingly, or the size of the first cache space can be decreased and the size of the second cache space can be increased. This can satisfy the space requirements of either the first or second cache space.

[0056] In this embodiment, the target probability distribution information obtained by processing the current input information using a cache prediction model can characterize the probability that the access location of the next read instruction is in memory. Based on the target probability distribution information, the probability that the data corresponding to the next read instruction will be stored in the first cache space and the second cache space can be determined. Consequently, the size of the first cache space and the size of the second cache space can be adjusted accordingly to ensure that the cache space can meet the caching requirements of the data corresponding to the read instruction, effectively increasing the cache hit rate.

[0057] The following describes the specific steps for adjusting the size of the first cache space and the size of the second cache space based on the target probability distribution information. See the following embodiment for details.

[0058] In some embodiments, based on target probability distribution information, increasing the size of the first cache space and decreasing the size of the second cache space, or decreasing the size of the first cache space and increasing the size of the second cache space, includes: increasing the size of the first cache space and decreasing the size of the second cache space when the probability is greater than a first threshold; increasing the size of the second cache space and decreasing the size of the first cache space when the probability is less than a second threshold. Wherein, the second threshold is less than the first threshold.

[0059] Figure 4 The schematic diagram illustrates the principle of a cache space adjustment method according to an embodiment of this application.

[0060] like Figure 4 As shown, the read module initiates read commands, which access locations in memory or cache space. The total size of the cache space remains unchanged; that is, the total size of the first cache space and the second cache space remains unchanged. When the read command access location is in memory, the data indicated by the read command is stored in the first cache space. When the read command access location is in the first cache space, the data indicated by the read command is moved from the first cache space to the second cache space. When the read command access location is in the second cache space, the access frequency of the data indicated by the read command in the second cache space is incremented by 1.

[0061] In this embodiment of the application, the first threshold and the second threshold are preset thresholds.

[0062] In this embodiment, if the probability that the access location of the next read instruction is in memory is greater than a first threshold, it indicates that the probability of the access location of the next read instruction being in memory is relatively high. Since the data indicated by the read instruction is stored in the first cache space when the access location of the read instruction is in memory, the size of the first cache space can be increased and the size of the second cache space can be decreased to ensure that the first cache space has available space to store the data indicated by the next read instruction.

[0063] In this embodiment, if the probability that the access location of the next read instruction is in memory is less than a second threshold, it indicates that the probability of the next read instruction accessing the location in memory is low, and the probability that the access location of the next read instruction is in the cache space is high. Since the data indicated by the read instruction is stored in the second cache space when the access location of the read instruction is in the cache space, the size of the second cache space can be increased while the size of the first cache space is decreased, so that the second cache space has available space to store the data indicated by the next read instruction.

[0064] In this embodiment of the application, the target probability distribution information can be a 64-bit floating-point number (vector form). The target probability distribution information can be compressed into the range of [-1,1] using trigonometric functions, and then mapped through a fully connected layer to map its range into the range of [0,1], thus obtaining the probability that the access location of the next read instruction is in memory.

[0065] For example, the first threshold can be set to 0.7, and the second threshold can be set to 0.3. When the target probability distribution indicates that the probability of the next read instruction accessing a memory location is 0.8, this probability value is greater than the first threshold, indicating that the probability of the next read instruction accessing a memory location is relatively high. In this case, the size of the first cache space can be increased, and the size of the second cache space can be decreased.

[0066] For example, if the probability distribution information indicates that the probability of the next read instruction accessing a location in memory is 0.2, this probability value is less than the second threshold, indicating that the probability of the next read instruction accessing a location in memory is relatively low, and the probability of the next read instruction accessing a location in the cache space is relatively high. In this case, the size of the second cache space can be increased, and the size of the first cache space can be decreased.

[0067] By comparing the probability with a first threshold and a second threshold, and adjusting the size of the first cache space and the second cache space according to the comparison result, the accuracy of adjusting the size of the first cache space and the second cache space can be improved, thereby improving the accuracy and reliability of the cache space adjustment method of this embodiment.

[0068] The specific steps for determining the second threshold will be described below. See the following example for details.

[0069] In some embodiments, the method further includes: acquiring multiple historical input information corresponding to multiple historical read instructions; determining a first number of historical input information for a first cache space from the multiple historical input information, and a second number of historical input information for a cache space from the multiple historical input information; and determining a second threshold based on the ratio of the first number to the second number, wherein the ratio is positively correlated with the second threshold.

[0070] In this embodiment, when the read instruction's access location is in memory, the data indicated by the read instruction is stored in a first cache space, and the data indicated by the read instruction is added to the first cache space. When the read instruction's access location is in a cache space, there are two possibilities: the read instruction's access location is in the first cache space, or the read instruction's access location is in a second cache space. When the read instruction's access location is in the first cache space, the data indicated by the read instruction is added to the second cache space. When the read instruction's access location is in the second cache space, since the data indicated by the read instruction already exists in the second cache space, the data indicated by the read instruction is not added to the second cache space, and the access frequency of the data indicated by the read instruction in the second cache space is increased by 1.

[0071] As can be seen from the above, when the current read instruction accesses a location in memory, the data indicated by the next read instruction will be added to the first cache space, increasing the space requirement of the first cache space. However, when the current read instruction accesses a location in the cache space, the data indicated by the next read instruction may not necessarily be added to the second cache space, and the second cache space may not necessarily require increased space.

[0072] In this embodiment, multiple historical input information corresponding to multiple historical read instructions are obtained. A first number of historical input information for the first cache space is determined from the multiple historical input information. The first number represents the number of historical input information that would increase the space requirement of the second cache space. A second number of historical input information for the cache space is determined from the multiple historical input information. The ratio of the first number to the second number represents the proportion of historical input information that would increase the space requirement of the second cache space from the multiple historical input information indicating that the access location of the read instruction is the cache space.

[0073] In this embodiment, a second threshold is determined based on the ratio of a first quantity to a second quantity. The second threshold can be preset within a threshold range, and its position within this range is determined by the ratio of the first quantity to the second quantity; the ratio is positively correlated with the second threshold.

[0074] For example, the threshold range for the second threshold is 0.1-0.3. When the ratio of the first quantity to the second quantity is 1, the second threshold is 0.3. When the ratio of the first quantity to the second quantity is 0, the second threshold is 0.1. When the ratio of the first quantity to the second quantity is 0.8, the second threshold is 0.1 + (0.3 - 0.1) × 0.8 = 0.26.

[0075] In this embodiment, a higher ratio indicates a higher probability that the space requirement of the second cache space will increase when the access location of the read instruction is in the cache space. Increasing the second threshold increases the likelihood that the probability is less than the second threshold, thereby increasing the likelihood of increasing the size of the second cache space and decreasing the size of the first cache space to meet the space requirement of the second cache space. Conversely, a lower ratio indicates a lower probability that the space requirement of the second cache space will increase when the access location of the read instruction is in the cache space. Decreasing the second threshold decreases the likelihood that the probability is less than the second threshold, thereby decreasing the likelihood of increasing the size of the second cache space and decreasing the size of the first cache space to match the space requirement of the second cache space.

[0076] By considering the access location of the read instruction in the first cache space and the second cache space in the embodiments of this application, the accuracy of the determined second threshold can be improved, so that the determined second threshold can match the actual situation, thereby improving the reliability of the cache space adjustment method of this embodiment.

[0077] The foregoing embodiments described the specific steps for determining the second threshold. The following will explain the specific steps for adjusting the size of the first cache space and the size of the second cache space when the probability is greater than the second threshold and less than the first threshold. See the following embodiments for details.

[0078] In some embodiments, increasing the size of the first cache space and decreasing the size of the second cache space, or decreasing the size of the first cache space and increasing the size of the second cache space, based on target probability distribution information, includes: obtaining the storage states of the first and second cache spaces when the probability is greater than a second threshold and less than a first threshold; decreasing the size of the first cache space and increasing the size of the second cache space when the storage state indicates that the first cache space has available space and the second cache space does not; and decreasing the size of the second cache space and increasing the size of the first cache space when the storage state indicates that the second cache space has available space and the first cache space does not.

[0079] In this embodiment, if the probability is greater than the second threshold and less than the first threshold, it indicates that the access location of the next read instruction does not have a clear bias. In this case, the size of the first and second cache spaces can be adjusted based on their storage states.

[0080] In this embodiment of the application, when the storage state indicates that the first cache space has available space and the second cache space does not have available space, the storage pressure of the second cache space can be alleviated by reducing the size of the first cache space and increasing the size of the second cache space.

[0081] In this embodiment of the application, when the storage state indicates that there is available space in the second cache space and no available space in the first cache space, the storage pressure of the first cache space can be alleviated by reducing the size of the second cache space and increasing the size of the first cache space.

[0082] By adapting the size of the first cache space and the second cache space according to their storage states in this embodiment, the storage pressure on the first cache space and the second cache space can be alleviated, thereby improving the reliability of the cache space adjustment method in this embodiment.

[0083] The foregoing embodiments described the specific steps for adjusting the first and second cache spaces. The following will explain the specific steps for processing the current input information using a cache prediction model to obtain the target probability distribution information. See the embodiments below for details.

[0084] In some embodiments, the cached prediction model is used to process the current input information to obtain target probability distribution information, including: obtaining historical probability distribution information obtained by the cached prediction model based on the input information corresponding to the previous read instruction. The cached prediction model is then used to process the current input information and the historical probability distribution information to obtain the target probability distribution information.

[0085] In this embodiment, the cache prediction model obtains historical probability distribution information based on the input information corresponding to the previous read instruction. This historical probability distribution information reflects the patterns of historical read instructions. The cache prediction model can predict the access position of the next read instruction based on the current input information and the historical probability distribution information, thus obtaining the target probability distribution information.

[0086] Through the embodiments of this application, the cache prediction model, combined with historical probability distribution information, can improve the accuracy of the obtained target probability distribution information, thereby improving the reliability of the cache space adjustment method of this embodiment.

[0087] The following will explain the two models included in the cache prediction model, and the specific steps for determining the target probability distribution information using each model. See the following examples for details.

[0088] In some embodiments, the cache prediction model includes a first cache prediction model and a second cache prediction model. The first cache prediction model includes a Long Short-Term Memory (LSTM) network, and the second cache prediction model includes a gated recurrent unit (GRU) network. The cache prediction model processes current input information and historical probability distribution information to obtain target probability distribution information, including: determining the historical number of read instructions acquired within a predetermined historical period. If the historical number is less than a preset threshold, the first cache prediction model is used to process the current input information and historical probability distribution information to obtain the target probability distribution information. If the historical number is greater than the preset threshold, the second cache prediction model is used to process the current input information and historical probability distribution information to obtain the target probability distribution information.

[0089] In this embodiment, the first cache prediction model includes a Long Short-Term Memory (LSTM) network. LSTM is a special type of RNN network that can learn and remember long-term dependencies. The first cache prediction model trained based on LSTM is suitable for scenarios where the cache space is adjusted according to read instructions over a long period of time. The first cache prediction model will not forget information from a long time ago, which can ensure the accuracy of the target probability distribution information obtained.

[0090] In this embodiment, the second cache prediction model includes a Gated Recurrent Unit (GRU) network. GRU is a special type of RNN network, similar in function and mechanism to LSTM, but simpler. The second cache prediction model trained based on GRU is more suitable for short sequence data, such as scenarios with intensive read operations within a short period. The second cache prediction model can effectively reduce computational cost and improve computational efficiency.

[0091] In this embodiment, the predetermined historical time period can be a closed interval from a predetermined historical time to the current time. The current time is the time when the current read instruction is obtained. The predetermined historical time is a pre-set time, which is located before the current time.

[0092] In this embodiment, the historical number of read instructions acquired within a predetermined historical period is determined. If the historical number is less than a preset threshold, it indicates that the number of read instructions acquired within the predetermined historical period is relatively small. In this case, a first cache prediction model can be used to process the current input information and historical probability distribution information to obtain the target probability distribution information. Using the first cache prediction model to determine the target probability distribution information ensures the accuracy of the obtained target probability distribution information.

[0093] In this embodiment, when the number of historical data exceeds a preset threshold, it indicates that a large number of read instructions have been acquired within the predetermined historical time period. The second cache prediction model can then be used to process the current input information and historical probability distribution information to obtain the target probability distribution information. Using the second cache prediction model to determine the target probability distribution information can reduce computational costs and improve computational efficiency.

[0094] By utilizing different cache prediction models to calculate based on the historical number of read instructions obtained within a predetermined historical period, the accuracy of the obtained target probability distribution information can be improved while ensuring computational efficiency.

[0095] The foregoing embodiments describe a cache prediction model including a first cache prediction model and a second cache prediction model. The specific steps for processing the current input information using the first cache prediction model to obtain the target probability distribution information will be explained below. See the embodiments below for details.

[0096] In some embodiments, the first cache prediction model includes a first filtering module, a first processing module, and a first output module. The first cache prediction model processes current input information and historical probability distribution information to obtain target probability distribution information, including: processing the current input information and historical probability distribution information using the first filtering module to obtain filtered current input information and filtered historical probability distribution information; processing the current input information and historical probability distribution information using the first processing module to obtain candidate memory states; and processing the candidate memory states, historical memory states, filtered current input information, and filtered historical probability distribution information to obtain the current memory state; and processing the current input information, historical probability distribution information, and current memory state using the first output module to obtain the target probability distribution information.

[0097] Figure 5 A schematic diagram of a first cache prediction model according to an embodiment of this application is shown.

[0098] like Figure 5 As shown, Figure 5 The diagram illustrates the probability distribution h0 output by the first cache prediction model at time t0 based on the input information x0 at time t0, where C0 represents the memory state at time t0. At time t1, the diagram shows the probability distribution h1 output by the first cache prediction model based on the input information x1 at time t1, where C1 represents the memory state at time t1. At time t2, the diagram shows the probability distribution h2 output by the first cache prediction model based on the input information x2 at time t2, where C2 represents the memory state at time t2.

[0099] The following describes the embodiments of this application using the current input information as x1, the target probability distribution information as h1, the current memory state as C1, the historical memory state as C0, and the historical probability distribution information as h0 as an example.

[0100] In this embodiment, the first cache prediction model includes a first filtering module, a first processing module, and a first output module. The first cache prediction model includes an LSTM network. The first filtering module may include the input gate and forget gate of the LSTM network. The first processing module may include the input gate and memory cell of the LSTM network. The first output module may include the output gate of the LSTM network.

[0101] In this embodiment, the activation function can be the Sigmoid activation function. The Sigmoid activation function is shown in formula (1).

[0102] (1)

[0103] In this embodiment, the input gate can be used to filter the current input information x1. Not all of the current input information x1 needs to be stored in the cell state. The input gate uses formula (2) and an activation function to filter the current input information x1 based on the current input information x1 and the historical probability distribution information h0, thus obtaining the filtered current input information I1.

[0104] (2)

[0105] in, It is the Sigmoid activation function. This is the weight matrix. This is a bias term.

[0106] In this embodiment, the forget gate can be used to filter historical probability distribution information as h0. Outdated information may exist in long-term memory. The forget gate uses formula (3) to filter historical probability distribution information h0 based on the current input information x1 and historical probability distribution information h0, and obtains the filtered historical probability distribution information Y1.

[0107] (3)

[0108] in, This is the weight matrix. This is a bias term.

[0109] In this embodiment, the input gate can calculate the candidate memory state. The input gate calculates the candidate memory state based on the current input information x1 and the historical probability distribution information h0 using formula (4). .

[0110] (4)

[0111] in, This is the weight matrix. This is a bias term.

[0112] In this embodiment, the memory cell can calculate the current memory state C1. The memory cell uses formula (5) based on the candidate memory states... The current memory state C1 is obtained by combining the historical memory state C0, the filtered current input information I1, and the filtered historical probability distribution information Y1.

[0113] (5)

[0114] in, This indicates element-wise multiplication.

[0115] In this embodiment, the output gate can calculate the target probability distribution information h1. The output gate obtains the target probability distribution information h1 based on the current input information x1, the historical probability distribution information h0, and the current memory state C1 according to formulas (6) and (7).

[0116] (6)

[0117] (7)

[0118] in, This is the weight matrix. For bias terms, This is an intermediate term.

[0119] Through the gating mechanism of this embodiment, the memory state is continuously updated, which is equivalent to retaining the experience of each past read operation. This allows the data storage indicated by a new read instruction to take historical information into account when determining whether the cache space needs to be adjusted. This can improve the accuracy of the obtained target probability distribution information, thereby improving the accuracy and reliability of the cache space adjustment method.

[0120] The following describes the specific steps for processing the current input information using the second cache prediction model to obtain the target probability distribution information. See the following example for details.

[0121] In some embodiments, the second cache prediction model includes a second filtering module, a second processing module, and a second output module. The second cache prediction model processes the current input information and historical probability distribution information to obtain target probability distribution information, including: processing the current input information and historical probability distribution information using the second filtering module to obtain filtered historical probability distribution information; processing the filtered historical probability distribution information, the current input information, and the historical probability distribution information using the second processing module to obtain candidate hidden states; and processing the current input information, historical probability distribution information, and candidate hidden states using the second output module to obtain target probability distribution information.

[0122] Figure 6 A schematic diagram of a second cache prediction model according to an embodiment of this application is shown.

[0123] like Figure 6 As shown, Figure 6 The diagram shows the probability distribution h0 output by the second cache prediction model at time t0 based on the input information x0 at time t0. At time t1 based on the input information x1 at time t1, the diagram shows the probability distribution h1 output by the second cache prediction model. At time t2 based on the input information x2 at time t2, the diagram shows the probability distribution h2 output by the second cache prediction model.

[0124] The following uses the current input information as x1, the target probability distribution information as h1, and the historical probability distribution information as h0 as an example to illustrate the embodiments of this application.

[0125] In this embodiment, the second cache prediction model includes a second filtering module, a second processing module, and a second output module. The second cache prediction model includes a GRU network, and the second filtering module may include a reset gate for the GRU network. The second processing module may include a reset gate for the GRU network. The second output module may include an update gate for the GRU network.

[0126] In this embodiment, the activation function may be a Sigmoid activation function. The Sigmoid activation function has been described in the foregoing embodiments and will not be repeated here.

[0127] In this embodiment, a reset gate is used to filter historical probability distribution information h0. The reset gate uses formula (8) and an activation function to filter historical probability distribution information h0 based on the current input information x1 and historical probability distribution information h0, thereby obtaining the filtered historical probability distribution information R1.

[0128] (8)

[0129] in, It is the Sigmoid activation function. and This is the weight matrix. This is a bias term.

[0130] In this embodiment, the reset gate is used to calculate the candidate hidden state. The reset gate obtains the candidate hidden state using formula (9) based on the filtered historical probability distribution information R1, the current input information x1, and the historical probability distribution information h0. .

[0131] (9)

[0132] in, and This is the weight matrix.

[0133] In this embodiment, the update gate is used to calculate the target probability distribution information h1. The update gate uses formulas (10) and (11) to calculate the target probability distribution information h1 based on the current input information x1, the historical probability distribution information h0, and the candidate hidden state. Thus, the target probability distribution information h1 is obtained.

[0134] (10)

[0135] (11)

[0136] in, For the middle term, and This is the weight matrix. This is a bias term.

[0137] Through the embodiments of this application, compared with the first cache prediction model, the second cache prediction model...

[0138] It is simpler and lighter, effectively reducing the risk of overfitting. It can improve the accuracy of the obtained target probability distribution information, thereby improving the accuracy and reliability of the cache space adjustment method.

[0139] The specific steps for training the first cache prediction model and the second cache prediction model will be described below. See the following examples for details.

[0140] In some embodiments, the method further includes: acquiring a sequence of historical input information for multiple historical read instructions, wherein the sequence of historical input information includes the generation time of each historical input instruction; determining the frequency of occurrence of historical input information in the sequence of historical input information based on the generation time; and determining a first historical input information sequence and a second historical input information sequence from the sequence of historical input information based on the frequency of occurrence. The frequency of occurrence of historical input information in the first historical input information sequence is less than the frequency of occurrence of historical input information in the second historical input information sequence. The first historical input information sequence is used to train a first cache prediction model, and the second historical input information sequence is used to train a second cache prediction model.

[0141] In this embodiment, a sequence of historical input information for multiple historical read commands is obtained, wherein the sequence of historical input information includes the generation time of each historical input command. The historical input information in the sequence is arranged sequentially according to the generation time of each historical input command.

[0142] In this embodiment, the first cache prediction model includes an LSTM network. The first cache prediction model trained based on the LSTM network is suitable for scenarios where the cache space is adjusted based on read instructions over a long period of time. Therefore, the first cache prediction model can be trained using a sequence of first historical input information with a lower frequency of occurrence.

[0143] In this embodiment, the second cache prediction model includes a GRU network. The second cache prediction model trained based on the GRU network is suitable for scenarios with intensive read operations in a short period of time. Therefore, the second cache prediction model can be trained using a second historical input information sequence that appears more frequently in the historical input information.

[0144] Through the embodiments of this application, the first cache prediction model and the second cache prediction model are trained using historical input information sequences with different features, respectively, so that the obtained first cache prediction model and second cache prediction model can be applied to their respective application scenarios.

[0145] According to another aspect of the embodiments of this application, a cache space adjustment device is also provided, comprising: a first determining module, configured to determine current input information based on a current read instruction, wherein the current input information indicates the access location of the current read instruction, the access location being in a cache space or memory, the cache space including a first cache space and a second cache space, the first cache space being used to store data indicated by the read instruction when it is directed to memory, and the second cache space being used to store data indicated by the read instruction when it is directed to the cache space; a processing module, configured to process the current input information using a cache prediction model to obtain target probability distribution information, wherein the cache prediction model is trained from historical input information corresponding to historical read instructions, and the target probability distribution information characterizes the probability that the access location of the next read instruction is in memory; and an adjusting module, configured to, based on the target probability distribution information, increase the size of the first cache space and decrease the size of the second cache space, or decrease the size of the first cache space and increase the size of the second cache space.

[0146] It should be noted that the first determining module in this embodiment can be used to perform the above operation S310, the processing module in this embodiment can be used to perform the above operation S320, and the adjustment module in this embodiment can be used to perform the above operation S330.

[0147] The embodiments provided in this application utilize a cache prediction model to process the current input information to obtain target probability distribution information, which can characterize the probability that the access location of the next read instruction is in memory. Based on the target probability distribution information, the probability that the data corresponding to the next read instruction is stored in the first cache space and the second cache space can be determined. Consequently, the size of the first cache space and the size of the second cache space can be adjusted accordingly to ensure that the cache space can meet the caching requirements of the data corresponding to the read instruction, effectively increasing the cache hit rate.

[0148] In some embodiments, the adjustment module includes: a first adjustment submodule, configured to increase the size of a first cache space and decrease the size of a second cache space when the probability is greater than a first threshold; and a second adjustment submodule, configured to increase the size of a second cache space and decrease the size of a first cache space when the probability is less than a second threshold. The second threshold is less than the first threshold.

[0149] In some embodiments, the apparatus further includes: a first acquisition module, configured to acquire a plurality of historical input information corresponding to a plurality of historical read instructions; a second determination module, configured to determine a first number of historical input information for a first cache space from the plurality of historical input information, and a second number of historical input information for a cache space from the plurality of historical input information; and a third determination module, configured to determine a second threshold based on the ratio of the first number to the second number, wherein the ratio is positively correlated with the second threshold.

[0150] In some embodiments, the adjustment module includes: a first acquisition submodule, configured to acquire the storage states of a first cache space and a second cache space when the probability is greater than a second threshold and less than a first threshold; a third adjustment submodule, configured to decrease the size of the first cache space and increase the size of the second cache space when the storage states indicate that the first cache space has available space and the second cache space does not have available space; and a fourth adjustment submodule, configured to decrease the size of the second cache space and increase the size of the first cache space when the storage states indicate that the second cache space has available space and the first cache space does not have available space.

[0151] In some embodiments, the processing module includes: a second acquisition submodule, configured to acquire historical probability distribution information obtained by the cached prediction model based on the input information corresponding to the previous read instruction; and a processing submodule, configured to process the current input information and historical probability distribution information using the cached prediction model to obtain target probability distribution information.

[0152] In some embodiments, the cache prediction model includes a first cache prediction model and a second cache prediction model. The first cache prediction model includes a Long Short-Term Memory (LSTM) network, and the second cache prediction model includes a gated recurrent unit (GRU) network. The processing submodule includes: a determination unit, configured to determine the historical number of read instructions acquired within a predetermined historical period; a first processing unit, configured to process current input information and historical probability distribution information using the first cache prediction model to obtain target probability distribution information when the historical number is less than a preset threshold; and a second processing unit, configured to process current input information and historical probability distribution information using the second cache prediction model to obtain target probability distribution information when the historical number is greater than a preset threshold.

[0153] In some embodiments, the first cache prediction model includes a first filtering module, a first processing module, and a first output module. The first processing unit includes: a first filtering module, used to process current input information and historical probability distribution information to obtain filtered current input information and filtered historical probability distribution information; a first processing module, used to process current input information and historical probability distribution information to obtain candidate memory states, and to process candidate memory states, historical memory states, filtered current input information, and filtered historical probability distribution information to obtain a current memory state; and a first output module, used to process current input information, historical probability distribution information, and the current memory state to obtain target probability distribution information.

[0154] In some embodiments, the second cache prediction model includes a second filtering module, a second processing module, and a second output module. The second processing module includes: a second filtering module for processing current input information and historical probability distribution information to obtain filtered historical probability distribution information; a second processing module for processing the filtered historical probability distribution information, current input information, and historical probability distribution information to obtain candidate hidden states; and a second output module for processing current input information, historical probability distribution information, and candidate hidden states to obtain target probability distribution information.

[0155] In some embodiments, the apparatus further includes: a second acquisition module, configured to acquire a sequence of historical input information for multiple historical read instructions, wherein the sequence of historical input information includes the generation time of each historical input instruction; and a fourth determination module, configured to determine the frequency of occurrence of historical input information in the sequence of historical input information based on the generation time, and to determine a first historical input information sequence and a second historical input information sequence from the sequence of historical input information based on the frequency of occurrence. The frequency of occurrence of historical input information in the first historical input information sequence is less than the frequency of occurrence of historical input information in the second historical input information sequence. The first historical input information sequence is used to train a first cache prediction model, and the second historical input information sequence is used to train a second cache prediction model.

[0156] According to another aspect of the embodiments of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to perform the steps of any of the above method embodiments through the computer program.

[0157] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0158] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0159] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored program, wherein the program executes the steps in any of the above method embodiments when it is run.

[0160] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0161] According to another aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program / instructions comprising program code for performing the method shown in the flowchart. In such an embodiment, reference is made to... Figure 7 The computer program can be downloaded and installed from a network via the communication section 709, and / or installed from the removable medium 711. When the computer program is executed by the central processing unit 701, it performs various functions provided in the embodiments of this application. The sequence numbers of the embodiments of this application above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0162] refer to Figure 7 , Figure 7 A schematic block diagram of a computer system for an electronic device according to an embodiment of this application is shown.

[0163] Figure 7 A schematic block diagram of a computer system architecture for implementing embodiments of the present application is shown. Figure 7 As shown, the computer system 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 702 or programs loaded from storage section 708 into random access memory (RAM) 703. The RAM 703 also stores various programs and data required for system operation. The CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output interface 704 (I / O interface) is also connected to the bus 704.

[0164] The following components are connected to the input / output interface 704: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a local area network card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the input / output interface 704 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0165] Specifically, according to embodiments of this application, the processes described in the various method flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 709, and / or installed from removable medium 711. When the computer program is executed by central processing unit 701, it performs various functions defined in the system of this application.

[0166] It should be noted that, Figure 7 The computer system 700 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0167] Obviously, those skilled in the art should understand that the modules or steps of the embodiments of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of this application are not limited to any particular combination of hardware and software.

[0168] The above are merely preferred embodiments of this application and are not intended to limit the embodiments of this application. For those skilled in the art, various modifications and variations can be made to the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A method for adjusting cache space, characterized in that, The method includes: The current input information is determined based on the current read instruction, wherein the current input information is used to indicate the access location of the current read instruction, the access location is in a cache space or memory, the cache space includes a first cache space and a second cache space, the first cache space is used to store the data indicated by the read instruction when it is directed to memory, and the second cache space is used to store the data indicated by the read instruction when it is directed to the cache space; The current input information is processed using a cache prediction model to obtain target probability distribution information. The cache prediction model is trained using historical input information corresponding to historical read instructions. The target probability distribution information represents the probability that the access location of the next read instruction is in the memory. Based on the target probability distribution information, the size of the first cache space is increased and the size of the second cache space is decreased, or the size of the first cache space is decreased and the size of the second cache space is increased, wherein: If the probability is greater than a first threshold, increase the size of the first cache space and decrease the size of the second cache space; If the probability is less than the second threshold, increase the size of the second cache space and decrease the size of the first cache space; Wherein, the second threshold is less than the first threshold; The method further includes: Retrieve multiple historical input information corresponding to multiple historical read commands; Determine a first number of historical input information for the first cache space from the plurality of historical input information, and a second number of historical input information for the cache space from the plurality of historical input information; The second threshold is determined based on the ratio of the first quantity to the second quantity, wherein the ratio is positively correlated with the second threshold.

2. The method according to claim 1, characterized in that, The step of increasing the size of the first cache space and decreasing the size of the second cache space, or decreasing the size of the first cache space and increasing the size of the second cache space, based on the target probability distribution information, includes: If the probability is greater than the second threshold and less than the first threshold, obtain the storage status of the first cache space and the second cache space; When the storage state indicates that the first cache space has available space and the second cache space does not have available space, the size of the first cache space is reduced and the size of the second cache space is increased. When the storage state indicates that the second cache space has available space and the first cache space does not have available space, the size of the second cache space is reduced and the size of the first cache space is increased.

3. The method according to claim 1, characterized in that, The process of using a cached prediction model to process the current input information to obtain target probability distribution information includes: Obtain the historical probability distribution information of the cache prediction model based on the input information corresponding to the previous read instruction; The target probability distribution information is obtained by processing the current input information and the historical probability distribution information using the cached prediction model.

4. The method according to claim 3, characterized in that, The cache prediction model includes a first cache prediction model and a second cache prediction model. The first cache prediction model includes a long short-term memory network, and the second cache prediction model includes a gated recurrent unit network. The step of processing the current input information and the historical probability distribution information using the cached prediction model to obtain the target probability distribution information includes: Determine the historical number of read commands acquired within the predetermined historical time period; If the number of historical data is less than a preset threshold, the first cached prediction model is used to process the current input information and the historical probability distribution information to obtain the target probability distribution information. If the number of historical data exceeds the preset threshold, the second cache prediction model is used to process the current input information and the historical probability distribution information to obtain the target probability distribution information.

5. The method according to claim 4, characterized in that, The first cache prediction model includes a first filtering module, a first processing module, and a first output module; The step of processing the current input information and the historical probability distribution information using the first cached prediction model to obtain the target probability distribution information includes: The first filtering module processes the current input information and the historical probability distribution information to obtain filtered current input information and filtered historical probability distribution information. The first processing module processes the current input information and the historical probability distribution information to obtain the candidate memory state, and processes the candidate memory state, the historical memory state, the filtered current input information and the filtered historical probability distribution information to obtain the current memory state. The target probability distribution information is obtained by processing the current input information, the historical probability distribution information, and the current memory state using the first output module.

6. The method according to claim 4, characterized in that, The second cache prediction model includes a second filtering module, a second processing module, and a second output module; The step of processing the current input information and the historical probability distribution information using the second cache prediction model to obtain the target probability distribution information includes: The second filtering module processes the current input information and the historical probability distribution information to obtain filtered historical probability distribution information. The second processing module processes the filtered historical probability distribution information, the current input information, and the historical probability distribution information to obtain the candidate hidden state; The target probability distribution information is obtained by processing the current input information, the historical probability distribution information, and the candidate hidden state using the second output module.

7. The method according to claim 4, characterized in that, The method further includes: Obtain a sequence of historical input information for multiple historical read commands, wherein the sequence of historical input information includes the generation time of each historical input command; The frequency of occurrence of historical input information in the historical input information sequence is determined based on the generation time, and a first historical input information sequence and a second historical input information sequence are determined from the historical input information sequence based on the frequency of occurrence. Wherein, the frequency of occurrence of historical input information in the first historical input information sequence is less than the frequency of occurrence of historical input information in the second historical input information sequence, the first historical input information sequence is used to train the first cache prediction model, and the second historical input information sequence is used to train the second cache prediction model.

8. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 7.

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