Resistive random access memory architecture

By setting transistors and level converters outside the RRAM, the problems of large area occupied by the gate tube and high voltage power consumption are solved, and a high-density and low-cost memory design is achieved.

CN120748463APending Publication Date: 2025-10-03INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
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Patent Information

Application Number
CN202510242418.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-03-03
Publication Date
2025-10-03

AI Technical Summary

Technical Problem

In existing RRAM memories, the gate transistors occupy a large area and require high voltage, resulting in large chip area and high power consumption.

Method used

The bit line transistor and source line transistor are set outside the resistive memory to replace the internal selection tube, and the initial control voltage signal is converted by using a level converter to reduce the voltage input to reduce the unit area and power consumption.

Benefits of technology

The storage density is improved, the unit area and storage cost are reduced, the power consumption is reduced, and the stability of the memory is guaranteed.

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Abstract

The invention provides a resistive random access memory architecture which can be applied to the technical field of circuits. The architecture includes: a resistive random access memory; the address decoder is used for converting the received address signal into a control signal; the word line driving module comprises a word line and a word line driver, and the word line driver is used for receiving the control signal and adjusting the level state of the word line based on the control signal so as to control the resistive random access memory to be in a conducting state; the control module comprises a level translator which is used for performing level conversion on the off-chip initial control voltage signal to obtain a target control voltage signal; the bit line transistor is used for controlling a bit line of the control module to be in a conducting state according to the target control voltage signal; the source line transistor is used for controlling a source line of the control module to be in a conducting state according to the target control voltage signal; the resistive random access memory in the on state adjusts a resistance state in response to the source line and bit line level signals, and executes a data write instruction based on the resistance state.
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