Etching method and semiconductor process equipment

Abstract

The invention provides an etching method and semiconductor process equipment, relates to the technical field of semiconductors, and is designed for solving the problem that a necking phenomenon is easy to form at the top position of an etching material layer in a metal hard mask etching process. The etching method comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises an etching material layer, a metal hard mask layer, an oxide layer, an anti-reflection layer and a graphical photoresist layer which are stacked in sequence; a first etching step: etching the anti-reflection layer by taking the photoresist layer as a mask, and exposing the oxide layer; in the deposition step, a first carbon-containing sacrificial layer is formed on the top of the anti-reflection layer, a second carbon-containing sacrificial layer is formed on the top of the oxide layer, and the thickness of the first carbon-containing sacrificial layer is larger than that of the second carbon-containing sacrificial layer. According to the invention, the thickness residual amount of the anti-reflection layer can be improved, so that the anti-reflection layer can still remain in the subsequent etching step, and the phenomenon of necking caused by the fact that the fillet morphology of the anti-reflection layer is transmitted to the etching material layer is prevented.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an etching method and semiconductor process equipment. Background Art

[0002] As chip integration increases, the critical dimensions of semiconductor devices are becoming smaller and smaller, and the patterns are becoming denser, which in turn places increasing demands on the accuracy of pattern transfer. To improve the accuracy of pattern transfer, related technologies use a metal hard mask with a relatively high etching selectivity to transfer the pattern to the etching material layer. Specifically, a metal hard mask, an oxide layer, an anti-reflective layer, and a photoresist layer are sequentially arranged on the etching material layer. First, the anti-reflective layer and the oxide layer are etched downward using the photoresist layer as a mask, transferring the pattern to the metal hard mask. Then, further etching is performed using the metal hard mask as a mask.

[0003] As semiconductor manufacturing processes continue to advance, the precision of pattern transfer continues to increase, often requiring thinner photoresist and anti-reflective layers. Advanced processes, in turn, require thicker and more complex etch material layers, often requiring thicker metal hard masks. This leaves virtually no photoresist or anti-reflective layers left during the metal hard mask etching process. Furthermore, because the photoresist used to form the photoresist layer is relatively soft, its top becomes rounded after plasma bombardment. This morphology, after further transfer through the anti-reflective layer, oxide layer, and metal hard mask, causes a "necking" phenomenon at the top of the etched material layer. Summary of the Invention

[0004] The first object of the present invention is to provide an etching method to solve the technical problem that a "necking" phenomenon is easily formed at the top position of the etching material layer in the metal hard mask etching process.

[0005] The etching method provided by the present invention comprises:

[0006] A semiconductor device is provided, comprising an etching material layer, a metal hard mask layer, an oxide layer, an anti-reflection layer and a patterned photoresist layer stacked in sequence;

[0007] a first etching step, using the photoresist layer as a mask to etch the anti-reflection layer and expose the oxide layer; and

[0008] In a deposition step, a first carbon-containing sacrificial layer is formed on top of the anti-reflection layer, and a second carbon-containing sacrificial layer is formed on top of the oxide layer. The thickness of the first carbon-containing sacrificial layer is greater than that of the second carbon-containing sacrificial layer.

[0009] Furthermore, before the first etching step, the method further includes: a photoresist layer modification step of modifying the photoresist layer to reduce the line width roughness of the photoresist layer.

[0010] Furthermore, the photoresist layer modification step includes: a photoresist layer residual adhesive removal step, removing the protrusions on the sidewalls of the photoresist layer;

[0011] The upper RF power is 100-400W, and the lower RF power is 0. The process gas is a CF type gas, and the flow rate of the CF type gas is between 100-140 sccm.

[0012] Furthermore, the photoresist layer modification step further includes: a photoresist layer curing step of curing the photoresist layer;

[0013] The upper RF power is 700-1200 W, and the lower RF power is 0. The process gas is HBr gas, and the flow rate of the HBr gas is between 130 and 170 sccm.

[0014] Furthermore, in the first etching step, the upper radio frequency power is 500-1500W, and the lower radio frequency power is 30-100W.

[0015] Furthermore, after the deposition step, it includes: a second etching step, etching the second carbon-containing sacrificial layer and the oxide layer using the anti-reflection layer as a mask; wherein the process gas is a mixed gas of CF4 and CHF3, and the ratio of the flow rate of CF4 gas to the flow rate of CHF3 gas is (0.5~5):1.

[0016] Furthermore, after the second etching step, a main etching step is included to etch the metal hard mask layer; wherein the process pressure is 5 to 20 mtorr.

[0017] Furthermore, after the main etching step, an over-etching step is included to partially etch the etching material layer; wherein the dilution gas includes N2 or He.

[0018] Furthermore, after the over-etching step, the method includes: planarizing the upper surface of the oxide layer.

[0019] The beneficial effects brought about by the etching method of the present invention are:

[0020] In this etching method, by adding a deposition step after the anti-reflective layer etching step, the top of the anti-reflective layer is shielded from surrounding areas, while the top of the oxide layer is shielded by the anti-reflective layer. This allows the carbon-containing sacrificial layer to more easily contact the top of the anti-reflective layer during deposition, thereby forming a thicker first carbon-containing sacrificial layer on top of the anti-reflective layer and a second carbon-containing sacrificial layer with a thickness less than the first carbon-containing sacrificial layer on top of the oxide layer. By utilizing the thickness difference of the carbon-containing sacrificial layers formed in these two locations, the remaining thickness of the anti-reflective layer can be increased. In subsequent etching steps, the first carbon-containing sacrificial layer can be used to offset the etching amount, thereby reducing the consumption of the anti-reflective layer. This allows a portion of the anti-reflective layer to remain in the next etching step, preventing the rounded corner morphology of the anti-reflective layer from being transferred to the oxide layer and further to the etched material layer, thereby forming a "necking" phenomenon at the top of the etched material layer.

[0021] The second object of the present invention is to provide a semiconductor process equipment to solve the technical problem that a "necking" phenomenon is easily formed at the top position of the etching material layer in the metal hard mask etching process.

[0022] The semiconductor process equipment provided by the present invention includes a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller. The controller includes at least one processor and at least one memory. The memory stores a computer program. When the computer program is executed by the processor, the above-mentioned etching method is implemented.

[0023] The beneficial effects brought about by the semiconductor process equipment of the present invention are:

[0024] The semiconductor process equipment can implement the above etching method. Accordingly, the semiconductor process equipment has all the advantages of the above etching method, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0026] Figure 1 A cross-sectional view of the structure of a semiconductor device in each step manufactured by an etching method provided in the related art;

[0027] Figure 2 A flowchart of an etching method provided by an embodiment of the present invention;

[0028] Figure 3A structural cross-sectional view of a semiconductor device in each step manufactured by an etching method provided in an embodiment of the present invention;

[0029] Figure 4 A flow chart of another etching method provided by an embodiment of the present invention;

[0030] Figure 5 A graph showing the relationship between the upper RF power and the remaining thickness of the anti-reflection layer in the first etching step of the etching method provided by an embodiment of the present invention;

[0031] Figure 6 A graph showing the relationship between the lower RF power and the remaining thickness of the anti-reflection layer in the first etching step of the etching method provided by an embodiment of the present invention;

[0032] Figure 7 A graph showing the relationship between the CF4 / CHF3 ratio and the remaining thickness of the anti-reflection layer in the second etching step of the etching method provided in an embodiment of the present invention;

[0033] Figure 8 A schematic structural diagram of semiconductor process equipment provided by an embodiment of the present invention.

[0034] Description of reference numerals:

[0035] 101'-photoresist layer; 102'-antireflection layer; 103'-oxide layer; 104'-metal hard mask layer; 105'-etching material layer;

[0036] 101 - photoresist layer; 102 - anti-reflection layer; 103 - oxide layer; 104 - metal hard mask layer; 105 - etching material layer;

[0037] 501-first carbon-containing sacrificial layer; 502-second carbon-containing sacrificial layer;

[0038] 100-plasma; 200-semiconductor process equipment; 20-process chamber; 20A-gas inlet assembly; 20B-upper electrode assembly; 20C-lower electrode assembly; 20D-exhaust assembly;

[0039] 21-RF coil; 22-wafer carrier; 23-upper RF power supply; 24-lower RF power supply; 25-upper matcher; 26-lower matcher. DETAILED DESCRIPTION

[0040] In order to improve the accuracy of pattern transfer, related technologies use a metal hard mask with relatively high etching selectivity to transfer the pattern to the etching material layer. Figure 1 The following is a cross-sectional view of the structure of a semiconductor device manufactured according to the etching method provided in the related art in each step. The specific steps are as follows:

[0041] The morphology before etching is shown in (a). After the photoresist layer 101 ′ undergoes photolithography processes such as development and fixing, a line pattern is formed with a horizontal top and vertical sidewalls.

[0042] Using photoresist layer 101' as a mask, the pattern is transferred to anti-reflective layer 102'. Because the photoresist used to form photoresist layer 101' is relatively soft, its top corners become rounded after plasma bombardment. Furthermore, due to the need for line width control, a certain amount of overetching is required before the oxide layer 103' is reached to meet the required line width. At this point, photoresist layer 101' is completely consumed, and the rounded top corners are transferred to anti-reflective layer 102', as shown in (b).

[0043] Using the anti-reflection layer 102' as a mask, the oxide layer 103' is etched downwards. Since this step does not have a high etching selectivity for the anti-reflection layer 102', the anti-reflection layer 102' will also be lost to a certain extent. The morphology of the semiconductor device after etching is shown in (c).

[0044] Using the anti-reflective layer 102' as a mask, the metal hard mask layer 104' is etched downward. Because the anti-reflective layer 102' has a rounded top corner inherited from the photoresist layer 101', the edges of the anti-reflective layer 102' are completely etched first, leaving some in the center. As the etching process progresses, the oxide layer 103' becomes rounded at the edges and flattened in the center, forming a "shoulder" morphology. This morphology also creates a sloped morphology on the sidewalls of the metal hard mask layer 104', as shown in (d).

[0045] Over-etching is performed to ensure that the metal hard mask layer 104' is completely opened. At this time, the etching material layer 105' is consumed to a certain extent, as shown in (e).

[0046] The etching material layer 105' is etched. In this step, the tilted morphology of the metal hard mask layer 104' is transferred to the etching material layer 105', thereby forming a "necking" phenomenon at the top of the etching material layer 105', which seriously affects the sidewall morphology of the etching material layer 105'.

[0047] Therefore, the purpose of the present invention is to provide an etching method and semiconductor process equipment to solve the technical problem that a "necking" phenomenon is easily formed at the top position of the etching material layer during the metal hard mask etching process.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the following detailed description of the specific embodiments of the present invention is given in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0049] Figure 2 Flowchart of the etching method provided in this embodiment. Figure 2 As shown, this embodiment provides an etching method, including:

[0050] Step S100: Provide a semiconductor device. Figure 3 As shown in (a) , the semiconductor device includes an etching material layer 105 , a metal hard mask layer 104 , an oxide layer 103 , an anti-reflection layer 102 and a patterned photoresist layer 101 , which are sequentially stacked.

[0051] In the above-mentioned semiconductor device, the metal hard mask layer 104 is located on top of the etching material layer 105 and is used to prevent the pattern on the photoresist layer 101 from being destroyed due to pattern miniaturization. It can be formed by chemical vapor deposition or spin coating, and the material can be inorganic thin film materials such as TiN (titanium nitride), SiN (silicon nitride) and SiO2 (silicon dioxide); the oxide layer 103 is located on top of the metal hard mask layer 104 and is used to prevent short circuits and the flow of current between circuits to improve the stability and performance of the device, and the material can be SiO2; the anti-reflection layer 102 is located on top of the oxide layer 103 and is used to reduce light reflection occurring during the photolithography process, suppress interference between incident light and reflected light to generate standing waves, and improve light transmission efficiency; the photoresist layer 101 is located on top of the anti-reflection layer 102, and is formed into a line pattern from a relatively soft photoresist through photolithography processes such as development and fixing, with its top being horizontal and the sidewalls being vertical.

[0052] Step S300: First etching step, such as Figure 3 As shown in (b), the anti-reflection layer 102 is etched using the photoresist layer 101 as a mask to expose the oxide layer 103.

[0053] In this step, the upper surface of the oxide layer 103 serves as the etching stop surface. Typically, when the vertical etching contacts the oxide layer 103, the vertical etching stops, and only the horizontal etching is performed to increase the window spacing size (B1). However, in order to meet the line width requirements and over-etching requirements, etching will continue for a certain period of time after the vertical etching stops. This step is a key step in controlling B1 and the remaining thickness of the anti-reflection layer 102. By increasing the etching time or increasing the amount of etching gas introduced, B1 can be effectively increased, but the remaining thickness of the anti-reflection layer 102 will be reduced, resulting in an insufficient thickness of the anti-reflection layer 102.

[0054] Specifically, in the first etching step, the upper RF power may be 500-1500W.

[0055] By increasing the upper RF power, the lateral etching degree can be enhanced, the sidewall consumption can be increased, and the window spacing size B1 of the anti-reflection layer 102 can be increased, such as Figure 5As shown, as the upper radio frequency power increases (the horizontal axis in the figure is from left to right), the window spacing size B1 of the anti-reflection layer 102 increases linearly.

[0056] As the lateral etching degree increases, the longitudinal consumption of the anti-reflection layer 102 will be reduced accordingly, thereby increasing the thickness of the anti-reflection layer 102. However, when the upper RF power increases to a certain level, due to the existence of the rounded corner morphology of the anti-reflection layer 102, the thickness of the anti-reflection layer 102 is not sensitive to the change of the upper RF, which is reflected in the Figure 5 The variation curve of the remaining thickness of the middle anti-reflection layer 102 is: firstly it increases linearly, and after increasing to a certain value, it fluctuates around the value.

[0057] Specifically, when the lateral etching increases, the lateral dimension B2 of the anti-reflection layer 102 decreases. Due to the rounded corners of the anti-reflection layer 102, the lateral etching at the top of the anti-reflection layer 102 consumes the thickness of the anti-reflection layer 102. From the above analysis, it can be seen that the increase in the degree of lateral etching leads to the reduction of the longitudinal etching, which in turn leads to the reduction of the longitudinal consumption of the anti-reflection layer 102. As a result, the increase in the thickness of the anti-reflection layer 102 due to the reduction in the longitudinal etching and the decrease in the thickness of the anti-reflection layer 102 due to the increase in the lateral etching can offset each other, resulting in the phenomenon that the remaining thickness of the anti-reflection layer 102 is insensitive after the upper RF power increases to a certain level.

[0058] In addition, in the first etching step, the lower RF power may also be set to 30-100W.

[0059] By reducing the lower RF power, the plasma bombardment on the anti-reflection layer 102 can be weakened, thereby reducing the consumption of the photoresist layer 101 and the anti-reflection layer 102. At the same time, the etching environment of the process chamber is made cleaner, and the polymer accumulation on the sidewalls and bottom of the photoresist layer 101 and the anti-reflection layer 102 is reduced, thereby reducing the protection of the sidewalls and increasing the window spacing size B1. Figure 6 As shown, as the upper RF power decreases (the horizontal axis in the figure is from right to left), the remaining thickness of the anti-reflection layer 102 and the window spacing size B1 both increase.

[0060] Step S500: Deposition step, such as Figure 3 As shown in (c), a first carbon-containing sacrificial layer 501 is formed on the top of the anti-reflection layer 102, and a second carbon-containing sacrificial layer 502 is formed on the top of the oxide layer 103, wherein the thickness of the first carbon-containing sacrificial layer 501 is greater than the thickness of the second carbon-containing sacrificial layer 502.

[0061] By adding a deposition step after the etching step of the anti-reflection layer 102, since there is no shielding around the top of the anti-reflection layer 102, and the top of the oxide layer 103 is shielded by the anti-reflection layer 102, the carbon-containing sacrificial layer can more easily contact the top of the anti-reflection layer 102 during the deposition process, so as to form a thicker first carbon-containing sacrificial layer 501 on the top of the anti-reflection layer 102, and form a second carbon-containing sacrificial layer 502 with a thickness less than the first carbon-containing sacrificial layer 501 on the top of the oxide layer 103. By utilizing the thickness difference of the carbon-containing sacrificial layers formed in the above-mentioned two locations, the remaining thickness of the location where the anti-reflection layer 102 is located can be increased, so that in the subsequent etching step, the etching amount can be offset by the above-mentioned first carbon-containing sacrificial layer 501 to reduce the consumption of the anti-reflection layer 102, so that in the etching step of the next stage, there can still be some remaining anti-reflection layer 102 to prevent the rounded corner morphology of the anti-reflection layer 102 from being transferred to the oxide layer 103 and further transferred to the etching material layer 105, thereby forming a "necking" phenomenon at the top position of the etching material layer 105.

[0062] It should be noted that, in this embodiment, the thickness direction can refer to Figure 3 As shown by the corresponding arrows in (a), the thickness of the device structure represents the size in the thickness direction.

[0063] In this embodiment, the thickness of the first carbon-containing sacrificial layer 501 is 3 to 5 times the thickness of the second carbon-containing sacrificial layer 502 .

[0064] By limiting the thickness of the first carbon-containing sacrificial layer 501 and the second carbon-containing sacrificial layer 502 to the above range, the first carbon-containing sacrificial layer 501 has a sufficient thickness to reduce the weakening effect of the subsequent etching process.

[0065] Figure 4 This is a flow chart of another etching method provided in this embodiment. Figure 4 As shown, before the first etching step, step S200 is further included: a photoresist layer 101 modification step, in which the photoresist layer 101 is modified to reduce the line width roughness of the photoresist layer 101 .

[0066] After photolithography, the sidewall boundaries of the photoresist layer 101 are not completely smooth, but typically have an uneven or rough appearance. During the etching process, the pattern of the photoresist layer 101 is transferred layer by layer, and this rough appearance is gradually amplified, making the sidewall boundaries even more uneven. In this step S200, by modifying the photoresist layer 101, the line width roughness of the photoresist layer 101 can be reduced, making the sidewalls of the photoresist layer 101 smoother, thereby reducing the adverse effects of the etching process on the pattern transfer accuracy.

[0067] The above-mentioned photoresist layer 101 modification step may include: a residual adhesive removal step of the photoresist layer 101, removing the protrusions on the sidewall of the photoresist layer 101; wherein the upper RF power is 100-400W and the lower RF power is 0; the process gas is a CF-type gas, and the flow rate of the CF-type gas is between 100 and 140 sccm.

[0068] In this step, only the upper RF is used without the lower RF, which can prevent the plasma from bombarding the photoresist layer 101 and causing its deformation, thereby reducing the impact on the sidewalls of the photoresist layer 101. At the same time, the use of CF-type gas can etch the protrusions on the sidewalls of the photoresist layer 101, passivating or smoothing the sharper protrusions to achieve a smoothing effect, thereby reducing the line width roughness of the photoresist layer 101.

[0069] In addition, by limiting the upper RF power to the above range, on the one hand, it is possible to avoid insufficient dissociation of the etching gas due to too low an upper RF power, which leads to inadequate etching of the raised portion of the sidewall of the photoresist layer 101; on the other hand, it is possible to avoid excessive dissociation due to too high an upper RF power, which leads to excessive etching of the photoresist layer 101 and increases in the sidewall spacing B3 (refer to FIG. Figure 3 (a)) and reducing the thickness of the photoresist layer 101.

[0070] Specifically, in the step of removing the residual adhesive from the photoresist layer 101 , the upper RF power may be 300W.

[0071] The above-mentioned photoresist layer 101 modification step may further include: a photoresist layer 101 curing step, curing the photoresist layer 101; wherein the upper RF power is 700-1200W and the lower RF power is 0; the process gas is HBr (hydrogen bromide) gas, and the flow rate of the HBr gas is between 130-170sccm.

[0072] In this step, HBr gas is used to generate vacuum ultraviolet (VUV) light in the process chamber, inducing polymer chain rearrangement and chemically reacting with the photoresist layer 101 to modify it, smoothing the edge morphology, forming a dense and hard cross-linked layer, and curing the surface, thereby improving the etching resistance of the photoresist layer 101. This makes it easier to maintain the original appearance during the etching process and reduce deformation. Using only the upper RF and not the lower RF can prevent excessive damage to the photoresist layer 101. Furthermore, by keeping the upper RF power within a relatively high range, HBr can be dissociated more, allowing for sufficient contact with the photoresist layer 101 and enhancing the curing effect.

[0073] By limiting the flow rate of HBr gas to the above range, on the one hand, it is possible to avoid weakening the curing effect due to too little HBr gas flow rate, and on the other hand, it is possible to avoid waste due to too much HBr gas flow rate.

[0074] In this embodiment, the CF-based gas used in the above-mentioned residual adhesive removal step of the photoresist layer 101 can be CF4 (carbon tetrafluoride), and its flow rate can be increased from the original 80 sccm to 120 sccm; the HBr gas used in the above-mentioned curing step of the photoresist layer 101 can have a flow rate increased from the original 100 sccm to 150 sccm.

[0075] Increasing the CF gas flow rate in the residual adhesive removal step of the photoresist layer 101 and increasing the HBr gas flow rate in the curing step of the photoresist layer 101 can also help stabilize the ignition and prevent extinguishing.

[0076] Please continue to refer to Figure 4 In this embodiment, after the deposition step, step S600 can be included: a second etching step, etching the second carbon-containing sacrificial layer 502 and the oxide layer 103 using the anti-reflection layer 102 as a mask; wherein the process gas is a mixed gas of CF4 and CHF3 (trifluoromethane), and the ratio of the flow rate of CF4 gas to the flow rate of CHF3 gas is (0.5~5):1.

[0077] In this step, the material of the oxide layer 103 to be etched is usually OX (oxide), SiN (silicon nitride) and SiON (silicon oxynitride). Generally, the oxide layer 103 is thin and the etching time is short. However, in this embodiment, since the second carbon-containing sacrificial layer 502 is formed on the top of the oxide layer 103 in step S500, it takes a long time to first open the second carbon-containing sacrificial layer 502 and then etch the oxide layer 103 below. The device structure after etching is as follows: Figure 3 As shown in (d) in .

[0078] By increasing the proportion of CHF3 gas within a certain range, the C / F ratio is increased, thereby introducing more C into the process chamber, thereby generating more carbon-containing byproducts that adhere to the surface of the anti-reflection layer 102, thereby forming a protective effect on the anti-reflection layer 102 and reducing the consumption of the anti-reflection layer 102 in the subsequent etching process. Figure 7 As shown, when the proportion of CHF 3 gas increases (the horizontal axis in the figure is from right to left), the remaining thickness of the anti-reflection layer 102 increases, and the effect on the side wall angle of the oxide layer 103 is relatively small.

[0079] Specifically, the total flow rate of CF4 gas and CHF3 gas remains unchanged. For example, in the initial stage, the flow rate of CF4 gas is 100 sccm and the flow rate of CHF3 gas is 20 sccm. When the flow rate of CHF3 gas increases to 80 sccm, the flow rate of CF4 gas is reduced to 40 sccm.

[0080] More specifically, in the second etching step, the process pressure can be controlled at 5-20 mtorr, the upper RF power is 300-600 W to generate plasma, and the lower RF power is 20-80 W; the temperature of the electrostatic chuck is 35° C., and the etching time is 20-40 s.

[0081] Please continue to refer to Figure 4 After the second etching step, step S700 may be included: a main etching step, etching the metal hard mask layer 104, wherein the process pressure is 5 to 20 mtorr.

[0082] In this embodiment, the material of the metal hard mask layer 104 is specifically TiN.

[0083] By reducing the process pressure during the etching of the metal hard mask layer 104, the collision effect of the plasma can be reduced, thereby increasing its mean free path, strengthening the plasma bombardment, and enhancing the etching anisotropy. This straightens the sidewalls of the metal hard mask layer 104 during the etching process, making it easier to maintain the window spacing at the bottom when the etched topography of the metal hard mask layer 104 is transferred downward. Therefore, compared with an inclined topography, the vertical topography of the metal hard mask layer 104 is more likely to increase the window spacing at the bottom.

[0084] Specifically, in the main etching step, 50 to 150 sccm of Cl2 (chlorine) is introduced as the etching gas, 10 to 50 sccm of CH4 is introduced to form carbon-containing byproducts on the surface of the anti-reflection layer 102 to protect the anti-reflection layer 102 in this step, and 50 to 200 sccm of N2 (nitrogen) or Ar (argon) is introduced as the carrier gas and dilution gas. At the same time, the process pressure is controlled at 5 to 20 mtorr, the upper RF power is 500 to 1000 W to generate plasma, and the lower RF power is 10 to 50 W. In addition, the temperature of the electrostatic chuck is 35°C, the etching time is 10 to 30 seconds, and the etching is stopped when the etching material layer 105 is exposed.

[0085] Please continue to refer to Figure 4 After the main etching step, the process may include step S800: an over-etching step for partially etching the etching material layer 105, wherein the diluent gas includes N2 or He, and the device structure after etching is as follows: Figure 3 As shown in (e) in .

[0086] This over-etching step can partially etch the etching material layer 105 to ensure that the metal hard mask layer 104 is fully opened. By selecting N2 or He as the dilution gas in the over-etching step, the bombardment effect of the dilution gas can be reduced. Since the over-etching step lasts for a short time, it has almost no impact on the window spacing and only slightly reduces the thickness of the anti-reflection layer 102. As a result, after the over-etching step is completed, there is still anti-reflection layer 102 remaining to protect the sidewall morphology of the oxide layer 103 and the metal hard mask layer 104 from being affected by lateral sputtering, thereby preventing the metal hard mask layer 104 from tilting and causing the etching material layer 105 to "neck" during subsequent etching of the etching material layer 105.

[0087] Specifically, during the overetch step, 10 to 50 sccm of Cl₂ is introduced as the etching gas, and 50 to 150 sccm of N₂ or Ar is introduced as the carrier gas and dilution gas. Simultaneously, the process pressure is controlled between 5 and 15 mtorr, the upper RF power is between 500 and 1000 W to generate plasma, and the lower RF power is between 10 and 40 W. Furthermore, the electrostatic chuck temperature is maintained at 35°C, and the etching time is between 5 and 15 seconds.

[0088] Please continue to refer to Figure 4 In this embodiment, after the over-etching step, step S900 may be included: planarizing the upper surface of the oxide layer 103 .

[0089] By planarizing the upper surface of the oxide layer 103 , residues attached to the upper surface of the oxide layer 103 can be removed, thereby ensuring the cleanliness of the upper surface of the oxide layer 103 and preventing the residues from adversely affecting subsequent processes.

[0090] In this embodiment, after step S800, the anti-reflection layer 102 still remains on the upper surface of the oxide layer 103. Figure 3 As shown in (e), this part of the anti-reflection layer 102 can be removed by a dry etching process. Specifically, in step S900, 100 to 200 sccm of O2 (oxygen) is introduced as an etching gas, and 10 to 40 sccm of N2 is introduced as a protective gas. At the same time, the process pressure is controlled at 5 to 15 mtorr, the upper RF power is 800 to 1300 W to generate plasma, and the lower RF power is 0 to prevent the plasma from bombarding the bottom of the window. In addition, the temperature of the electrostatic chuck is 45°C, the etching time is 40 to 60s, and the etching is stopped when the oxide layer 103 is over-etched by 50% to ensure that the residue on the upper surface of the oxide layer 103 is completely removed. The device structure after etching is as shown in FIG. Figure 3 As shown in (f), at this time, the upper surface of the oxide layer 103 is flat, and the verticality between the sidewalls of the oxide layer 103 and the metal hard mask layer 104 is good.

[0091] Figure 8 FIG. 2 is a schematic structural diagram of a semiconductor process equipment 200 provided in an embodiment of the present invention. Figure 8 As shown, this embodiment also provides a semiconductor process equipment 200, including a process chamber 20, an air inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C and a controller, wherein the controller includes at least one processor and at least one memory, and a computer program is stored in the memory, and the computer program implements the above-mentioned etching method when executed by the processor.

[0092] The semiconductor process equipment 200 can implement the above etching method. Accordingly, the semiconductor process equipment 200 has all the advantages of the above etching method, which will not be described in detail here.

[0093] For example, the controller can be either a host computer or a slave computer. Specifically, the controller can control the opening of the valve of the gas inlet assembly 20A to introduce the corresponding process gas into the process chamber 20. The controller can also control the opening and closing of the valve of the gas inlet assembly 20A to control the flow rate of the process gas. The controller can also control the exhaust assembly 20D to exhaust the interior of the process chamber 20, for example, by controlling the valve opening of the exhaust assembly 20D or the speed of the exhaust pump, thereby controlling the pressure inside the process chamber 20 and exhausting reaction byproducts.

[0094] The upper electrode assembly 20B may include an RF coil 21, an upper RF power supply 23, and an upper matcher 25. The controller is further configured to control the upper RF power supply 23 to provide upper RF power to the RF coil 21 via the upper matcher 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma 100.

[0095] The lower electrode assembly 20C may include a wafer carrier 22, a lower RF power supply 24, and a lower matcher 26. The controller is further configured to control the lower RF power supply 24 to provide lower RF power to the wafer carrier 22 via the lower matcher 26 to provide an RF bias. The wafer carrier 22 may be an electrostatic chuck, a mechanical chuck, or a vacuum chuck.

[0096] The semiconductor process equipment 200 in the embodiment of the present application may be an inductively coupled plasma device or a capacitively coupled plasma device. The embodiment of the present application does not limit the type of the semiconductor process equipment 200.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

[0098] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0099] In the above embodiments, the descriptions of directions such as “upper”, “lower”, “left”, “right”, and “side” are all based on the drawings.

[0100] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An etching method, characterized in that: include: A semiconductor device is provided, comprising an etching material layer (105), a metal hard mask layer (104), an oxide layer (103), an anti-reflection layer (102), and a patterned photoresist layer (101) which are stacked in sequence; A first etching step is to etch the anti-reflection layer (102) using the photoresist layer (101) as a mask to expose the oxide layer (103); and In a deposition step, a first carbon-containing sacrificial layer (501) is formed on top of the anti-reflection layer (102), and a second carbon-containing sacrificial layer (502) is formed on top of the oxide layer (103), wherein the thickness of the first carbon-containing sacrificial layer (501) is greater than the thickness of the second carbon-containing sacrificial layer (502).

2. The etching method according to claim 1, wherein: Before the first etching step, the method further includes: a photoresist layer (101) modification step, in which the photoresist layer (101) is modified to reduce the line width roughness of the photoresist layer (101).

3. The etching method according to claim 2, wherein: The photoresist layer (101) modification step includes: a photoresist layer (101) residual adhesive removal step, removing the protruding portion of the side wall of the photoresist layer (101); The upper RF power is 100-400W, and the lower RF power is 0. The process gas is a CF type gas, and the flow rate of the CF type gas is between 100-140 sccm.

4. The etching method according to claim 2, wherein: The photoresist layer (101) modification step further includes: a photoresist layer (101) curing step, curing the photoresist layer (101); The upper RF power is 700-1200 W, and the lower RF power is 0. The process gas is HBr gas, and the flow rate of the HBr gas is between 130 and 170 sccm.

5. The etching method according to claim 1, wherein: In the first etching step, the upper radio frequency power is 500-1500W, and the lower radio frequency power is 30-100W.

6. The etching method according to claim 1, wherein: After the deposition step, the method further comprises: In a second etching step, the second carbon-containing sacrificial layer (502) and the oxide layer (103) are etched using the anti-reflection layer (102) as a mask; wherein the process gas is a mixed gas of CF4 and CHF3, and the ratio of the flow rate of the CF4 gas to the flow rate of the CHF3 gas is (0.5-5):

1.

7. The etching method according to claim 6, characterized in that: After the second etching step, a main etching step is performed to etch the metal hard mask layer (104); wherein the process pressure is 5 to 20 mtorr.

8. The etching method according to claim 7, characterized in that: After the main etching step, an over-etching step is included to partially etch the etching material layer (105); wherein the dilution gas includes N2 or He.

9. The etching method according to claim 8, characterized in that: After the over-etching step, the method includes: planarizing the upper surface of the oxide layer (103).

10. A semiconductor process equipment comprising a process chamber (20), an air inlet assembly (20A), an upper electrode assembly (20B), a lower electrode assembly (20C) and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the etching method according to any one of claims 1 to 9 is implemented.

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