Deep silicon etching method and semiconductor process equipment

Abstract

The invention provides a deep silicon etching method and semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first circulation step and a second circulation step, and each of the first circulation step and the second circulation step comprises an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products and a deposition step for forming a protective layer on the side wall of the groove, protective gas adopted in the deposition step of the second circulation step comprises oxygen-containing gas, and the lower electrode power of the deposition step of the second circulation step is larger than that of the deposition step of the first circulation step. According to the deep silicon etching method, the etching rates of different areas of the isolation groove can be balanced, the deep micro-load effect is optimized, and the depth consistency of the isolation groove is improved; and meanwhile, the mask layer is not consumed in the deposition step, so that the consumption of the mask layer is reduced, the effective height of the mask layer is ensured, the morphology precision of the formed isolation groove and AA is improved, and the electrical property and yield of the product are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a deep silicon etching method and semiconductor process equipment. Background Art

[0002] With the rapid development of technology, dynamic random access memory (DRAM), a crucial container for data storage and exchange, faces increasingly stringent performance requirements. To ensure stable electrical performance and yield, the active array (AA), a key structure in the DRAM storage array area, requires isolation trenches between active areas (AA) to be at least 200nm deep. Within the active array, the isolation trenches exhibit pattern density differences. Deep silicon etching (DSE) can create a deep micro-loading effect, leading to inconsistent trench depths. This impacts the topography accuracy of the isolation trenches and AA, and consequently, the product's electrical performance and yield.

[0003] In related technologies, the deep micro-load effect is generally reduced by increasing the duty cycle of the lower electrode power in the etching step. However, this operation will also increase the etching loss of the mask layer in the etching step, resulting in insufficient effective height of the mask layer end, which in turn causes the AA to suffer from head clipping, and even severe line breakage defects, which still cannot guarantee the electrical performance and yield of the product.

[0004] Therefore, how to simultaneously reduce the deep micro-loading effect and ensure the effective height of the mask layer to improve the electrical properties and yield of the product is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of the present invention is to provide a deep silicon etching method and semiconductor process equipment to solve the technical problem in the related art that it is impossible to simultaneously reduce the micro-load effect of the isolation trench depth and ensure the effective height of the mask layer, thereby affecting the electrical properties and yield of the product.

[0006] To solve the above problems, the present invention provides a deep silicon etching method, comprising a first cycle step and a second cycle step, wherein the first cycle step and the second cycle step both include an etching step for etching a groove in a silicon substrate, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove, wherein the protective gas used in the deposition step of the second cycle step includes an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than the lower electrode power of the deposition step of the first cycle step.

[0007] Optionally, the power of the lower electrode in the deposition step of the first cycle step is 0, and the power of the lower electrode in the deposition step of the second cycle step is 10-80W.

[0008] Optionally, the power of the lower electrode in the deposition step of the second cycle step is 30-60W.

[0009] Optionally, the flow rate of the oxygen-containing gas in the deposition step of the second cycle step is 200-300 sccm.

[0010] Optionally, in the second cycle step, the etching step, the removal step and the deposition step are performed sequentially.

[0011] Optionally, in the first cycle step, the etching step, the deposition step and the removal step are performed in sequence, wherein the process gas of the removal step contains a carbon-fluorine gas.

[0012] Optionally, the number of cycles of the first cycle step is 2 to 4 times.

[0013] Optionally, the number of cycles of the second cycle step is 11 to 15 times.

[0014] Optionally, before executing the first cycle step, a pre-removal step is first executed, wherein the pre-removal step is used to remove the oxide layer on the surface of the silicon substrate.

[0015] The present invention also provides a semiconductor process equipment, comprising: a process chamber, a supporting base, an upper radio frequency power supply, a lower radio frequency power supply and a controller, wherein:

[0016] The carrying base is used to carry the silicon substrate;

[0017] The upper RF power supply is used to apply upper electrode power to the process chamber;

[0018] The lower RF power supply is used to load the lower electrode power to the supporting base;

[0019] The controller includes a memory and a processor. The memory stores computer instructions. The processor executes the computer instructions to perform the deep silicon etching method.

[0020] In the deep silicon etching method provided by the present invention, a deposition step of a second cycle step is set to use an oxygen-containing gas as a protective gas, and the lower electrode power applied in the deposition step of the second cycle step is greater than the lower electrode power in the deposition step of the first cycle step. When the deposition step of the second cycle step is executed, its lower electrode power can draw more oxygen-containing gas into the lower trench section, thereby enhancing the oxidation deposition micro-load effect of the oxygen-containing gas on the silicon sidewalls and silicon bottom walls of the lower trench section, so that a thicker protective layer is deposited on the trench sidewalls and bottom walls of the first region with a larger CD of the isolation trench, correspondingly slowing down the etching rate of the first region in the etching step of the second cycle step. In the first region and the second region of the lower trench section, the deposition rate of the deposition step corresponds to the etching rate of the etching step, thereby balancing the overall etching rate of the lower trench section, optimizing the depth micro-load effect, and improving the depth consistency of the isolation trench.

[0021] At the same time, the deposition step of the second cycle uses oxygen-containing gas as a protective gas. The oxygen-containing gas forms a protective layer by oxidizing the silicon sidewalls and the silicon bottom wall. The application of the lower electrode power will not increase the consumption of the mask layer in the deposition step, thereby reducing the micro-load of the isolation trench depth and improving the consistency of the isolation trench depth. At the same time, it reduces the consumption of the mask layer and ensures the effective height of the mask layer, thereby improving the morphological accuracy of the isolation trench and AA, reducing the defects of AA head cutting or even broken wires, and improving the electrical properties and yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 Target etch topography for the active array in DRAM;

[0024] Figure 2a This is an etching morphology image of the isolation trench along the direction perpendicular to AA obtained according to the first deep silicon etching method provided in the related art;

[0025] Figure 2b This is an etching morphology image of the isolation trench along the direction parallel to AA obtained according to the first deep silicon etching method provided in the related art;

[0026] Figure 3 The etching morphology of the active array obtained by the second deep silicon etching method provided in the related art, wherein the end of the AA suffers from the head cutting phenomenon;

[0027] Figure 4A schematic flow chart of the first cycle step and the second cycle step in the deep silicon etching method provided in an embodiment of the present invention;

[0028] Figure 5a Deep silicon etching method Figure 4 Under the cycle flow shown, when the number of cycles in the first cycle step and the deposition step in the second cycle step are not optimized, an electron microscope image of the etching morphology of the isolation groove along the direction perpendicular to AA is obtained;

[0029] Figure 5b Deep silicon etching method Figure 4 Under the cycle flow shown, when the number of cycles in the first cycle step and the deposition step in the second cycle step are not optimized, an electron microscope image of the etching morphology of the isolation groove along the AA direction is obtained;

[0030] Figure 6a An electron microscope image of the etching morphology of the isolation trench along the direction perpendicular to AA obtained by the first deep silicon etching method provided in an embodiment of the present invention;

[0031] Figure 6b An electron microscope image of the etching morphology of the isolation trench along the direction parallel to AA obtained by the first deep silicon etching method provided by an embodiment of the present invention;

[0032] Figure 7a An electron microscope image of the etching morphology of the isolation trench along the direction perpendicular to AA obtained by the second deep silicon etching method provided in an embodiment of the present invention;

[0033] Figure 7b An electron microscope image of the etching morphology of the isolation trench along the direction parallel to AA obtained by the second deep silicon etching method provided in an embodiment of the present invention;

[0034] Figure 8 A schematic diagram of semiconductor process equipment provided by an embodiment of the present invention.

[0035] Description of reference numerals:

[0036] 10 - mask layer; 11 - opening; 20 - silicon substrate; 21 - isolation trench; 211 - upper trench segment; 212 - lower trench segment; 213 - first region; 214 - second region; 215 - deep microload; 22 - active region; 221 - end; 222 - middle;

[0037] 110 - process chamber; 120 - supporting base; 130 - upper RF power supply; 140 - upper matching element; 150 - RF coil; 160 - dielectric window; 170 - lower matching element; 180 - lower RF power supply. DETAILED DESCRIPTION

[0038] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0041] Figure 1 This is the target etching morphology of the active array in DRAM. Figure 1 As shown, multiple active areas 22 (AA) in the active array are arranged in a collinear or parallel manner. The region of the isolation trench 21 located between two adjacent AAs along a direction parallel to the AA is a first region 213, and the region located between two adjacent AAs along a direction perpendicular to the AA is a second region 214. The critical dimensions (CD) of the first region 213 are greater than those of the second region 214. Ideally, the two ends 221 along the length direction of the AA are arc-shaped, and the depths of the first region 213 and the second region 214 of the isolation trench 21 are consistent.

[0042] Figure 2a This is an etching morphology diagram of the isolation trench 21 obtained along the direction perpendicular to AA by the first deep silicon etching method provided in the related art. Figure 2b This is an etching morphology diagram of the isolation trench 21 obtained along the direction parallel to AA by the first deep silicon etching method provided in the related art. Figure 3This is an etching morphology image of the active array obtained by the second deep silicon etching method provided in the related art, wherein the end portion 221 of AA suffers from the head truncation phenomenon.

[0043] In the related art of etching the silicon substrate 20 to form the isolation trench 21, since the CD of the first region 213 of the isolation trench 21 is greater than the CD of the second region 214, there is a pattern density difference between different regions of the isolation trench 21. During the process of etching the isolation trench 21 using the first deep silicon etching method, the etching rate of the first region 213 is greater than the etching rate of the second region 214, resulting in the formation of deep micro-loads 215 in different regions of the isolation trench 21. Figure 2a and Figure 2b As shown, the depth of the first region 213 of the isolation trench 21 is greater than the depth of the second region 214, thereby affecting the morphological accuracy of the isolation trench 21 and the AA, and affecting the electrical properties and yield of the product. In order to reduce the depth micro-load 215 of the isolation trench 21, the duty cycle of the lower electrode power in the etching step of the second deep silicon etching method is increased compared to the first deep silicon etching method. However, while increasing the plasma etching intensity of the etching step to reduce the depth micro-load 215, the etching intensity of the mask layer 10 is also increased, resulting in increased loss of the mask layer 10 and a reduction in the effective height. In particular, as shown in FIG. Figure 3 As shown, under the action of micro-load caused by the density difference of the pattern of the opening 11 of the mask layer 10, the etching loss of the end 221 corresponding to AA is greater than the etching loss of the middle part 222, which can easily cause the end 221 of AA to suffer from head cutting. In severe cases, even broken wire defects may occur, and the electrical performance and yield of the product cannot be guaranteed.

[0044] This embodiment provides a deep silicon etching method, which divides the etching process into two loop steps. The deposition step (Deposition, Dep) of the second loop step (Loop2) is set to use oxygen-containing gas as a protective gas, and its lower electrode power is greater than the lower electrode power of the deposition step in the first loop step (Loop1). This can balance the etching rates of different areas of the isolation trench 21, optimize the depth micro-load effect, and improve the depth consistency of the isolation trench 21. At the same time, oxygen-containing gas is used as a protective gas in the deposition step, and the mask layer 10 is not consumed during the deposition process. Therefore, on the basis of reducing the depth micro-load 215 and improving the depth consistency of the isolation trench 21, the consumption of the mask layer 10 is reduced, the effective height of the mask layer 10 is ensured, and the morphological accuracy of the isolation trench 21 and AA is correspondingly improved, thereby improving the electrical properties and yield of the product. The deep silicon etching method provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] This embodiment provides a deep silicon etching method, including a first cycle step and a second cycle step, both of which include an etching step (Main etch, ME) for etching a groove in a silicon substrate 20, a removal step (Breakthrough, BT) for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove, wherein the protective gas used in the deposition step of the second cycle step includes an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than the lower electrode power of the deposition step of the first cycle step.

[0046] Initially, a mask layer 10, such as a SiO2 mask layer 10, is provided on the top of the silicon substrate 20, and the mask layer 10 is formed with an opening 11 capable of defining the area of ​​the isolation trench 21; during the process, the first cycle step is performed to etch and form the upper trench section 211 of the isolation trench 21. The upper trench section 211 is close to the opening 11 of the mask layer 10, and no lower electrode power is required or a lower lower electrode power is applied. The protective gas in the deposition step can enter the upper trench section 211 more and deposit on its sidewalls and bottom wall to form a protective layer; the upper trench section The CD of the first region 213 of 211 is greater than the CD of the second region 214. Under the micro-load caused by the pattern density difference, the thickness of the protective layer deposited in the first region 213 of the upper trench segment 211 is greater, thereby slowing down the etching rate of the first region 213 in the etching step in the first cycle step. In the first region 213 and the second region 214 of the upper trench segment 211, the deposition rate of the deposition step corresponds to the etching rate of the etching step, thereby balancing the overall etching rate of the upper trench segment 211 and optimizing the deep micro-load effect of the first cycle step.

[0047] The second cycle step performed later is used to etch the lower trench section 212 of the isolation groove 21. The lower trench section 212 has a large depth, and the opening 11CD of the mask layer 10 is small, so it is difficult for the protective gas to enter the lower trench section 212. The deposition step of the second cycle step is set to use oxygen-containing gas as the protective gas, and the lower electrode power applied in the deposition step of the second cycle step is greater than the lower electrode power in the deposition step of the first cycle step. When the deposition step of the second cycle step is executed, its lower electrode power can draw more oxygen-containing gas into the lower trench section 212, thereby The oxidation deposition micro-loading effect of the oxygen-containing gas on the silicon sidewalls and silicon bottom walls of the lower trench section 212 is enhanced, so that a thicker protective layer is deposited on the trench sidewalls and bottom walls of the first region 213 with a larger CD, which correspondingly slows down the etching rate of the first region 213 in the etching step in the second cycle step. In the first region 213 and the second region 214 of the lower trench section 212, the deposition rate of the deposition step corresponds to the etching rate of the etching step, thereby balancing the overall etching rate of the lower trench section 212, optimizing the depth micro-loading effect, and improving the depth consistency of the isolation trench 21.

[0048] At the same time, the deposition step of the second cycle step uses oxygen-containing gas as a protective gas. The oxygen-containing gas forms a protective layer by oxidizing the silicon sidewalls and the silicon bottom wall. The application of the lower electrode power will not increase the consumption of the mask layer 10 in the deposition step, thereby reducing the micro-load 215 of the isolation groove 21 depth and improving the depth consistency of the isolation groove 21. At the same time, the consumption of the mask layer 10 is reduced and the effective height of the mask layer 10 is ensured, thereby improving the morphological accuracy of the isolation groove 21 and AA, reducing the defects of AA head cutting or even broken wires, and improving the electrical properties and yield of the product.

[0049] Specifically, the oxygen-containing gas of the second circulating gas can be O2; the deposition step of the first circulating step can also use an oxygen-containing gas, such as O2, as a protective gas to reduce the consumption of the mask layer 10 in the process and further ensure the effective height of the mask layer 10.

[0050] In the embodiment of the present invention, the lower electrode power during the deposition step of the first cycle is 0, and the lower electrode power during the deposition step of the second cycle is 10-80 W. The upper trench segment 211 is close to the opening 11 of the mask layer 10, and no lower electrode power is applied during the deposition step of the first cycle. This allows a relatively large amount of shielding gas to enter the upper trench segment 211. This effectively alleviates the deep micro-loading effect of the first cycle, improves the operational convenience of the deposition step, and reduces energy consumption. The depth and width of the lower trench section 212 are relatively large. In the deposition step of the second cycle, it is difficult for the oxygen-containing gas to enter the lower trench section 212. By applying a small lower electrode power of 10 to 80 W to it, the oxygen-containing gas can be effectively drawn into the lower trench section 212 without damaging the mask layer 10, thereby enhancing the micro-load effect of the oxidation deposition of the oxygen-containing gas on the silicon sidewalls and silicon bottom walls of the lower trench section 212, and correspondingly balancing the overall etching rate of the lower trench section 212, optimizing the depth micro-load effect, and improving the depth consistency of the isolation trench 21, thereby improving the morphology accuracy of the isolation trench 21 and AA, and improving the electrical properties and yield of the product.

[0051] Specifically, in the embodiment of the present invention, the lower electrode power during the deposition step of the second cycle is 30-60 W. Applying a suitable range of lower electrode power during the deposition step of the second cycle ensures that the lower electrode power has an appropriate effect on the pulling force of the oxygen-containing gas and effectively balances the depth micro-loading effect of the lower trench section 212. This reduces the possibility that a relatively low lower electrode power will weaken the pulling force of the oxygen-containing gas and reduce the degree of optimization of the depth micro-loading effect, resulting in a relatively large depth difference between the first region 213 and the second region 214, or that a relatively high lower electrode power will waste energy.

[0052] In an embodiment of the present invention, the flow rate of the oxygen-containing gas in the deposition step of the second cycle is 200-300 sccm. Specifically, the process recipe of the deposition step of the second cycle can be exemplified as follows: the protective gas includes O2 with a flow rate of 200-300 sccm, the chamber pressure is 10-15 mT, the chamber temperature is 45-60°C, the upper electrode power is 1000-1500 W (13.56 MHz, continuous wave mode), and the lower electrode power is 30-60 W (13.56 MHz, continuous wave mode); the flow rate ratio of the process gas ejected from the nozzle in the chamber to the center, middle, and edge regions of the silicon substrate 20 is approximately 65:20:15, for example, and the process time is 10-13 seconds.

[0053] Figure 4 A schematic flow chart of the first cycle step and the second cycle step in the deep silicon etching method provided in an embodiment of the present invention.

[0054] like Figure 4 As shown, in the embodiment of the present invention, in the first cycle step, an etching step, a deposition step, and a removal step are sequentially performed, wherein the process gas of the removal step contains a carbon-fluorine gas; in the second cycle step, an etching step, a removal step, and a deposition step are sequentially performed. During the process, the etching step etches the silicon substrate 20 in the area of ​​the opening 11, transferring the pattern of the opening 11 of the mask layer 10 to the silicon substrate 20 to form a trench of a certain depth; the deposition step forms a protective layer with good ion bombardment resistance by oxidizing the silicon sidewalls and silicon bottom wall to protect the silicon sidewalls and reduce the erosion of the silicon sidewalls by the etching step. At the same time, the etching step can bombard and remove the protective layer formed on the silicon bottom wall to perform effective longitudinal etching; the removal step can remove the byproducts produced by the etching step to ensure the smooth and effective progress of the etching step.

[0055] The first cycle step is used to etch and form an upper trench section 211 close to the opening 11 of the mask layer 10, wherein the carbon fluorine gas in the removal step of the first cycle step contains a certain amount of carbon element. In the upper trench section 211 with a smaller trench depth, a certain amount of carbon element will remain on the bottom wall and side wall of the trench during the removal step reaction process; the first cycle step is set to cyclically execute the ME step, Dep step and BT step in sequence, and the ME step of the next cycle is immediately followed after the BT step in the previous cycle is completed. Then, the carbon element remaining in the BT step in the previous cycle can form a carbon polymer in the ME step and be deposited on the side wall and bottom wall of the trench, thereby protecting the side wall of the trench.

[0056] As the first cycle step proceeds, the trench depth continues to deepen, and the thickness of the carbon polymer formed on the trench sidewall gradually increases, forming a conical trench with the sidewall inclined from top to bottom toward the central area, wherein the carbon polymer can leave an etching margin for the lateral erosion of the upper trench segment 211 of the isolation trench 21 during the ME step and the BT step etching in the second cycle step, and resist the lateral erosion of the silicon sidewall of the upper trench segment 211 of the isolation trench 21 in the second cycle step; after the first cycle step is completed, the second cycle step is continued: the ME step, the BT step and the Dep step are cyclically executed in sequence, so that the etching can proceed smoothly and the verticality of the silicon sidewall of the lower trench segment 212 is ensured; at the same time, the carbon polymer formed on the upper trench segment 211 of the isolation trench 21 can protect the silicon sidewall of this area, so as to resist the lateral erosion of the silicon sidewall of this area in the second cycle step, further reduce the lateral erosion of the upper trench segment 211 of the isolation trench 21, thereby further improving the morphological accuracy of the isolation trench 21 and AA, and further improving the product yield.

[0057] After the number of cycles of the second cycle step is reached, an etching step is continued to be performed to remove the protection layer formed in the deposition step in the last cycle, thereby obtaining the isolation trench 21 of the target depth.

[0058] Specifically, the etching step in the first cycle can use Cl2 as the main etching gas and be combined with one or more inert auxiliary gases such as Ar, He, and N2, which is beneficial to the uniformity of the entire etching process. At the same time, a small amount of O2 is introduced to protect the sidewalls. The deposition step uses a higher upper electrode power, turns off the lower electrode power, and is equipped with O2 to form a protective layer on the silicon sidewalls to resist subsequent lateral etching. The removal step uses a fluorine-containing gas to promptly remove the Si-Cl byproducts formed after the etching step to prevent the byproducts from continuing to accumulate at the bottom and blocking the etching. In the second cycle, the etching step uses a higher upper electrode power and lower electrode power than the etching step in the first cycle, and NF3 is added to make the etching deeper and straighter. The deposition step turns on the lower electrode power, and the other process recipes are basically the same as the deposition step in the first cycle. The process recipe of the removal step is basically the same as the process recipe of the removal step in the first cycle.

[0059] In an embodiment of the present invention, the number of cycles in the first cycle step is 2 to 4. Setting the number of cycles in the first cycle step to be greater than or equal to 2 ensures the amount of carbon polymer formed in the upper trench segment 211, ensures that the carbon polymer effectively protects the upper trench segment 211 in the first and second cycle steps, and reduces lateral erosion of the silicon sidewalls of the upper trench segment 211 in the first and second cycle steps, thereby ensuring the morphological accuracy of the upper trench segment 211 and the isolation trench 21. Furthermore, setting the number of cycles in the first cycle step to be less than or equal to 4 reduces the direct bombardment of the mask layer 10 by the etching step immediately following the next cycle after the removal step of the previous cycle removes byproducts from the top and sidewalls of the mask layer 10, resulting in significant damage to the mask layer 10. By reducing the number of cycles in the first cycle step, the physical bombardment of the mask layer 10 by the etching step is weakened, thereby ensuring the effective height of the mask layer 10, and correspondingly ensuring the morphological accuracy of the isolation trench 21 and AA formed subsequently, thereby ensuring the electrical performance and yield of the product.

[0060] Specifically, the number of cycles of the first cycle step is taken as 2 for example, and on the basis of ensuring that the carbon polymer formed in the upper trench segment 211 effectively protects it, the consumption of the mask layer 10 in the first cycle step is reduced as much as possible.

[0061] In the embodiment of the present invention, the number of cycles in the second cycle step is 11 to 15. After the number of cycles in the first cycle step is reduced, the number of cycles in the second cycle step is increased accordingly to ensure the depth of the isolation trench 21. In the embodiment of the present invention, the cycle sequence of the second cycle step adopts the ME step, BT step, and Dep step to ensure the verticality of the lower trench section 212 and the isolation trench 21. The removal step of the second cycle step increases the lower RF power and uses oxygen-containing gas as the protective gas, which can effectively optimize the deep micro-loading effect and improve the depth consistency of the lower trench section 212. This effectively ensures the morphological accuracy of the isolation trench 21 and AA, and ensures the electrical performance and yield of the product.

[0062] In the embodiment of the present invention, before executing the first cycle step, a pre-removal step (BT0) is first performed. The pre-removal step is used to remove the oxide layer on the surface of the silicon substrate 20. The surface of the silicon substrate 20 is exposed in the opening 11 area of ​​the mask layer 10. The exposed area of ​​the silicon substrate 20 can be oxidized by contact with the ambient gas to form a natural oxide layer. Before the cycle step is performed, the pre-removal step is first performed to remove the natural oxide layer to ensure smooth etching in the subsequent cycle step.

[0063] Below, in combination with the etching morphology diagram and the specific process recipe, the effects of optimizing the number of cycles in the first cycle step and optimizing the deposition step in the second cycle step in the deep silicon etching method provided by the embodiment of the present invention on increasing the effective height of the mask layer 10 and reducing the depth micro-loading effect of the isolation trench 21 are described in detail.

[0064] Figure 5a Deep silicon etching method Figure 4 In the cycle flow shown, when the number of cycles in the first cycle step and the deposition step in the second cycle step are not optimized, an electron microscope image of the etching morphology of the isolation trench 21 along the direction perpendicular to AA is obtained. Figure 5b Deep silicon etching method Figure 4 In the cycle flow shown, when the number of cycles in the first cycle step and the deposition step in the second cycle step are not optimized, an electron microscope image of the etching morphology of the isolation trench 21 along the direction parallel to AA is obtained.

[0065] Figure 5a and Figure 5b The deep silicon etching method before optimization is obtained. The deep silicon etching method before optimization specifically includes a first cycle step and a second cycle step, wherein the first cycle step sequentially cycles the etching step, the deposition step, and the removal step, and the number of cycles is greater than 4 times; the second cycle step sequentially cycles the etching step, the removal step, and the deposition step, and the lower electrode power of the deposition step is 0, and the number of cycles is 10 to 14 times. Initially, the height of the mask layer 10 is approximately like Figure 5a and Figure 5b As shown, after the first cycle step and the second cycle step, the remaining height of the mask layer 10 is approximately The depth of the first region 213 of the isolation trench 21 is approximately The depth of the second region 214 of the isolation trench 21 is approximately smaller than the depth of the first region 213. That is, the depth of the isolation trench 21 is approximately

[0066] Figure 6a This is an electron microscope image of the etching morphology of the isolation trench 21 along the direction perpendicular to AA obtained by the first deep silicon etching method provided by an embodiment of the present invention. Figure 6b This is an electron microscope image of the etching morphology of the isolation trench 21 along the direction parallel to AA obtained by the first deep silicon etching method provided by an embodiment of the present invention.

[0067] The difference between the first deep silicon etching method provided by the embodiment of the present invention and the deep silicon etching method before optimization is that: the number of cycles of the first cycle step in the first deep silicon etching method provided by the embodiment of the present invention is greater than 2 times and less than 4 times, which is less than the number of cycles of the first cycle step in the deep silicon etching method before optimization; accordingly, the number of cycles of the second cycle step in the first deep silicon etching method provided by the embodiment of the present invention is 11 to 15 times, which is greater than the number of cycles of the second cycle step in the deep silicon etching method before optimization. Figure 6a and 6b As shown, after the number of cycles of the first cycle step is reduced, the remaining height of the mask layer 10 is approximately Compared with the optimization, the depth of the first region 213 of the isolation trench 21 is approximately The depth of the second region 214 of the isolation trench 21 is approximately smaller than the depth of the first region 213. The depth of the isolation trench 21 is approximately As the number of cycles in the second cycle step increases, the deep micro-load 215 formed therein increases.

[0068] In the deep silicon etching method of the embodiment of the present invention, after reducing the number of cycles of the first cycle step compared to before optimization, the loss of the mask layer 10 can be effectively reduced, the effective height of the mask layer 10 can be increased, and the mask layer 10 can ensure the restriction and protection of the morphology transmission of AA and the isolation groove 21, thereby reducing the defects of AA head cutting or even line breakage.

[0069] Figure 7a This is an electron microscope image of the etching morphology of the isolation trench 21 along the direction perpendicular to AA obtained by the second deep silicon etching method provided by an embodiment of the present invention. Figure 7b This is an electron microscope image of the etching morphology of the isolation trench 21 along the direction parallel to AA obtained by the second deep silicon etching method provided by an embodiment of the present invention.

[0070] The second deep silicon etching method provided by the embodiment of the present invention is based on the first deep silicon etching method provided by the embodiment of the present invention, and optimizes the removal step in the second cycle step. The difference is that the lower electrode power of the removal step in the second cycle step of the second deep silicon etching method provided by the embodiment of the present invention is 30 to 60W, and the lower electrode power is improved. Figure 7a and 7b As shown, after applying the lower electrode power to the removal step of the second cycle, the remaining height of the mask layer 10 is approximately The effective height of the mask layer 10 is approximately constant; the depth of the first region 213 of the isolation trench 21 is approximately The depth of the second region 214 of the isolation trench 21 is approximately smaller than the depth of the first region 213. The depth of the isolation trench 21 is approximately It is reduced by nearly half compared with before optimization.

[0071] In the deep silicon etching method of the embodiment of the present invention, the depth micro-load effect of the isolation groove 21 can be reduced by nearly half compared with before optimization, thereby effectively reducing the depth micro-load 215 of the isolation groove 21, improving the depth consistency of the isolation groove 21, improving the morphology accuracy of AA and the isolation groove 21, and improving the electrical properties and yield of the product.

[0072] like Figure 8As shown, this embodiment further provides a semiconductor process apparatus, comprising: a process chamber 110, a supporting pedestal 120, an upper RF power supply 130, a lower RF power supply 180, and a controller. The supporting pedestal 120 is used to support a silicon substrate 20; the upper RF power supply 130 is used to apply upper electrode power to the process chamber 110; and the lower RF power supply 180 is used to apply lower electrode power to the supporting pedestal 120. The controller includes a memory and a processor, wherein the memory stores computer instructions, and the processor executes the computer instructions to perform the above-described deep silicon etching method. This semiconductor process apparatus is capable of performing the above-described deep silicon etching method and possesses all the beneficial effects of the above-described etching method, which will not be further described here.

[0073] Specifically, in the semiconductor processing equipment, a dielectric window 160 is provided above a pedestal 120 in a process chamber 110. A radio frequency coil 150 is provided above the dielectric window 160. An upper matching element 140 is provided between the radio frequency coil 150 and an upper radio frequency power supply 130. The upper radio frequency power supply 130 provides radio frequency power to the radio frequency coil 150 through the upper matching element 140, so that the radio frequency coil 150 excites the process gas inside the process chamber 110 to generate plasma. A lower matching element 170 is provided between the pedestal 120 and a lower radio frequency power supply 180. The lower radio frequency power supply 180 provides radio frequency power to the pedestal 120 through the lower matching element 170 to provide radio frequency bias. The pedestal 120 may be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum chuck.

[0074] The semiconductor process equipment of the embodiment of the present application may be an inductively coupled plasma (ICP) device or a capacitively coupled plasma (CCP) device. The embodiment of the present application does not limit the type of semiconductor process equipment.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A deep silicon etching method, characterized in that: The invention comprises a first cycle step and a second cycle step, wherein the first cycle step and the second cycle step both comprise an etching step for etching a groove in a silicon substrate (20), a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove, wherein the protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than the lower electrode power of the deposition step of the first cycle step.

2. The deep silicon etching method according to claim 1, wherein: The power of the lower electrode in the deposition step of the first cycle step is 0, and the power of the lower electrode in the deposition step of the second cycle step is 10-80W.

3. The deep silicon etching method according to claim 2, wherein: The power of the lower electrode in the deposition step of the second cycle step is 30-60W.

4. The deep silicon etching method according to claim 1, wherein: The flow rate of the oxygen-containing gas in the deposition step of the second cycle step is 200-300 sccm.

5. The deep silicon etching method according to claim 1, wherein: In the second cycle step, the etching step, the removal step and the deposition step are performed in sequence.

6. The deep silicon etching method according to any one of claims 1 to 5, characterized in that: In the first cycle step, the etching step, the deposition step and the removal step are performed in sequence, wherein the process gas of the removal step includes a carbon-fluorine gas.

7. The deep silicon etching method according to claim 6, characterized in that: The number of cycles of the first cycle step is 2 to 4 times.

8. The deep silicon etching method according to claim 6, wherein: The number of cycles in the second cycle step is 11 to 15 times.

9. The deep silicon etching method according to any one of claims 1 to 5, characterized in that: Before executing the first cycle step, a pre-removal step is first executed, wherein the pre-removal step is used to remove the oxide layer on the surface of the silicon substrate (20).

10. A semiconductor process equipment, characterized in that: include: A process chamber (110), a supporting base (120), an upper radio frequency power supply (130), a lower radio frequency power supply (180) and a controller, wherein: The supporting base (120) is used to support the silicon substrate (20); The upper radio frequency power supply (130) is used to apply upper electrode power to the process chamber (110); The lower radio frequency power supply (180) is used to load lower electrode power to the supporting base (120); The controller includes a memory and a processor, wherein the memory stores computer instructions, and the processor executes the deep silicon etching method according to any one of claims 1 to 9 by executing the computer instructions.

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