A package structure and method

Abstract

The application provides a packaging structure and method, and belongs to the technical field of ceramic packaging. The packaging structure comprises a ceramic shell and a ceramic cover plate, and the ceramic shell is connected with the ceramic cover plate. The ceramic shell comprises a plurality of first lead pins, a first ceramic body and a first solder pad. The plurality of first lead pins are arranged on the lower surface of the first ceramic body, and the first solder pad is arranged on the upper surface of the first ceramic body. The ceramic cover plate comprises second lead pins, a second ceramic body, a second solder pad and a solder sheet. The plurality of second lead pins are arranged on the upper surface of the second ceramic body, the second solder pad is arranged on the lower surface of the second ceramic body, and the solder sheet is arranged between the ceramic shell and the ceramic cover plate. The ceramic shell and the ceramic cover plate are welded through the solder sheet. The packaging structure realizes a double-sided electrode ceramic structure and guarantees air tightness, and has the advantages of small product size, short electrical signal transmission path and high reliability.

Description

Technical Field

[0001] This invention relates to the field of ceramic packaging technology, and in particular to a packaging structure and method. Background Technology

[0002] Ceramic packaging technology, as a key solution in the field of electronic packaging, occupies a central position in high-power, high-frequency, and high-reliability applications due to its unique material properties and process advantages. However, traditional ceramic packaging often uses a single-sided electrode lead structure, which is difficult to meet the requirements of high-density interconnection. In multi-layer stacking, the signal transmission path is relatively long, limiting the flexibility and integration density of circuit design. In addition, existing sealing processes have stringent requirements for stress control at the ceramic-metal interface. The difference in thermal expansion coefficients between the metal cover and the ceramic substrate can easily lead to seal cracking, affecting hermeticity and reliability. Summary of the Invention

[0003] The present invention aims to provide a packaging structure and method to achieve a chip packaging structure with high reliability, high flexibility and miniaturization.

[0004] In a first aspect, this application provides a packaging structure, including: a ceramic shell and a ceramic cover plate, wherein the ceramic shell and the ceramic cover plate are connected; the ceramic shell includes a plurality of first pins, a first ceramic body, and a first pad, wherein the plurality of first pins are disposed on the lower surface of the first ceramic body, and the first pad is disposed on the upper surface of the first ceramic body; the ceramic cover plate includes a plurality of second pins, a second ceramic body, a second pad, and a solder sheet, wherein the plurality of second pins are disposed on the upper surface of the second ceramic body, the second pad is disposed on the lower surface of the second ceramic body, and the solder sheet is disposed between the ceramic shell and the ceramic cover plate, wherein the ceramic shell and the ceramic cover plate are welded together by the solder sheet. Optionally, the first ceramic body can be a multilayer ceramic structure, including: a first ceramic layer, a second ceramic layer, and a third ceramic layer, wherein the first ceramic layer serves as a substrate, the second ceramic layer is disposed on the upper surface of the first ceramic layer, and the third ceramic layer is disposed on the upper surface of the second ceramic layer.

[0005] Optionally, the first ceramic body is a multilayer ceramic structure, including: a first ceramic layer, a second ceramic layer and a third ceramic layer, wherein the first ceramic layer serves as a substrate, the second ceramic layer is disposed on the upper surface of the first ceramic layer, and the third ceramic layer is disposed on the upper surface of the second ceramic layer.

[0006] Optionally, the second ceramic body is a double-layer ceramic structure, including a fourth ceramic layer and a fifth ceramic layer, wherein the fifth ceramic layer is disposed on the lower surface of the fourth ceramic layer.

[0007] Optionally, the solder sheet is a double-ring annular solder sheet, comprising an outer annular solder sheet and an inner symmetrical double-arc solder sheet.

[0008] Optionally, the solder sheet is made of AuSn or a tin-silver-copper alloy.

[0009] Optionally, each first pin can be cylindrical / square, and the material can be Kovar alloy. Each first pin is connected to the lower surface of the first ceramic body through silver-copper solder to lead out the signal; each second pin can be cylindrical / square, and the material can be Kovar alloy. Each second pin can be connected to the upper surface of the second ceramic body through silver-copper solder to lead out the signal.

[0010] Optionally, the ceramic shell further includes a first cavity and a second cavity, wherein the first cavity is located inside the second ceramic layer and the second cavity is located inside the third ceramic layer.

[0011] Optionally, the size of the first cavity is larger than the size of the chip; the size of the second cavity is larger than the size of the first cavity, forming a stepped structure with the first cavity.

[0012] Secondly, this application also provides a packaging method, using the packaging structure as described in any one of the first aspects, comprising the following steps:

[0013] High-temperature co-fired ceramic technology is used to punch through holes and print wiring in the first ceramic layer; through holes and a first cavity are punched in the second ceramic layer and wiring is printed; through holes and a second cavity are punched in the third ceramic layer and wiring is printed. Then, the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain a first green ceramic body. The first green ceramic body is then sintered at high temperature to obtain the first ceramic body.

[0014] Using high-temperature co-fired ceramic technology, the fourth ceramic layer is punched with through holes and printed with wiring; the fifth ceramic layer does not require punching or printing of wiring. The fourth and fifth ceramic layers are then stacked and laminated to obtain a second green ceramic body. The second green ceramic body is then sintered at high temperature to obtain the second ceramic body.

[0015] The first ceramic body is electroplated with nickel and gold to obtain a ceramic shell, and the second ceramic body is electroplated with nickel and gold to obtain a ceramic cover plate. Multiple first pins are soldered to the lower surface of the ceramic shell using silver-copper solder, and multiple second pins are soldered to the upper surface of the ceramic cover plate using silver-copper solder.

[0016] Solder sheets are pre-placed on the lower surface of the ceramic cover plate, and the chip is placed on the upper surface of the first ceramic layer;

[0017] Epoxy resin adhesive is injected into the first cavity and the second cavity of the ceramic shell using an automatic dispensing machine;

[0018] The solder sheet on the ceramic cover plate is baked to weld the ceramic shell to the ceramic cover plate, thereby achieving airtight encapsulation.

[0019] Optionally, a plurality of first vias are punched in the first ceramic layer, each first via is filled with metallization paste, and metal traces are printed on the first ceramic layer to form a basic path for signal transmission; a second via and a first cavity are punched in the second ceramic layer, the second via is filled with metallization paste, and metal traces are printed on the second ceramic layer; a third via and a second cavity are punched in the third ceramic layer; the third via is filled with metallization paste, and metal traces are printed on the third ceramic layer.

[0020] Optionally, a ceramic green sheet is selected as the fourth ceramic layer. Based on high-temperature co-fired ceramic technology, a fourth via is punched in the fourth ceramic layer, and metallization paste is filled into the fourth via. At the same time, metal traces and an insulating dielectric covering area are printed on the fourth ceramic layer. The insulating dielectric covering area is used to isolate the subsequent solder sheet from the first and second pads. The fifth ceramic layer does not need to be punched or have traces printed; it only serves as a structural support. The fourth and fifth ceramic layers are stacked and laminated to form a second green ceramic body. A second notch is cut on the side of the second green ceramic body, and its shape matches the first notch for packaging alignment.

[0021] This application provides a packaging structure and method. High-temperature co-fired ceramic technology enables the stacking of multiple ceramic layers and the design of metallized vias and traces, constructing efficient vertical and horizontal signal transmission paths, shortening signal transmission distances, and meeting high-density interconnect requirements. Electroplating the ceramic body with nickel-gold enhances the conductivity and oxidation resistance of the pads. Combined with silver-copper solder to weld Kovar alloy pins, a double-sided electrode structure is formed, enabling bidirectional signal output and improving circuit design flexibility and integration density. Pre-positioning solder pads on the ceramic cover plate and combining it with a baking and soldering process reduces the risk of solder joint cracking due to the difference in thermal expansion coefficients between ceramic and metal, ensuring hermeticity and reliability. The insulating dielectric covering area on the lower surface of the ceramic cover plate isolates the solder pads from the pads, preventing short circuits under high-voltage environments and improving structural safety. Epoxy resin adhesive injected by an automatic dispensing machine covers the chip and bonding wires, forming an internal protective layer to prevent mechanical damage and enhance insulation, improving internal structural stability. Precise mechanical alignment is achieved through feature notches on the sides of the ceramic shell and cover plate, improving packaging accuracy and yield, and ensuring accurate connection between pads and signal transmission holes.

[0022] To make the above-mentioned features and advantages of the invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a packaging structure provided in one embodiment of this application.

[0025] Figure 2 This is a schematic cross-sectional view of an encapsulation structure provided in one embodiment of this application.

[0026] Figure 3 This is a first-view cross-sectional schematic diagram of the ceramic cover plate in the packaging structure provided in one embodiment of this application.

[0027] Figure 4 This is a cross-sectional schematic diagram of the ceramic cover plate in the packaging structure provided in one embodiment of this application from a second perspective.

[0028] Figure 5 This is a flowchart of an encapsulation method provided in one embodiment of this application.

[0029] In the diagram: 1-Ceramic shell, 2-Ceramic cover plate, 3-Chip, 11-First pin, 12-First ceramic body, 121-First ceramic layer, 122-Second ceramic layer, 123-Third ceramic layer, 13-First pad, 14-First notch, 15-Chip mounting area, 16-Bonding wire, 17-First cavity, 18-Second cavity; 21-Second pin, 22-Second ceramic body, 221-Fourth ceramic layer, 222-Fifth ceramic layer, 23-Second pad, 24-Second notch, 25-Solder sheet, 26-Insulating medium covered area. Detailed Implementation

[0030] To make the objectives and technical solutions of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0031] It should be understood that when a component or layer is described as being "on," "connected to," or "coupled to" another component or layer, it may be located directly on, directly connected to, or directly coupled to the other component or layer, or there may be intermediate components or layers. Conversely, when a component is described as being "directly located" on, "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0032] It should be understood that while the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another region, layer, or portion. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the inventive concept.

[0033] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” are used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. It should be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those described in the figures. For example, if the device in the figures is inverted, an element described as “below” or “under” other elements or components would be oriented as “above” other elements or components. Therefore, the exemplary terms “above” or “below” can both include both above and below orientations. Devices can also be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein will be explained accordingly.

[0034] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. Unless otherwise expressly stated herein, the singular forms “a,” “an,” and “this” as used herein are intended to include the plural forms as well. It should be further understood that the terms “comprising” and / or “including” (when used in this specification) specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or inclusion of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0035] Throughout this specification, the phrase "in one embodiment" or "embodiment" means that a specific component, structure, or feature described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, specific components, structures, or features may be combined in any suitable manner in one or more embodiments. It should be understood that the following figures are not drawn to scale and are for illustrative purposes only.

[0036] In one embodiment, see Figure 1 This application provides a packaging structure including a ceramic shell 1 and a ceramic cover plate 2, wherein the ceramic shell 1 and the ceramic cover plate 2 are connected; the ceramic shell 1 includes a plurality of first pins 11, a first ceramic body 12, and a first pad 13, wherein the plurality of first pins 11 are disposed on the lower surface of the first ceramic body 12, and the first pad 13 is disposed on the upper surface of the first ceramic body 12; the ceramic cover plate 2 includes a plurality of second pins 21, a second ceramic body 22, a second pad 23, and a solder sheet 25, wherein the plurality of second pins 21 are disposed on the upper surface of the second ceramic body 22, the second pad 23 is disposed on the lower surface of the second ceramic body 22, and the solder sheet 25 is disposed between the ceramic shell 1 and the ceramic cover plate 2, wherein the ceramic shell 1 and the ceramic cover plate 2 are soldered together through the solder sheet 25 in the ceramic cover plate 2.

[0037] For example, please refer to Figure 2 The present application provides a packaging structure that also includes a chip 3, which is installed inside a ceramic housing 1. The size of the chip 3 is smaller than that of the ceramic housing 1 to accommodate chip installation.

[0038] As an example, each first pin 11 can be cylindrical / square and made of Kovar alloy. Each first pin 11 is connected to the lower surface of the first ceramic body 12 by silver-copper solder and can be used to lead out signals.

[0039] In one example, the ceramic housing 1 may include four first pins 11.

[0040] For example, please refer to Figure 2 The first ceramic body 12 can be a multi-layer ceramic structure, including: a first ceramic layer 121, a second ceramic layer 122 and a third ceramic layer 123. The first ceramic layer 121 serves as a substrate, the second ceramic layer 122 is disposed on the upper surface of the first ceramic layer 121, and the third ceramic layer 123 is disposed on the upper surface of the second ceramic layer 122.

[0041] Optionally, each of the first ceramic layer 121, the second ceramic layer 122, and the third ceramic layer 123 includes multiple vias (not shown), which are filled with metallization paste to form signal transmission holes between the first ceramic layer 121, the second ceramic layer 122, and the third ceramic layer 123. By constructing vertical and horizontal signal transmission paths between the multiple ceramic layers, the circuits of different ceramic layers can achieve effective interconnection of electrical signals, providing a foundation for complex signal transmission within the package structure. By stacking and laminating multiple ceramic layers to form an integrated first ceramic body, the package volume is significantly reduced while improving structural stability.

[0042] As an example, the first pad 13 is made of metallized paste as a base material, which is firmly bonded to the third ceramic layer 123 after high-temperature sintering. The surface of the first pad 13 is also coated with nickel and gold layers through an electroplating process to enhance conductivity and oxidation resistance. As an example, the first pad 13 is located on the upper surface of the third ceramic layer 123, and its structure is closely integrated with the metal traces and vias in the third ceramic layer 123. The vias are filled with metallized paste to form an integrated conductive path, ensuring the continuity of signal transmission in the vertical and horizontal directions in the multilayer ceramic structure. The first pad 13 forms a conductive path with the first pin 11 on the bottom surface of the ceramic shell 1 through the vias of the third ceramic layer 123, the second ceramic layer 122, and the first ceramic layer 121.

[0043] As an example, the ceramic housing 1 also includes a third pad (not shown), which is disposed at the connection between the lower surface of the first ceramic layer 121 and the first pin 11.

[0044] For example, please refer to Figure 1 The ceramic shell 1 also includes a first notch 14, which is integrally formed with the ceramic shell 1 and is disposed on the outer side of the ceramic shell 1.

[0045] As an example, the first notch 14 provides a mechanical alignment reference during encapsulation and welding, enabling precise positioning of the ceramic shell 1 and the ceramic cover plate 2 without signal transmission.

[0046] As an example, please continue reading Figure 2 The ceramic housing 1 also includes a chip mounting area 15 and a bonding wire 16. The chip mounting area 15 is located on the upper surface of the first ceramic layer 121 and is used to mount the chip 3. The first end of the bonding wire 16 is connected to the chip 3, and the second end of the bonding wire 16 is connected to the fourth pad (not shown) on the upper surface of the second ceramic layer 122.

[0047] As an example, the surface material of the chip mounting area 15 can be ceramic or metal, and the chip mounting area 15 achieves signal connection with the third pad on the bottom surface of the ceramic housing 1 through the via of the first ceramic layer 121.

[0048] As an example, the chip mounting area 15 can mount at least one chip 3, depending on the size of the ceramic casing 1 and the chip 3, which is not limited here.

[0049] As an example, the bonding wire 16 can be made of metal wire, which can be used to interconnect the chip 3 and the ceramic housing 1, forming a stable electrical connection. This ensures that the electrical signals of the chip can be effectively transmitted to the ceramic housing 1, and then led out to the external circuit through the first pin 11. This connection method flexibly adapts to the miniaturized design of the package structure, realizing signal transmission between the chip and the internal circuit within a limited cavity space. This helps to shorten the signal transmission path and improve the electrical performance and integration reliability of the package structure.

[0050] As an example, please continue reading Figure 2 The ceramic shell 1 also includes a first cavity 17 and a second cavity 18. The first cavity 17 is located inside the second ceramic layer 122, and the second cavity 18 is located inside the third ceramic layer 123. The first cavity 17 and the second cavity 18 form a stepped structure. The height of the stepped structure is lower than the height of the ceramic shell 1. The stepped surface of the stepped structure is provided with a fourth pad for connecting the bonding wire 16.

[0051] As an example, the first cavity 17 can be a square cavity. The size of the first cavity 17 is larger than the size of the chip 3. It can be used to accommodate the chip 3 and epoxy resin. The space of the first cavity 17 avoids unnecessary contact between the chip 3 and other metal structures of the ceramic shell 1, ensuring stable electrical performance and thus reducing stress.

[0052] As an example, the second cavity 18 can be a circular cavity. The size of the second cavity 18 is larger than that of the first cavity 17. The second cavity 18 and the first cavity 17 form a stepped structure to facilitate the exposure of the fourth pad located on the upper surface of the second ceramic layer 122. The height of the stepped structure is lower than the height of the ceramic shell.

[0053] As an example, the first ceramic body 12 of the ceramic shell 1 is formed by stacking and laminating a first ceramic layer 121, a second ceramic layer 122, and a third ceramic layer 123 using high-temperature co-firing technology and sintering at high temperature. The through-holes punched in each layer are filled with metallized paste, and the printed metal traces in the layers realize the vertical and horizontal electrical interconnection of the three ceramic layers. The first cavity 17 of the second ceramic layer 122 holds the chip 3. The second cavity 18 of the third ceramic layer 123 can expose the fourth pad located on the upper surface of the second ceramic layer 122. Multiple first pins 11 are connected to the lower surface of the first ceramic body 12 by silver-copper solder. The bonding wire 16 is located inside the first cavity 17 and the second cavity 18. One end is connected to the chip 3 in the chip mounting area 15, and the other end is connected to the fourth pad and forms a signal path with the first pins 11 through the internal metallized channel. The first notch 14 is formed by cutting on the side of the first ceramic body for mechanical fitting to realize welding alignment. The multilayer ceramic layer and metallization paste form an efficient signal transmission channel. The first pin 11 is stably connected to the first pad 13 through the signal transmission channel to ensure signal output. The first notch 14 ensures accurate packaging. The chip mounting area 15 and bonding wire 16 adapt to the integration of chip 3 and shorten the path, ultimately forming a high-voltage ceramic packaging structure with small size, high performance and high reliability.

[0054] For example, please refer to Figure 3 Each second pin 21 can be cylindrical or square, and can be made of Kovar alloy. Each second pin 21 can be connected to the upper surface of the second ceramic body 22 by silver-copper solder to lead out signals.

[0055] In one example, the ceramic cover plate 2 may include two second pins 21.

[0056] As an example, please continue reading Figure 3 The second ceramic body 22 is a double-layer ceramic structure, including: a fourth ceramic layer 221 and a fifth ceramic layer 222, with the fifth ceramic layer 222 disposed on the lower surface of the fourth ceramic layer 221.

[0057] Optionally, the fourth ceramic layer 221 is constructed by punching through holes and filling them with metallization paste, while simultaneously printing metal traces and insulating dielectric coverage areas on its surface to create vertical and horizontal signal transmission paths; the fifth ceramic layer 222 does not require punching or printing traces and serves only as a structural support layer. By stacking and laminating the two ceramic layers to form an integrated second ceramic body 22, the package size is significantly reduced, while the rigidity and sealing performance of the cover are improved.

[0058] As an example, the second pad 23 is made of metallized paste as a base, which is sintered at high temperature and then firmly bonded to the fourth ceramic layer 221. The surface is also coated with nickel and gold layers through electroplating, which enhances conductivity and oxidation resistance. The second pad 23 is located on the lower surface of the fourth ceramic layer 221 and is precisely aligned with the first pad 13 of the ceramic shell 1 during packaging, establishing a complete signal transmission link between the chip and the top and bottom leads. This reduces signal loss during transmission, improves electrical performance, and lays the structural foundation for subsequent hermetic packaging.

[0059] As an example, the ceramic cover plate 2 also includes a fifth pad (not shown), which is disposed at the connection between the upper surface of the fourth ceramic layer 221 and the second pin 21.

[0060] For example, please refer to Figure 4 The ceramic cover plate 2 also includes a second notch 24, a solder sheet 25, and at least one insulating medium covering area 26. The second notch 24 is disposed on the outer side of the ceramic cover plate 2 for welding alignment with the first notch 14. The solder sheet 25 is located on the bottom surface of the ceramic cover plate 2 for connecting the ceramic cover plate 2 and the ceramic shell 1. The insulating medium covering area 26 is located on the lower surface of the ceramic cover plate 2, between the solder sheet 25 and the second solder pad 23.

[0061] As an example, the second notch 24 provides a mechanical alignment reference during encapsulation and welding, enabling precise positioning of the ceramic shell 1 and the ceramic cover plate 2 without any signal transmission function.

[0062] As an example, the shape and size of the first notch 14 and the second notch 24 can be adjusted according to the specific design.

[0063] As an example, the solder sheet 25 can be a double-ring annular solder sheet, including an outer annular solder sheet and an inner symmetrical double-arc solder sheet. The material can be AuSn, tin-silver-copper alloy, etc. The ceramic shell 1 and the ceramic cover plate 2 can be welded together by the solder sheet 25. The solder sheet 25 is a key component for achieving hermetic encapsulation, and the solder sheet 25 needs to be far away from the trace area to ensure electrical and sealing performance.

[0064] As an example, the insulating medium coverage area 26 is a designated area on the lower surface of the ceramic cover plate 2 covered with a thin layer of insulating medium, which is a non-ceramic material. The designated area is located between the solder sheet 25 and the first pad 13 / second pad 23. The insulating medium coverage area 26 can isolate the solder sheet and the pad area, realize the solder resist function, and avoid short circuit between the soldering area and the electrical connection area.

[0065] Optionally, the insulating dielectric covering area 26 can also isolate the inner and outer rings of the solder sheet 25 to achieve solder resistance; the insulating dielectric covering area 26 can be of any shape.

[0066] As an example, the second ceramic body 22 is integrally formed by stacking and laminating the fourth ceramic layer 221 and the fifth ceramic layer 222 using high-temperature co-fired ceramic technology and then sintering at high temperature. The fourth ceramic layer 221 has through-holes filled with metallized paste, and its surface is printed with metal traces and second pads 23. It also has an insulating dielectric coverage area 26. The fifth ceramic layer 222, as a structural support layer, has no through-holes or metal traces. The two are tightly bonded to form a double-layer structure. The metallized paste in the through-holes of the fourth ceramic layer 221 is conductive to the metal traces, and the second pads 23 are connected to the metal traces. Multiple second pins 21 are vertically soldered to the upper surface of the fourth ceramic layer 221 using silver-copper solder. The second notch 24 is located at the... The outer surface of the second ceramic body 22 matches the first notch 14 of the ceramic shell 1. The solder pad 25 is pre-welded to the lower surface edge of the second ceramic body 22 and is isolated from the second pad 23 / first pad 13 by the insulating medium covered area 26. This structure improves the overall rigidity and sealing performance of the integrated design of the fourth ceramic layer 221 and the fifth ceramic layer 222. The via and metal trace work together with the second pin 21 to achieve efficient signal transmission. The insulating medium covered area 26 avoids solder overflow and short circuit. The second notch 24 ensures accurate alignment with the ceramic shell 1. The solder pad 25 helps with hermetic packaging. This combination achieves the effects of short signal transmission path, high reliability, and improved packaging accuracy and yield under high voltage environment.

[0067] As an example, the packaging structure provided in this application can be a circular ceramic packaging structure, including double-sided electrodes. Double-sided electrodes refer to a structural design where electrodes are provided both above the ceramic cover plate 2 and below the ceramic shell 1. Multiple first pins 11 are connected to the bottom of the ceramic shell 1 via silver-copper solder to serve as lower electrodes, and multiple second pins 21 are connected to the top of the ceramic cover plate 2 via silver-copper solder to serve as upper electrodes. The upper and lower pins together act as electrodes, enabling simultaneous signal extraction from both the upper and lower surfaces of the packaging structure. This structure can shorten the signal transmission path, improve integration density, and enhance circuit design flexibility.

[0068] In the aforementioned packaging structure, the first pin at the bottom of the ceramic shell and the second pin at the top of the ceramic cover form a double-sided electrode, enabling simultaneous bidirectional signal output, shortening the transmission distance from the chip to the external circuit, and improving electrical performance. The multi-layered ceramic co-fired structure of the ceramic shell and ceramic cover, along with the sealing via annular solder pads, avoids the risk of thermal mismatch between the metal and ceramic, ensuring the reliability of the hermetic packaging. The precise mechanical fitting and alignment of the first notch in the ceramic shell and the second notch in the ceramic cover ensures that the pads and signal transmission holes are aligned one-to-one, improving packaging accuracy. The insulating dielectric covering area on the underside of the cover plate isolates the solder pads from the solder pads, blocking the solder overflow path, preventing short circuits under high voltage conditions, and ensuring electrical safety. The stepped cavity inside the ceramic shell can accommodate the curvature of the bonding wires to reduce mechanical stress, while also accommodating epoxy resin to protect the chip and bonding wires, enhancing structural robustness. Vertical interconnection is achieved through multi-layer ceramic stacking and via metallization, which can significantly reduce the package size, maintain structural stability and high integration, and ultimately form a high-voltage double-sided electrode ceramic hermetic package structure with small size, short electrical signal transmission path, and high reliability.

[0069] In one embodiment, see Figure 5 This application also provides a packaging method applied to the above-mentioned packaging structure. The packaging method includes the following steps: steps S1 to S6.

[0070] Step S1: Using high-temperature co-fired ceramic technology, punch through holes and print wiring for the first ceramic layer; punch through holes and the first cavity for the second ceramic layer and print wiring; punch through holes and the second cavity for the third ceramic layer and print wiring. Then, stack and laminate the first, second, and third ceramic layers to obtain the first green ceramic body. The first green ceramic body is then sintered at high temperature to obtain the first ceramic body.

[0071] Step S2: Using high-temperature co-fired ceramic technology, punch through holes and print wiring on the fourth ceramic layer; no punching or wiring is required on the fifth ceramic layer. Then, stack and laminate the fourth and fifth ceramic layers to obtain the second green ceramic body. The second green ceramic body is then sintered at high temperature to obtain the second ceramic body.

[0072] Step S3: Electroplating the first ceramic body with nickel and gold to obtain a ceramic shell, electroplating the second ceramic body with nickel and gold to obtain a ceramic cover plate, welding multiple first pins to the lower surface of the ceramic shell with silver-copper solder, and welding multiple second pins to the upper surface of the ceramic cover plate with silver-copper solder.

[0073] Step S4: Pre-place solder pads on the lower surface of the ceramic cover plate and place the chip on the upper surface of the first ceramic layer.

[0074] Step S5: Inject epoxy resin into the first and second cavities of the ceramic shell using an automatic dispensing machine.

[0075] Step S6: Bake the solder sheet on the ceramic cover plate to weld the ceramic shell to the ceramic cover plate, achieving hermetic sealing.

[0076] In the packaging method of this application, by simultaneously setting metal pins on the upper and lower parts of the ceramic shell and the cover plate, double-sided electrode signal output can be achieved, shortening the interconnection distance and improving electrical performance under high voltage conditions; by using the ceramic cover plate and the ceramic shell to be welded and sealed with solder sheets, the risk of cracking caused by the mismatch of the thermal expansion coefficients of metal and ceramic can be avoided, ensuring airtightness and reliability; by setting an insulating dielectric covering area on the lower surface of the ceramic cover plate, the solder sheet and signal pad can be isolated to prevent high voltage short circuits; by setting feature notches on the sides of the ceramic shell and the cover plate, precise mechanical alignment can be achieved, improving packaging accuracy and yield; finally, a high-voltage double-sided electrode ceramic airtight packaging structure with small size, short electrical signal transmission path, and high reliability is formed.

[0077] In step S1, please refer to Figure 5 High-temperature co-fired ceramic technology is used to punch through holes and print wiring in the first ceramic layer; through holes and the first cavity are punched in the second ceramic layer and wiring is printed; through holes and the second cavity are punched in the third ceramic layer and wiring is printed. Then, the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain the first green ceramic body. The first green ceramic body is then sintered at high temperature to obtain the first ceramic body.

[0078] As an example, the first green ceramic body may include three ceramic layers, namely, a first ceramic layer 121, a second ceramic layer 122, and a third ceramic layer 123.

[0079] Specifically, based on high-temperature co-fired ceramic technology, multiple first vias are punched in the first ceramic layer 121, metallization paste is filled in each first via, and metal traces are printed on the first ceramic layer 121 to form a basic path for signal transmission; second vias and a first cavity 17 are punched in the second ceramic layer 122, metallization paste is filled in the second vias, and metal traces are printed on the second ceramic layer 122; third vias and a second cavity 18 are punched in the third ceramic layer 123; metallization paste is filled in the third vias, and metal traces are printed on the third ceramic layer 123.

[0080] As an example, the first cavity 17 can be square in shape and larger than the size of the chip 3, and can be used to accommodate the chip 3.

[0081] As an example, the first cavity 17 can serve as a chip mounting area 15 for placing the chip 3.

[0082] As an example, the second cavity 18 can be circular in shape, and its dimensions can be used to accommodate the chip 3. The dimensions of the second cavity 18 are larger than those of the first cavity 17, which facilitates the exposure of the first pad 13 located on the upper surface of the second ceramic layer 122, providing space for the pad connection between the ceramic shell 1 and the ceramic cover plate 2.

[0083] As an example, the first via, the second via, and the third via can be used as signal transmission holes to realize the electrical interconnection of each ceramic layer.

[0084] Further, the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain the first green ceramic body. Then, the side of the first green ceramic body is cut to form the first alignment notch 14. Finally, the first green ceramic body is sintered at high temperature to obtain the first ceramic body 12.

[0085] In step S2, please refer to Figure 5 Using high-temperature co-fired ceramic technology, the fourth ceramic layer is punched with through holes and printed with traces; the fifth ceramic layer does not require punching or printing traces. The fourth and fifth ceramic layers are then stacked and laminated to obtain the second green ceramic body. The second green ceramic body is then sintered at high temperature to obtain the second ceramic body.

[0086] As an example, the second ceramic body 22 is an integral structure of double-layer ceramic, ensuring the rigidity and sealing of the cover plate.

[0087] Specifically, in step S2, a ceramic green sheet is selected as the fourth ceramic layer 221. Based on high-temperature co-fired ceramic technology, a fourth via is punched in the fourth ceramic layer 221. Metallization paste is filled into the fourth via. At the same time, metal traces and an insulating dielectric covering area are printed on the fourth ceramic layer 221. The insulating dielectric covering area is used to isolate the subsequent solder sheet 25 from the first pad 13 / second pad 23. The fifth ceramic layer 222 does not need to be punched or have traces printed; it only serves as a structural support. The fourth ceramic layer 221 and the fifth ceramic layer 222 are stacked and laminated to form a second green ceramic body. A second notch 24 is cut on the side of the second green ceramic body, and its shape matches the first notch 14 for packaging alignment.

[0088] Furthermore, the second green ceramic body with the second notch is sintered at high temperature to obtain the second ceramic body 22.

[0089] In step S3, please refer to step 5. The first ceramic body is electroplated with nickel and gold to obtain a ceramic shell, and the second ceramic body is electroplated with nickel and gold to obtain a ceramic cover plate. Multiple first pins are soldered to the lower surface of the ceramic shell using silver-copper solder, and multiple second pins are soldered to the upper surface of the ceramic cover plate using silver-copper solder.

[0090] Specifically, in step S3, nickel and gold are electroplated onto the upper surface of the third ceramic layer in the first ceramic body 12 as the first pad, and nickel and gold are electroplated onto the lower surface of the fourth ceramic layer in the second ceramic body 22 as the second pad, to enhance the conductivity and oxidation resistance of the first and second pads, and the first and second pads are connected. After electroplating the first ceramic body 12 with nickel and gold, a ceramic shell 1 is obtained, and after electroplating the second ceramic body 22 with nickel and gold, a ceramic cover plate 2 is obtained.

[0091] Furthermore, silver-copper solder is used to solder multiple first pins 11 to the third pad on the lower surface of the ceramic shell 1 to achieve bottom signal output; silver-copper solder is used to solder second pins 21 to the fifth pad on the upper surface of the ceramic cover plate 2 to achieve top signal output, and the first pins 11 and second pins 21 are respectively connected to the first pad 13 and the second pad 23.

[0092] As an example, the first pin is made of Kovar alloy and is cylindrical or square in shape.

[0093] As an example, the second pin is made of Kovar alloy and is cylindrical or square in shape.

[0094] In step S4, please refer to Figure 5 Solder sheets are pre-placed on the lower surface of the ceramic cover plate, and the chip is placed on the upper surface of the first ceramic layer.

[0095] Specifically, in step S4, a solder sheet 25 is pre-placed on the lower surface of the ceramic cover plate 2, and the chip 3 is installed onto the chip mounting area 15 of the ceramic housing 1. The chip 3 can be fixed by conductive adhesive. The chip 3 is interconnected with the inner pins of the ceramic housing by bonding wires / pads to form an electrical connection. The bonding wire 16 is connected to the third pad through the through hole of the ceramic housing 1 to form a signal path between the chip 3 and the first pin 11.

[0096] As an example, the solder sheet 25 can be a double-ring annular solder sheet, including an outer annular ring and an inner symmetrical arc. The material can be AuSn, tin-silver-copper alloy, etc. It can weld the ceramic shell 1 to the ceramic cover plate 2. It is a key component for achieving hermetic encapsulation and needs to be far away from the wiring area to ensure electrical and sealing performance.

[0097] In step S5, please refer to Figure 5 Epoxy resin adhesive is injected into the first and second cavities of the ceramic shell using an automatic dispensing machine.

[0098] Specifically, in step S5, an automatic dispensing machine is used to inject epoxy resin into the first cavity and the second cavity of the ceramic shell 1 to ensure that the adhesive completely covers the chip 3 and the bonding wire 16. After curing, the epoxy resin forms an internal protective layer, which can prevent the chip 3 and the bonding wire 16 from being mechanically damaged during subsequent packaging and enhance internal insulation.

[0099] In step S6, please refer to Figure 5 The solder sheet on the ceramic cover plate is baked to weld the ceramic shell to the ceramic cover plate, thus achieving airtight sealing.

[0100] Specifically, in step S6, the first notch 14 of the ceramic shell 1 and the second notch 24 of the ceramic cover plate 2 are mechanically aligned to ensure that the first pad and the second pad, as well as their signal transmission holes, correspond one-to-one; the solder sheet 25 is baked to melt it, and the molten solder spreads along the upper surface edge of the ceramic shell 1 and the lower surface of the ceramic cover plate 2 to form a sealing ring; after welding, the insulating medium covering area isolates the solder sheet 25 from the second pad 23 to prevent high voltage short circuit, and at the same time, the chip mounting area 15 is hermetically sealed through the sealing ring.

[0101] Optionally, the first via, second via, and third via are all vertical signal transmission channels formed in the corresponding ceramic layers based on high-temperature co-fired ceramic technology. The first via is located in the first ceramic layer 121 and is formed by a stamping process. The hole is filled with a metallization paste specifically for high-temperature co-fired ceramics. It is conductive to the metal traces printed on the surface of the first ceramic layer 121, serving as the basis for vertical interconnection and providing an initial channel for signal transmission from the chip mounting area to the lower pins. The second via is located in the second ceramic layer 122 and is also formed by stamping and filled with metallization paste. It is correspondingly connected to the metal traces of the second ceramic layer 122 and the first via. Since the second ceramic layer 122 has a first cavity 17 for accommodating the chip, the second via must avoid the cavity area. It not only realizes signal conduction inside the second ceramic layer 122, but also, through cooperation with the first via, transmits the signal transmitted from the chip to the second ceramic layer via the bonding wire 16 down to the first ceramic layer 121. The third via is located in the third ceramic layer 123. It is formed by punching and filled with metallization paste, and is connected to the metal traces of the third ceramic layer 123 and the second via. The three vias work together with the metallization paste and the metal traces of the corresponding ceramic layers to build a continuous electrical path from the chip mounting area 15 through each ceramic layer to the first pin 11. This achieves efficient vertical interconnection of the multilayer ceramic structure, which not only ensures the stability and low loss of signal transmission, but also supports the multilayer integrated design of the package structure, laying the foundation for reducing package size and increasing integration density.

[0102] In the above packaging method, the high-temperature co-fired ceramic technology enables the stacking of multiple ceramic layers and the design of metallized vias and traces, which can construct efficient vertical and horizontal signal transmission paths, shorten signal transmission distances, and meet the requirements of high-density interconnection. By electroplating nickel and gold onto the ceramic body to enhance the conductivity and oxidation resistance of the pads, and combining it with silver-copper solder to weld Kovar alloy pins to form a double-sided electrode structure, bidirectional signal output can be achieved, improving circuit design flexibility and integration density. By pre-placing solder pads on the ceramic cover plate and combining it with a baking and soldering process, the risk of solder joint cracking caused by the difference in thermal expansion coefficients between ceramic and metal can be reduced, ensuring the hermeticity and reliability of the package. The insulating dielectric covering area on the lower surface of the ceramic cover plate isolates the solder pads from the pads, avoiding short circuits under high-voltage environments and improving structural safety. The injection of epoxy resin adhesive by an automatic dispensing machine to cover the chip and bonding wires forms an internal protective layer, preventing mechanical damage and enhancing insulation, thus improving the stability of the internal structure. The feature notches on the sides of the ceramic shell and the cover plate enable precise mechanical alignment, improving packaging accuracy and yield, and ensuring accurate connection between the pads and signal transmission holes.

[0103] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] Although this application has been disclosed above with reference to embodiments, it is not intended to limit this application. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this application.

Claims

1. A packaging structure, characterized in that, include: A ceramic housing and a ceramic cover plate are connected together. The ceramic housing includes a plurality of first pins, a first ceramic body, and a first pad. The plurality of first pins are disposed on the lower surface of the first ceramic body, and the first pad is disposed on the upper surface of the first ceramic body. The ceramic cover plate includes a plurality of second pins, a second ceramic body, a second pad, a solder sheet, and at least one insulating dielectric covering area. The plurality of second pins are disposed on the upper surface of the second ceramic body, and the second pad is disposed on the lower surface of the second ceramic body. The solder sheet is disposed between the ceramic housing and the ceramic cover plate, and the ceramic housing and the ceramic cover plate are welded together by the solder sheet. The insulating dielectric covering area is disposed in a designated area on the lower surface of the second ceramic body, and the designated area is located between the solder sheet and the first pad or the solder sheet and the second pad, thus isolating the solder sheet from the pad.

2. The packaging structure according to claim 1, characterized in that, The first ceramic body is a multi-layer ceramic structure, including: a first ceramic layer, a second ceramic layer and a third ceramic layer. The first ceramic layer serves as a substrate, the second ceramic layer is disposed on the upper surface of the first ceramic layer, and the third ceramic layer is disposed on the upper surface of the second ceramic layer.

3. The packaging structure according to claim 1, characterized in that, The second ceramic body is a double-layer ceramic structure, including a fourth ceramic layer and a fifth ceramic layer, wherein the fifth ceramic layer is disposed on the lower surface of the fourth ceramic layer.

4. The packaging structure according to claim 1, characterized in that, The solder sheet is a double-ringed annular solder sheet, comprising an outer annular solder sheet and an inner symmetrical double-arc solder sheet.

5. The packaging structure according to claim 1, characterized in that, The solder sheet is made of AuSn, a tin-silver-copper alloy.

6. The packaging structure according to claim 1, characterized in that, Each of the first pins is cylindrical or square and made of Kovar alloy; each of the second pins is cylindrical or square and made of Kovar alloy.

7. The packaging structure according to claim 1, characterized in that, The ceramic shell also includes a first cavity and a second cavity, wherein the first cavity is located inside the second ceramic layer and the second cavity is located inside the third ceramic layer.

8. The packaging structure according to claim 7, characterized in that, The size of the first cavity is larger than the chip size, and the size of the second cavity is larger than the size of the first cavity.

9. A packaging method, characterized in that, The application of the packaging structure as described in any one of claims 1 to 8 includes the following steps: High-temperature co-fired ceramic technology is used to punch through holes and print wiring in the first ceramic layer; through holes and a first cavity are punched in the second ceramic layer and wiring is printed; through holes and a second cavity are punched in the third ceramic layer and wiring is printed. Then, the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain a first green ceramic body. The first green ceramic body is sintered at high temperature to obtain a first ceramic body. The side of the first ceramic body is scored to form an alignment first notch. Using high-temperature co-fired ceramic technology, the fourth ceramic layer is punched with through holes and printed with wiring; the fifth ceramic layer does not require punching or printing of wiring. The fourth and fifth ceramic layers are then stacked and laminated to obtain a second green ceramic body. The second green ceramic body is then sintered at high temperature to obtain a second ceramic body. The first ceramic body is electroplated with nickel and gold to obtain a ceramic shell, and the second ceramic body is electroplated with nickel and gold to obtain a ceramic cover plate. Multiple first pins are soldered to the lower surface of the ceramic shell using silver-copper solder, and multiple second pins are soldered to the upper surface of the ceramic cover plate using silver-copper solder. Solder sheets are pre-placed on the lower surface of the ceramic cover plate, and the chip is placed on the upper surface of the first ceramic layer; Epoxy resin adhesive is injected into the first and second cavities of the ceramic shell using an automatic dispensing machine; The solder sheet on the ceramic cover plate is baked to weld the ceramic shell to the ceramic cover plate, thereby achieving airtight encapsulation.

10. The packaging method according to claim 9, characterized in that, Using high-temperature co-fired ceramic technology, vias are punched and traces are printed on the fourth ceramic layer; no punching or trace printing is required on the fifth ceramic layer. The fourth and fifth ceramic layers are then stacked and laminated to obtain a second green ceramic body. This second green ceramic body is then sintered at high temperature to obtain a second ceramic body. The process includes selecting a ceramic green sheet as the fourth ceramic layer, punching a fourth via on the fourth ceramic layer using high-temperature co-fired ceramic technology, filling the fourth via with metallization paste, and simultaneously printing metal traces and an insulating dielectric covering area on the fourth ceramic layer. The insulating dielectric covering area is used to isolate subsequent solder pads from the first and second solder pads. The fifth ceramic layer does not require punching or trace printing and only serves as structural support. The fourth ceramic layer and the fifth ceramic layer are stacked and laminated to form a second green ceramic body. A second notch is cut on the side of the second green ceramic body, the shape of which matches the first notch. The second green ceramic body with the second notch is sintered at high temperature to obtain the second ceramic body.

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