Packaging assembly, packaging module and preparation method of packaging module

Abstract

The invention discloses a packaging assembly, a packaging module and a preparation method of the packaging module, the packaging assembly comprises a first mother board, the first mother board comprises a first frame and a plurality of groups of first daughter boards, the plurality of groups of first daughter boards are distributed at intervals along a first direction, and each group of first daughter boards comprises a plurality of first daughter boards distributed at intervals along a second direction, the first mother board further comprises a plurality of first connecting parts, and the first daughter boards are connected with the first daughter boards which are adjacent in the first direction and the second direction through the first connecting parts; the plurality of chips are arranged corresponding to the first daughter boards, and the first side of each chip is electrically connected with the corresponding first daughter board; the packaging assembly is configured to be capable of segmenting the first connecting part along a set track so as to separate a plurality of subunits, at least part of the segmented first connecting part forms conductive terminals of the subunits, and the packaging assembly is further configured to be capable of segmenting different first connecting parts along different set tracks so as to form at least two subunits. And the numbers of the chips in different subunits are different, so that the process can be simplified.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a packaging component, a packaging module and a method for preparing the packaging module. Background Art

[0002] For packaging modules with a top metal layer, the current preparation process is to connect the chip to the substrate and then connect the top metal sheet on the top of the chip. When the packaging module includes multiple chips, it is also necessary to connect the top metal sheets of different chips through leads. The process is cumbersome, especially when it comes to the production of packaging modules of different models. Since the number of chips inside packaging modules of different models is different, the complexity of the process will be further increased, which is not conducive to reducing product costs. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a packaging component that can simplify the process and reduce the cost of the product.

[0004] The present invention also provides a packaging module and a method for preparing the packaging module.

[0005] A packaging assembly according to a first embodiment of the present invention includes: a first motherboard made of a conductive material, the first motherboard including a plurality of groups of first daughter boards, the plurality of groups of first daughter boards being spaced apart along a first direction, each group of first daughter boards including a plurality of first daughter boards spaced apart along a second direction, the first direction being perpendicular to the second direction, the first motherboard further including a plurality of first connecting portions, each first daughter board being connected to a first daughter board adjacent to the first direction and to a first daughter board adjacent to the second direction via the first connecting portions; a plurality of chips, arranged corresponding to each of the first sub-boards, wherein a first side of each of the chips is electrically connected to the corresponding first sub-board; In which, the packaging component is configured to be able to split the first connecting part along a set track to separate multiple sub-units, and at least part of the split first connecting part forms the conductive terminal of the sub-unit, and the packaging component is also configured to be able to split different first connecting parts along different set tracks to form at least two sub-units, and the number of chips in different sub-units is different.

[0006] The motherboard according to the first embodiment of the present invention has at least the following beneficial effects: This embodiment can separate the subunits by disconnecting the first connection portion by cutting along the first and second directions. Different subunits containing different numbers of chips can be formed by simply adjusting the cutting trajectory, further simplifying the process. Furthermore, the first connection portion in this embodiment not only secures the first sub-board but also serves as a conductive member to achieve electrical connection between adjacent chips. For a package module containing multiple chips, this embodiment can replace the leads with the retained first connection portion, eliminating the step of connecting the leads and helping to reduce the cost of the package module.

[0007] In other embodiments of the present invention, each of the first sub-plates has a source conductive portion and a gate conductive portion that are spaced apart from each other, and the plurality of first connecting portions include a first sub-connecting portion and a second sub-connecting portion. The source conductive portion is connected to the first sub-plate adjacent to the first direction via the first sub-connecting portion, and is connected to the first sub-plate adjacent to the second direction via the second sub-connecting portion. The gate conductive portion is connected to the first sub-plate adjacent to the first direction via the first sub-connecting portion, and is connected to the first sub-plate adjacent to the second direction via the second sub-connecting portion. The chip includes a source region and a gate region located on the first side, the source region is connected to the source conductive portion corresponding to the first sub-board, and the gate region is electrically connected to the gate conductive portion of the same first sub-board.

[0008] In other embodiments of the present invention, the source conductive portion is connected to the source conductive portion of the first sub-board adjacent in the first direction through the first sub-connection portion, and is connected to the gate conductive portion of the first sub-board adjacent in the second direction through the second sub-connection portion.

[0009] In other embodiments of the present invention, the gate conductive portion is connected to the source conductive portion of the first sub-board adjacent to the first direction through the first sub-connection portion, and the gate conductive portion is connected to the source conductive portion of the first sub-board adjacent to the second direction through the second sub-connection portion.

[0010] In other embodiments of the present invention, each of the gate conductive portions is provided with the first sub-connection portion on both sides opposite to each other along the first direction, wherein one side of the gate conductive portion is connected to the source conductive portion of one of the first sub-boards adjacent in the first direction through the first sub-connection portion, and the other side is connected to the gate conductive portion of another first sub-board adjacent in the first direction through the first sub-connection portion.

[0011] In other embodiments of the present invention, the package assembly further includes a second motherboard, the second motherboard including a plurality of groups of second daughter boards, the plurality of groups of second daughter boards being spaced apart along the first direction, each group of second daughter boards including a plurality of second daughter boards spaced apart along the second direction, the second motherboard further including a plurality of second connecting portions, each second daughter board being connected to the second daughter board adjacent to the first direction and adjacent to the second direction via the second connecting portions; Each of the chips includes a drain region located on a second side, the drain region is electrically connected to the corresponding second sub-board, and the second side is arranged opposite to the first side; The packaging component is configured to be able to split the first connection portion and the second connection portion along the set track to separate multiple sub-units, and to be able to split different first connection portions and second connection portions along different set tracks to form at least two sub-units.

[0012] In other embodiments of the present invention, the plurality of second connection parts include a third sub-connection part and a fourth sub-connection part, and the second sub-board is connected to the second sub-board adjacent to the first direction through the third sub-connection part, and is connected to the second sub-board adjacent to the second direction through the fourth sub-connection part.

[0013] In other embodiments of the present invention, the packaging assembly further includes a first connection layer located between the first daughter board and the first side corresponding to the chip, and the first connection layer includes a nanowire layer.

[0014] The packaging module according to the second embodiment of the present invention includes or is configured as the sub-unit separated from the packaging assembly.

[0015] In other embodiments of the present invention, the packaging module includes a single chip and a single first daughter board; Alternatively, the packaging module includes a plurality of the chips and a plurality of first sub-boards corresponding to the plurality of the chips, the plurality of chips are distributed along the first direction, and each first sub-board is connected to the first sub-board adjacent to the first direction via the first connecting portion; or, the plurality of chips are distributed along the second direction, and each first sub-board is connected to the first sub-board adjacent to the second direction via the first connecting portion; Alternatively, the packaging module includes multiple groups of chips and multiple groups of first sub-boards corresponding to the multiple groups of chips, the multiple groups of chips are distributed along the first direction, each group of chips contains multiple chips distributed along the second direction, and each first sub-board is connected to the first sub-board adjacent to the first direction and the first sub-board adjacent to the second direction through the first connecting part.

[0016] A method for preparing a package module according to a third embodiment of the present invention includes the following steps: preparing the packaging assembly; The packaging component is divided according to a set track to separate the plurality of sub-units, and the dividing track includes a transverse dividing track parallel to the first direction and a longitudinal dividing track parallel to the second direction.

[0017] The package assembly is divided according to a set track to separate the plurality of sub-units, comprising: dividing the package assembly according to a first track to separate a plurality of first-type sub-units, wherein a single chip is separated between each of the transverse dividing tracks in the first track, and a single chip is separated between each of the longitudinal dividing tracks, and the first-type sub-unit includes a single chip and a single first sub-board; Alternatively, dividing the package assembly according to a set track to separate the plurality of sub-units includes: dividing the package assembly according to a second track to separate a plurality of second-type sub-units, wherein a plurality of chips are spaced between each of the transverse dividing tracks in the second track, and a single chip is spaced between each of the longitudinal dividing tracks, the second-type sub-units including a plurality of chips and a plurality of the first sub-boards corresponding to the plurality of chips, and the plurality of chips are distributed along the second direction; Alternatively, dividing the package assembly according to a set track to separate the plurality of sub-units includes: dividing the package assembly according to a third track to separate a plurality of sub-units of a third type, wherein a single chip is separated between each of the transverse dividing tracks in the third track, and a plurality of chips are separated between each of the longitudinal dividing tracks, wherein the third type of sub-units includes a plurality of the chips and a plurality of the first sub-boards corresponding to the plurality of the chips, and the plurality of chips are distributed along the first direction; Alternatively, the packaging component is divided according to a set track to separate a plurality of the sub-units, including: dividing the packaging component according to a fourth track to separate a plurality of fourth-type sub-units, a plurality of the chips are spaced between each of the horizontal dividing tracks in the fourth track, and a plurality of the chips are spaced between each of the vertical dividing tracks, the fourth-type sub-units include multiple groups of the chips and multiple groups of the first sub-boards corresponding to the multiple groups of chips, the multiple groups of chips are distributed along the first direction, and each group of chips includes multiple chips distributed along the second direction.

[0018] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which: Figure 1 This is a front view of the packaging component in an embodiment of the present invention; Figure 2 for Figure 1 Rear view of the packaged components; Figure 3 for Figure 1 Exploded diagram of the package components; Figure 4 for Figure 1 A main view of the first motherboard of the package assembly; Figure 5 for Figure 4 A partial schematic diagram showing the connection relationship between adjacent first sub-boards; Figure 6 is a partial schematic diagram showing the connection relationship between adjacent first sub-boards in another embodiment; Figure 7 is a three-dimensional schematic diagram of a packaging module in an embodiment of the present invention; Figure 8 is a three-dimensional schematic diagram of a subunit in an embodiment of the present invention; Figure 9 is a three-dimensional schematic diagram of a packaging module in another embodiment of the present invention; Figure 10 is a three-dimensional schematic diagram of a packaging module in another embodiment of the present invention; Figure 11 is a schematic diagram of a first trajectory in an embodiment of the present invention; Figure 12 is a schematic diagram of a second trajectory in an embodiment of the present invention; Figure 13 Schematic diagram of the fourth trajectory in an embodiment of the present invention.

[0020] Reference numerals: Packaging component 10; First motherboard 100, first daughter board 110, source conductive portion 111, middle source conductive portion 111a, left source conductive portion 111b, right source conductive portion 111c, upper source conductive portion 111d, gate conductive portion 112, middle gate conductive portion 112a, left gate conductive portion 112b, right gate conductive portion 112c, lower gate conductive portion 112d, first connecting portion 120, first sub-connecting portion 121, source first sub-connecting portion 121a, gate first sub-connecting portion 121b, second sub-connecting portion 122, source second sub-connecting portion 122a, gate second sub-connecting portion 122b, first frame 130; The second motherboard 200, the second daughterboard 210, the second connecting portion 220, the third sub-connecting portion 221, the fourth sub-connecting portion 222, and the second frame 230; Chip 300; First connection layer 400; a second connection layer 500; Subunit 20, conductive terminal 21, molded body 22; Encapsulation module 30; Horizontal segmentation trajectory A; Vertical segmentation trajectory B. DETAILED DESCRIPTION

[0021] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0022] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0023] In the description of the present invention, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0024] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0025] In the description of the present invention, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0026] The first embodiment of the present invention provides a packaging assembly 10, which can be used to prepare packaging modules 30 of different models with a relatively simplified process, thereby helping to reduce the cost of the packaging modules 30. Figures 1 to 3 The package assembly 10 includes a first motherboard 100, a chip array, and a first connection layer 400 disposed between the first motherboard 100 and the chip array. The first motherboard 100 is connected to a first side of the chip array via the first connection layer 400. Figure 3 In some specific embodiments, the package assembly 10 further includes a second motherboard 200 and a second connection layer 500 disposed between the second motherboard 200 and the chip array. The second motherboard 200 is connected to the second side of the chip array via the second connection layer 500. The second side is disposed opposite to the first side. Figure 3 The lower side of the .

[0027] Reference Figure 3 The chip array includes a plurality of chips 300, and the plurality of chips 300 are arranged in a matrix. Specifically, the plurality of chips 300 are arranged along a first direction (eg Figure 1 The chips 300 are divided into multiple groups along the second direction (eg, Figure 1 A plurality of chips 300 are distributed in the vertical direction (in the vertical direction). A first side of the chip 300 (eg Figure 3 The upper side of the electrode has a source region and a gate region, and the second side (e.g. Figure 3 The lower side of the device has a drain region.

[0028] The first motherboard 100 is made of conductive material to achieve electrical connection between the chip 300 and the outside world and between the chips 300. For example, the first motherboard 100 is made of copper. Figure 1 and Figure 4 The first motherboard 100 includes multiple sets of first daughter boards 110, which are spaced apart along a first direction. Each set of first daughter boards 110 includes multiple first daughter boards 110 spaced apart along a second direction, such that each first daughter board 110 corresponds to each chip 300. In some specific embodiments, the first motherboard 100 also includes a first frame 130, which is configured as a rectangular frame. The multiple sets of first daughter boards 110 are connected to the inner side of the first frame 130 and are spaced apart from the first frame 130 by a predetermined distance.

[0029] In addition, the first motherboard 100 also includes multiple first connecting parts 120, and each first sub-board 110 is connected to the first sub-board 110 adjacent in the first direction and the first sub-board 110 adjacent in the second direction through the first connecting part 120. For example, for the first sub-board 110 on the outermost periphery, in addition to being adjacent to other first sub-boards 110, it is also adjacent to the first frame 130. In addition to being connected to the adjacent first sub-board 110 through the first connecting part 120, the first sub-board 110 on the outermost periphery is also connected to the first frame 130 through the first connecting part 120; for the first sub-board 110 on the inside, it is surrounded by other first sub-boards 110, and the first sub-board 110 is only connected to the adjacent first sub-board 110 through the first connecting part 120. Each first sub-board 110, each first connecting portion 120, and the first frame 130 form an integrated structure. The outermost first sub-board 110 is secured by the first frame 130, while each inner first sub-board 110 is secured by an adjacent first sub-board 110. In this way, all first sub-boards 110 can be secured, facilitating storage and transfer of the entire first motherboard 100. As a specific method for preparing the first motherboard 100, a portion of material can be removed from an entire copper plate through stamping, wire cutting, etching, or other methods. The remaining portion of the copper plate forms the aforementioned first sub-boards 110, first connecting portions 120, and first frame 130. It should be noted that in some embodiments, the first frame 130 of the first motherboard 100 is retained during the processing of the package assembly 10, and the finished package assembly 10 will include the first frame 130. In other embodiments, the first frame 130 of the first motherboard 100 is removed during the processing of the package assembly 10, and the finished package assembly 10 will no longer include the first frame 130.

[0030] Based on the above, adjacent first sub-panels 110 and first sub-panels 110 and first frame 130 are spaced apart and connected by first connecting portions 120. Thus, when a first connecting portion 120 is cut, adjacent first sub-panels 110 or first sub-panels 110 and first frame 130 are disconnected. That is, by dividing the first connecting portion 120 of the package assembly 10 along a predetermined trajectory, a plurality of sub-units 20 can be separated, and at least a portion of the divided first connecting portion 120 forms the conductive terminals 21 of the sub-units 20. Exemplarily, the predetermined trajectory includes a transverse dividing trajectory A parallel to the first direction and a longitudinal dividing trajectory B parallel to the second direction. It should be noted that in some specific embodiments, the sub-unit 20 is a package module 30. In other embodiments, the sub-unit 20 is configured as an intermediate product, which is further molded to form a package module, as will be described in subsequent embodiments.

[0031] On the other hand, if the connection of a certain first connecting part 120 is maintained, the adjacent first sub-boards 110 can still be connected into an integrated structure through the first connecting part 120. At this time, the separated sub-unit 20 will include multiple first sub-boards 110 and multiple chips 300. In other words, by adjusting different segmentation trajectories, different types of sub-units 20 can be obtained, and the number of chips 300 in different sub-units 20 is different.

[0032] In this embodiment, multiple chips 300 can be simultaneously connected to the first motherboard 100 to form a package assembly 10, and then separated into sub-units by segmentation. This has higher production efficiency than the solution of individually connecting the chips to the top metal sheet in the related art. On the other hand, since the first sub-boards 110 are grouped along the first direction, and the multiple first sub-boards 110 in each group are arranged along a second direction perpendicular to the first direction, the first connecting portions 120 used to connect the first sub-boards 110 and between the first sub-boards 110 and the first frame 130 are also distributed along the first and second directions. Based on this, the first connecting portions 120 can be disconnected by segmentation along the first and second directions to separate the sub-units 20. Moreover, different sub-units 20 containing different numbers of chips can be formed by simply adjusting the segmentation trajectory, which can further simplify the process. In addition, the first connecting portion 120 in this embodiment can not only fix the first sub-board 110, but also serve as a conductive part to realize electrical connection between adjacent chips 300. For the packaging module 30 containing multiple chips, this embodiment can replace the lead by retaining the first connecting portion 120, thereby eliminating the step of connecting the lead, which helps to reduce the cost of the packaging module 30.

[0033] It should be noted that, in this embodiment, there is no limitation on the method of dividing the first connection portion 120 . For example, the first connection portion 120 may be divided by cutting with a knife or by cutting with a laser.

[0034] On the basis of the first embodiment, in some embodiments of the present invention, referring to Figure 4 、 Figure 5 Each first sub-board 110 has a source conductive portion 111 and a gate conductive portion 112 arranged at intervals. The source conductive portion 111 is used to connect to the source region of the chip 300, and the gate conductive portion 112 is used to connect to the gate region of the chip 300. The source conductive portion 111 can be set as one as shown in the figure, or it can be set as multiple. When it is set as multiple, the multiple source conductive portions 111 are connected and conducted through the third connecting portion.

[0035] In order to adapt to the connection of the first sub-board 110 along the first direction and the second direction, the plurality of first connecting portions 120 include at least two types, one of which is named as the first sub-connecting portion 121, and the other is named as the second sub-connecting portion 122. The first sub-connecting portion 121 is used to realize the connection between adjacent first sub-boards 110 or between the first sub-board 110 and the first frame 130 along the first direction (for example Figure 5 The second sub-connection portion 122 is used to realize the connection between adjacent first sub-boards 110 or between the first sub-board 110 and the first frame 130 along the second direction (for example Figure 5 The source conductive portion 111 and the gate conductive portion 112 are both fixed in the first and second directions by corresponding first connecting portions 120. Specifically, the source conductive portion 111 is connected to the first sub-plate 110 adjacent in the first direction via the first sub-connecting portion 121, and is connected to the first sub-plate 110 adjacent in the second direction via the second sub-connecting portion 122. The gate conductive portion 112 is connected to the first sub-plate 110 adjacent in the first direction via the first sub-connecting portion 121, and is connected to the first sub-plate 110 adjacent in the second direction via the second sub-connecting portion 122. For further distinction, the first sub-connecting portion 121 and the second sub-connecting portion 122 connected to the source conductive portion 111 are respectively named source first sub-connecting portion 121a and source second sub-connecting portion 122a, and the first sub-connecting portion 121 and the second sub-connecting portion 122 connected to the gate conductive portion 112 are respectively named gate first sub-connecting portion 121b and gate second sub-connecting portion 122b.

[0036] By fixing the source conductive portion 111 or the gate conductive portion 112 in two directions perpendicular to each other through the first sub-connection portion 121 and the second sub-connection portion 122, the source conductive portion 111 or the gate conductive portion 112 can be firmly placed in the first motherboard 100, and the deformation of the source conductive portion 111 or the gate conductive portion 112 can be effectively reduced.

[0037] It should be noted that this embodiment does not limit the number of first sub-connection portions 121 and second sub-connection portions 122 connected to the source conductive portion 111 or the gate conductive portion 112. In the illustrated embodiment, a single side of the source conductive portion 111 or the gate conductive portion 112 is connected to the first sub-board 110 adjacent to that side through a single sub-connection portion. In other specific embodiments, a single side of the source conductive portion 111 or the gate conductive portion 112 may also be connected to the first sub-board 110 adjacent to that side through multiple sub-connections.

[0038] When the first sub-plate 110 has a source conductive portion 111 and a gate conductive portion 112 spaced apart, and the plurality of first connecting portions 120 include a first sub-connecting portion 121 and a second sub-connecting portion 122, in some embodiments of the present invention, referring to Figure 5 The aforementioned “the source conductive portion 111 is connected to the first sub-plate 110 adjacent in the first direction through the first sub-connection portion 121” specifically means: the source conductive portion 111 is connected to the source conductive portion 111 of the first sub-plate 110 adjacent in the first direction through the first sub-connection portion 121; the aforementioned “the source conductive portion 111 is connected to the first sub-plate 110 adjacent in the second direction through the second sub-connection portion 122” specifically means: the source conductive portion 111 is connected to the gate conductive portion 112 of the first sub-plate 110 adjacent in the second direction through the second sub-connection portion 122.

[0039] Specifically, for ease of identification and description, Figure 5 The scope of each sub-connection is marked by a dotted line, and Figure 5 The source conductive portion 111 and the gate conductive portion 112 in the first sub-plate 110 located in the center are respectively named as the middle source conductive portion 111a and the middle gate conductive portion 112a. Based on them, the source conductive portion 111 and the gate conductive portion 112 in the first sub-plate 110 on the left are respectively named as the left source conductive portion 111b and the left gate conductive portion 112b. The source conductive portion 111 and the gate conductive portion 112 in the first sub-plate 110 on the right are respectively named as the right source conductive portion 111c and the right gate conductive portion 112c. The source conductive portion 111 in the upper first sub-plate 110 is named as the upper source conductive portion 111d. The gate conductive portion 112 in the lower first sub-plate 110 is named as the lower gate conductive portion 112d.

[0040] Based on the above, specifically, the left side of the middle source conductive part 111a is connected to the left source conductive part 111b through the source first sub-connection part 121a, the right side is connected to the right source conductive part 111c through the source first sub-connection part 121a, and the lower side is connected to the lower gate conductive part 112d through the source second sub-connection part 122a.

[0041] In this embodiment, the source first sub-connection portion 121a is used to connect adjacent source conductive portions 111 in the first direction, and the source second sub-connection portion 122a is used to connect adjacent source conductive portions 111 and gate conductive portions 112 in the second direction, so as to facilitate the distribution of the first sub-connection portions 121 in the circumferential direction of the source conductive portion 111.

[0042] When the first sub-plate 110 has a source conductive portion 111 and a gate conductive portion 112 spaced apart, and the plurality of first connecting portions 120 include a first sub-connecting portion 121 and a second sub-connecting portion 122, in some embodiments of the present invention, referring to Figure 5 The aforementioned "gate conductive portion 112 is connected to the first sub-plate 110 adjacent in the first direction via the first sub-connection portion 121" specifically means: the gate conductive portion 112 is connected to the source conductive portion 111 of the first sub-plate 110 adjacent in the first direction via the first sub-connection portion 121. The aforementioned "gate conductive portion 112 is connected to the first sub-plate 110 adjacent in the second direction via the second sub-connection portion 122" specifically means: the gate conductive portion 112 is connected to the source conductive portion 111 of the first sub-plate 110 adjacent in the second direction via the second sub-connection portion 122. Based on the aforementioned nomenclature, specifically, the left side of the middle gate conductive portion 112a is connected to the left source conductive portion 111b via the gate first sub-connection portion 121b, and the upper side is connected to the upper source conductive portion 111d via the gate second sub-connection portion 122b. Exemplarily, the gate first sub-connection portion 121b in this embodiment has an inclined connection section to accommodate the connection between the gate conductive portion 112 and the adjacent source conductive portion 111.

[0043] In this embodiment, the gate conductive portion 112 is connected to the adjacent source conductive portion 111 through the gate first sub-connection portion 121b. The gate first sub-connection portion 121b can span the gap between adjacent first sub-plates 110 along the first direction, and can also span the gap between the source conductive portion 111 and the gate conductive portion 112 along the second direction, thereby realizing the staggered connection between the gate conductive portion 112 and the source conductive portion 111 of the adjacent first sub-plates 110, which can improve the overall strength of the first motherboard 100.

[0044] It should be noted that when the separated sub-unit 20 includes multiple chips 300 and corresponding first sub-boards 110, in order to prevent direct conduction between the gate regions and source regions of adjacent chips, it is necessary to cut off the gate first sub-connecting portion 121b by means of segmentation or the like. On the other hand, in order to achieve parallel connection between the gate regions of adjacent chips, adjacent gate conductive portions 112 can be connected separately by wires.

[0045] When the gate conductive portion 112 and the source conductive portion 111 of the adjacent first sub-plates 110 are staggered and connected, in some embodiments of the present invention, referring to Figure 6, each gate conductive portion 112 is provided with a first sub-connection portion 121 on both sides opposite to each other along the first direction, wherein one side of the gate conductive portion 112 is connected to the source conductive portion 111 of a first sub-plate 110 adjacent to the first direction through the first sub-connection portion 121, and the other side is connected to the gate conductive portion 112 of another first sub-plate 110 adjacent to the first direction through the first sub-connection portion 121, that is, Figure 5 Compared with the solution in , this embodiment adds a first sub-connection portion 121 on the other side of the gate conductive portion 112, and the adjacent gate conductive portions 112 can be connected to the first sub-connection portion 121. When the separated sub-unit 20 includes multiple chips 300 and the corresponding first sub-board 110, the gate regions of adjacent chips can be connected through the adjacent gate conductive portions 112 and the first sub-connection portion 121 therebetween, thereby eliminating the need for additional leads.

[0046] Based on the aforementioned naming, specifically, the left side of the middle gate conductive portion 112 a is connected to the right gate conductive portion 112 c through the gate first sub-connection portion 121 b .

[0047] In other embodiments, the aforementioned “gate conductive portion 112 is connected to the first sub-plate 110 adjacent to the first direction through the first sub-connection portion 121” specifically means that the gate conductive portion 112 is connected to the gate conductive portion 112 of the first sub-plate 110 adjacent to the first direction through the first sub-connection portion 121, that is, Figure 5 Compared with the solution in FIG, in this embodiment, the gate conductive portion 112 is connected to the adjacent gate conductive portion 112 through the first sub-connection portion 121 instead of being connected to the adjacent source conductive portion 111.

[0048] On the basis of the first embodiment, in some embodiments of the present invention, referring to Figure 2 The package assembly 10 also includes a second motherboard 200. Each chip 300 includes a drain region located on the second side. The drain region of each chip 300 is electrically connected to the corresponding second motherboard 200. In this way, both opposite sides of the chip 300 can be protected. Compared with the method of storing or transferring the chip 300 separately, the risk of failure of the chip 300 during storage and transfer can be significantly reduced.

[0049] The second motherboard 200 is made of a conductive material, exemplarily copper. The second motherboard 200 includes multiple sets of second daughter boards 210 spaced apart along a first direction. Each set of second daughter boards 210 includes multiple second daughter boards 210 spaced apart along a second direction, such that each second daughter board 210 corresponds to each chip 300. In some specific embodiments, the second motherboard 200 also includes a second frame 230, which is configured as a rectangular frame. The multiple sets of second daughter boards 210 are connected to the inner side of the second frame 230 and are spaced apart from the second frame 230 by a predetermined distance.

[0050] In addition, the second motherboard 200 also includes multiple second connecting parts 220, and each second sub-board 210 is connected to the second sub-board 210 adjacent in the first direction and the second direction through the second connecting part 220. For example, for the second sub-board 210 on the outermost periphery, in addition to being adjacent to other second sub-boards 210, it is also adjacent to the second frame 230. In addition to being connected to the adjacent second sub-board 210 through the second connecting part 220, the second sub-board 210 on the outermost periphery is also connected to the second frame 230 through the second connecting part 220; for the second sub-board 210 on the inside, it is surrounded by other second sub-boards 210, and the second sub-board 210 is only connected to the adjacent second sub-board 210 through the second connecting part 220. Each second sub-board 210, each second connecting portion 220, and the second frame 230 form an integrated structure. The outermost second sub-board 210 is secured by the second frame 230, and each inner second sub-board 210 is secured by an adjacent second sub-board 210. In this way, all second sub-boards 210 can be secured, facilitating storage and transfer of the entire second motherboard 200. As a specific method for preparing the second motherboard 200, a portion of material can be removed from an entire copper plate through stamping, wire cutting, etching, or other methods. The remaining portion of the copper plate forms the aforementioned second sub-boards 210, second connecting portions 220, and second frame 230. It should be noted that in some embodiments, the second frame 230 of the second motherboard 200 is retained during the processing of the package assembly 10, and the prepared package assembly 10 will include the second frame 230. In other embodiments, the second frame 230 of the second motherboard 200 is removed during the processing of the package assembly 10, and the prepared package assembly 10 will no longer include the second frame 230.

[0051] Adjacent second sub-panels 210 and between the second sub-panels 210 and the second frame 230 are spaced apart and connected by second connecting portions 220. Similar to the first connecting portion 120, when a second connecting portion 220 is cut off, the adjacent second sub-panels 210 or the second sub-panels 210 and the second frame 230 will be disconnected. On the other hand, if a second connecting portion 220 is kept connected, the adjacent second sub-panels 210 can still be connected to form an integrated structure through the second connecting portion 220. Based on this, the packaging component 10 is configured to be able to split the first connecting portion 120 and the second connecting portion 220 along a set trajectory to separate multiple sub-units 20, and to be able to split different first connecting portions 120 and second connecting portions 220 along different set trajectories to form at least two types of sub-units 20.

[0052] When the package assembly 10 further includes a second motherboard 200, in some embodiments of the present invention, referring to Figure 2 The multiple second connection parts 220 include at least two types, one of which is named the third sub-connection part 221, and the other is named the fourth sub-connection part 222. The third sub-connection part 221 is used to realize the mutual connection between adjacent second sub-boards 210 or between the second sub-board 210 and the second frame 230 along the first direction, and the fourth sub-connection part 222 is used to realize the mutual connection between adjacent second sub-boards 210 or between the second sub-board 210 and the second frame 230 along the second direction.

[0053] The second sub-board 210 is fixed in two directions perpendicular to each other by the third sub-connecting portion 221 and the fourth sub-connecting portion 222 , so that the second sub-board 210 can be firmly placed in the second motherboard 200 , effectively reducing deformation of the second sub-board 210 .

[0054] On the basis of the first embodiment, in some embodiments of the present invention, referring to Figure 3 The package assembly 10 further includes a first connection layer 400 positioned between the first sub-plate 110 and the first side of the corresponding chip 300. The first connection layer 400 includes a nanowire layer. In this embodiment, the first sub-plate 110 and the chip 300 are connected via the first connection layer 400 comprising nanowires. This increases the connection area between the chip 300 and the first sub-plate 110, thereby increasing the current flow capacity and facilitating heat transfer between the chip 300 and the first sub-plate 110. This reduces the amount of heat generated on top of the chip 300 and reduces creep and reaggregation of the metal layer on top of the chip 300. Furthermore, compared to traditional methods such as silver paste sintering, the pressure and temperature required for nanowire layer production are lower than those required for sintering, thereby reducing process requirements.

[0055] For example, as a way to connect the chip 300 and the first sub-board 110 through the first connection layer 400, a copper base layer can be formed on the source and gate regions on the upper surface of the chip 300, and on the connection regions corresponding to the source and gate regions on each first sub-board 110 in the first motherboard 100, and then a nanowire structure is continued to grow on the copper base layers of the two. Then, the nanowire structures of the two are made to fit together. Under certain pressure and temperature conditions, the nanowire structures are interconnected to realize the connection between the chip 300 and the first sub-board 110.

[0056] On the basis of the first embodiment, in some embodiments of the present invention, referring to Figure 3 The package assembly 10 further includes a second connection layer 500 located between the second daughter board 210 and the second side of the corresponding chip 300. The second connection layer 500 also includes a nanowire layer. For the same reasons, this embodiment has all the advantages of the aforementioned embodiments.

[0057] For example, as a way to connect the chip 300 and the second daughter board 210 through the second connection layer 500, a copper base layer can be formed on the drain area on the upper surface of the chip 300 and the connection area corresponding to the drain area on each second daughter board 210 in the second mother board 200, and then a nanowire structure is continued to grow on the copper base layers of the two. Then, the nanowire structures of the two are made to fit each other. Under certain pressure and temperature conditions, the nanowire structures are interconnected to realize the connection between the chip 300 and the second daughter board 210.

[0058] A second embodiment of the present invention provides a packaging module 30, which is configured as a subunit 20 separated from the packaging assembly 10 of the aforementioned embodiment. The packaging assembly 10 applicable to this embodiment also includes a molding layer covering the first motherboard 100 and the chips 300. After cutting the packaging assembly 10, the separated subunits 20 can directly form the packaging module 30, eliminating the need for further molding. For example, multiple chips 300 are connected to the first motherboard 100 and the second motherboard 200, respectively, and then the entire assembly is molded to obtain the packaging assembly 10 applicable to this embodiment.

[0059] by Figure 7Taking the figure as an example, it shows the smallest sub-unit separated from the packaging component 10 in this embodiment. The sub-unit 20 (packaging module 30) of this embodiment includes a first sub-board 110, a first connecting part 120, a chip 300 and a molding body 22. In other embodiments, the sub-unit 20 also includes a second sub-board 210 and a second connecting part 220. The molding body 22 is formed by cutting the aforementioned molding layer. As shown in the figure, the molding body 22 covers part of the surface of the first sub-board 110 and the first connecting part 120, and completely covers the chip 300. Specifically, the upper surface of the first sub-board 110 is exposed from the upper side of the molding body 22, the lower surface of the second sub-board 210 is exposed from the lower side of the molding body 22, and the cut sides of the first connecting part 120 and the second connecting part 220 are exposed from the side of the molding body, so that the first connecting part 120 and the second connecting part 220 can form a conductive terminal 21.

[0060] In other embodiments, the packaging module 30 includes subunits 20 separated from the packaging assembly 10 in the aforementioned embodiment. The packaging assembly 10 applicable to this embodiment does not include a molding layer covering the first motherboard 100 and the chip 300. After the packaging assembly 10 is cut, the separated subunits 20 need to be further molded to form the packaging module 30. For example, the packaging assembly 10 applicable to this embodiment can be obtained by connecting multiple chips 300 to the first motherboard 100 and the second motherboard 200 respectively.

[0061] by Figure 8 Taking the figure as an example, it shows the smallest sub-unit separated from the packaging component 10 in this embodiment. The sub-unit 20 includes a first sub-board 110, a first connecting portion 120, and a chip 300. In other embodiments, the sub-unit 20 also includes a second sub-board 210 and a second connecting portion 220. As shown in the figure, the sub-unit 20 in this embodiment is not covered with a molded body 22.

[0062] On the basis of the second embodiment, in some embodiments of the present invention, referring to Figure 7 The package module 30 includes a single chip 300 and a single first daughter board 110. In other embodiments, the package module 30 further includes a single second daughter board 210. This embodiment is the smallest module that can be formed by the package assembly 10.

[0063] On the basis of the second embodiment, in some embodiments of the present invention, referring to Figure 9The packaging module 30 includes a plurality of chips 300 and a plurality of first sub-boards 110 corresponding to the plurality of chips 300. In other embodiments, the packaging module 30 further includes a plurality of second sub-boards 210 corresponding to the plurality of chips 300. In this embodiment, the plurality of chips 300 are distributed along the first direction. At this time, the first connection portion 120 (i.e., the second sub-connection portion 122) of each first sub-board 110 in the second direction is cut off. The first connection portion 120 (i.e., the first sub-connection portion 121) of the first sub-board 110 located on the outside in the first direction is also cut off. The first connection portions 120 (i.e., the first sub-connection portion 121) in the first direction between adjacent first sub-boards 110 are retained, thereby allowing adjacent first sub-boards 110 to remain connected in the first direction.

[0064] In other embodiments, multiple chips 300 can also be distributed along the second direction. In this case, the first connection portion 120 (i.e., the first sub-connection portion 121) of each first sub-board 110 in the first direction is cut off, and the first connection portion 120 (i.e., the second sub-connection portion 122) of the first sub-board 110 in the second direction and located on the outside is also cut off. The first connection portions 120 (i.e., the second sub-connection portion 122) in the second direction between adjacent first sub-boards 110 are retained, so that adjacent first sub-boards 110 can remain connected in the second direction.

[0065] On the basis of the second embodiment, in some embodiments of the present invention, referring to Figure 10 The packaging module 30 includes multiple groups of chips 300 and multiple groups of first sub-boards 110 corresponding to the multiple groups of chips 300. The multiple groups of chips 300 are distributed along the first direction, and each group of chips 300 includes multiple chips 300 distributed along the second direction. Exemplarily, the packaging module 30 includes two groups of chips 300, and each group of chips 300 includes two chips 300, so that the packaging module 30 has a total of four chips 300.

[0066] In this embodiment, each first sub-board 110 is connected to the first sub-board 110 adjacent in the first direction and the first sub-board 110 adjacent in the second direction through the first connecting portion 120. Specifically, the first connecting portion 120 located on the outside of each chip 300 is cut off, and the first connecting portion 120 located on the inside is retained, so that each first sub-board 110 can remain connected in both the first direction and the second direction.

[0067] The third embodiment of the present invention further provides a method for preparing a packaging module 30, comprising the following steps: S100: preparing the packaging component 10 in the aforementioned embodiment; S200 divides the package component 10 into a plurality of sub-units 20 according to the set track. Figure 11The segmentation track includes a horizontal segmentation track A parallel to the first direction and a vertical segmentation track B parallel to the second direction. The horizontal segmentation track A passes through the gaps between the first sub-panels 110 and between the first sub-panel 110 and the first frame 130 along the first direction. The vertical segmentation track B passes through the gaps between the first sub-panels 110 and between the first sub-panel 110 and the first frame 130 along the second direction. By segmenting along the intersecting horizontal segmentation track A and vertical segmentation track B, multiple sub-units 20 can be separated. In addition, by changing different set tracks, different sub-units 20 can be formed, which is explained below through different examples.

[0068] On the basis of the third embodiment, in some embodiments of the present invention, referring to Figure 11 The aforementioned “segmentation of the package assembly 10 along a set track to separate a plurality of sub-units 20” specifically refers to segmenting the package assembly 10 along a first track to separate a plurality of first-type sub-units 20, wherein a single chip 300 is spaced between each transverse segmentation track A in the first track, and a single chip 300 is spaced between each longitudinal segmentation track B, and the first-type sub-unit 20 includes a single chip 300 and a single first sub-board 110, thereby being configured or further prepared as Figure 7 The package module 30 shown in FIG.

[0069] On the basis of the third embodiment, in some embodiments of the present invention, referring to Figure 12 The aforementioned "the package component 10 is divided along the set track to separate multiple sub-units 20" specifically means: the package component 10 is divided along the second track to separate multiple sub-units 20 of the second type, multiple chips 300 are separated between each horizontal dividing track A in the second track, and a single chip 300 is separated between each vertical dividing track B. The second type of sub-unit 20 includes multiple chips 300 and multiple first sub-boards 110 corresponding to the multiple chips 300. The multiple chips 300 are distributed along the second direction. Exemplarily, two chips 300 are separated between each horizontal dividing track A in the second track, so that it can be set or further prepared as Figure 9 The package module 30 shown in FIG.

[0070] On the basis of the third embodiment, in some embodiments of the present invention, the aforementioned "the packaging component 10 is divided according to the set track to separate multiple sub-units 20" specifically refers to: the packaging component 10 is divided according to the third track to separate multiple sub-units 20 of the third type, and each horizontal dividing track A in the third track is separated by a single chip 300, and each longitudinal dividing track B is separated by multiple chips 300. The third type of sub-unit 20 includes multiple chips 300 and multiple first sub-boards 110 corresponding to the multiple chips 300, and the multiple chips 300 are distributed along the first direction.

[0071] On the basis of the third embodiment, in some embodiments of the present invention, referring to Figure 13 The aforementioned "the packaging component 10 is divided according to the set track to separate multiple sub-units 20" specifically refers to: dividing the packaging component 10 according to the set track to separate multiple sub-units 20, including: dividing the packaging component 10 according to the fourth track to separate multiple sub-units 20 of the fourth type, multiple chips 300 are spaced between each horizontal dividing track A in the fourth track, and multiple chips 300 are spaced between each vertical dividing track B. The fourth type of sub-unit 20 includes multiple groups of chips 300 and multiple groups of first sub-boards 110 corresponding to the multiple groups of chips 300. The multiple groups of chips 300 are distributed along the first direction, and each group of chips 300 includes multiple chips 300 distributed along the second direction. Exemplarily, two chips 300 are spaced between each horizontal dividing track A in the fourth track, and two chips 300 are spaced between each vertical dividing track B, so that it can be set as or further prepared into Figure 10 The package module 30 shown in FIG.

[0072] While the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to the embodiments described above. Various modifications may be made within the scope of knowledge possessed by a person skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof may be combined with one another unless there is a conflict.

Claims

1. A packaging component, characterized in that include: a first motherboard made of a conductive material, the first motherboard including a plurality of groups of first daughter boards, the plurality of groups of first daughter boards being spaced apart along a first direction, each group of first daughter boards including a plurality of first daughter boards spaced apart along a second direction, the first direction being perpendicular to the second direction, the first motherboard further including a plurality of first connecting portions, each first daughter board being connected to a first daughter board adjacent to the first direction and to a first daughter board adjacent to the second direction via the first connecting portions; a plurality of chips, arranged corresponding to each of the first sub-boards, wherein a first side of each of the chips is electrically connected to the corresponding first sub-board; In which, the packaging component is configured to be able to split the first connecting part along a set track to separate multiple sub-units, and at least part of the split first connecting part forms the conductive terminal of the sub-unit, and the packaging component is also configured to be able to split different first connecting parts along different set tracks to form at least two sub-units, and the number of chips in different sub-units is different.

2. The packaging assembly according to claim 1, wherein: Each of the first sub-plates has a source conductive portion and a gate conductive portion that are spaced apart from each other. The plurality of first connecting portions include a first sub-connecting portion and a second sub-connecting portion. The source conductive portion is connected to the first sub-plate adjacent to the first direction via the first sub-connecting portion, and is connected to the first sub-plate adjacent to the second direction via the second sub-connecting portion. The gate conductive portion is connected to the first sub-plate adjacent to the first direction via the first sub-connecting portion, and is connected to the first sub-plate adjacent to the second direction via the second sub-connecting portion. The chip includes a source region and a gate region located on the first side. The source region is electrically connected to the source conductive portion corresponding to the first sub-board, and the gate region is electrically connected to the gate conductive portion of the same first sub-board.

3. The packaging assembly according to claim 2, wherein: The source conductive portion is connected to the source conductive portion of the first sub-plate adjacent in the first direction through the first sub-connection portion, and is connected to the gate conductive portion of the first sub-plate adjacent in the second direction through the second sub-connection portion.

4. The packaging assembly according to claim 2, wherein: The gate conductive portion is connected to the source conductive portion of the first sub-plate adjacent in the first direction through the first sub-connection portion, and the gate conductive portion is connected to the source conductive portion of the first sub-plate adjacent in the second direction through the second sub-connection portion.

5. The packaging assembly according to claim 4, wherein: Each of the gate conductive portions is provided with the first sub-connection portion on both sides opposite to each other along the first direction, wherein one side of the gate conductive portion is connected to the source conductive portion of one of the first sub-plates adjacent in the first direction through the first sub-connection portion, and the other side is connected to the gate conductive portion of another first sub-plate adjacent in the first direction through the first sub-connection portion.

6. The packaging assembly according to claim 1, wherein: The package assembly further includes a second motherboard, the second motherboard including a plurality of groups of second daughter boards, the plurality of groups of second daughter boards being spaced apart along the first direction, each group of second daughter boards including a plurality of second daughter boards spaced apart along the second direction, the second motherboard further including a plurality of second connecting portions, each second daughter board being connected to the second daughter board adjacent to the first direction and the second direction via the second connecting portions; Each of the chips includes a drain region located on a second side, the drain region is electrically connected to the corresponding second sub-board, and the second side is arranged opposite to the first side; The packaging component is configured to be able to split the first connection portion and the second connection portion along the set track to separate multiple sub-units, and to be able to split different first connection portions and second connection portions along different set tracks to form at least two sub-units.

7. The packaging assembly according to claim 5, wherein: The plurality of second connection parts include a third sub-connection part and a fourth sub-connection part, and the second sub-board is connected to the second sub-board adjacent to the first direction through the third sub-connection part, and is connected to the second sub-board adjacent to the second direction through the fourth sub-connection part.

8. The packaging assembly according to claim 1, wherein: The package assembly further includes a first connection layer located between the first daughter board and the first side of the corresponding chip, wherein the first connection layer includes a nanowire layer.

9. Encapsulation module, characterized in that, The package assembly comprises or is configured as the subunit separated from the package assembly according to any one of claims 1 to 8.

10. The packaging module according to claim 9, characterized in that The packaging module includes a single chip and a single first daughter board; Alternatively, the packaging module includes a plurality of the chips and a plurality of first sub-boards corresponding to the plurality of the chips, the plurality of chips are distributed along the first direction, and each first sub-board is connected to the first sub-board adjacent to the first direction via the first connecting portion; or, the plurality of chips are distributed along the second direction, and each first sub-board is connected to the first sub-board adjacent to the second direction via the first connecting portion; Alternatively, the packaging module includes multiple groups of chips and multiple groups of first sub-boards corresponding to the multiple groups of chips, the multiple groups of chips are distributed along the first direction, each group of chips contains multiple chips distributed along the second direction, and each first sub-board is connected to the first sub-board adjacent to the first direction and the first sub-board adjacent to the second direction through the first connecting part.

11. A method for preparing a package module, comprising the following steps: Preparing a package assembly according to any one of claims 1 to 9; The packaging component is divided according to a set track to separate the plurality of sub-units, and the dividing track includes a transverse dividing track parallel to the first direction and a longitudinal dividing track parallel to the second direction.

12. The method for preparing a packaging module according to claim 11, wherein: The package assembly is divided according to a set track to separate the plurality of sub-units, comprising: dividing the package assembly according to a first track to separate a plurality of first-type sub-units, wherein a single chip is separated between each of the transverse dividing tracks in the first track, and a single chip is separated between each of the longitudinal dividing tracks, and the first-type sub-unit includes a single chip and a single first sub-board; Alternatively, dividing the package assembly according to a set track to separate the plurality of sub-units includes: dividing the package assembly according to a second track to separate a plurality of second-type sub-units, wherein a plurality of chips are spaced between each of the transverse dividing tracks in the second track, and a single chip is spaced between each of the longitudinal dividing tracks, the second-type sub-units including a plurality of chips and a plurality of the first sub-boards corresponding to the plurality of chips, and the plurality of chips are distributed along the second direction; Alternatively, dividing the package assembly according to a set track to separate the plurality of sub-units includes: dividing the package assembly according to a third track to separate a plurality of sub-units of a third type, wherein a single chip is separated between each of the transverse dividing tracks in the third track, and a plurality of chips are separated between each of the longitudinal dividing tracks, wherein the third type of sub-units includes a plurality of the chips and a plurality of the first sub-boards corresponding to the plurality of the chips, and the plurality of chips are distributed along the first direction; Alternatively, the packaging component is divided according to a set track to separate a plurality of the sub-units, including: dividing the packaging component according to a fourth track to separate a plurality of fourth-type sub-units, a plurality of the chips are spaced between each of the horizontal dividing tracks in the fourth track, and a plurality of the chips are spaced between each of the vertical dividing tracks, the fourth-type sub-units include multiple groups of the chips and multiple groups of the first sub-boards corresponding to the multiple groups of chips, the multiple groups of chips are distributed along the first direction, and each group of chips includes multiple chips distributed along the second direction.

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