A bidirectional surge protection circuit

Abstract

The application provides a bidirectional surge protection circuit, and relates to the technical field of surge protection, which comprises a surge detection circuit, a driving circuit and a surge discharge circuit connected between a first terminal and a second terminal; when a surge in any direction occurs between the first terminal and the second terminal, the surge detection circuit detects the surge current to generate a starting signal, the driving circuit receives the starting signal and amplifies it into a driving signal, and the surge discharge circuit is turned on by the driving signal to discharge the surge current. The beneficial effect is that the surge detection circuit of the application only flows through a very small current. Therefore, the clamping voltage VC of the application does not linearly increase with the increase of Ipp as in the traditional TVS, thereby realizing a smooth clamping voltage. The dynamic resistance of the circuit of the application is extremely low, avoiding the problem that the traditional TVS must sacrifice other parameters in order to reduce the dynamic resistance, and realizing a low clamping voltage while maintaining the optimization of other parameters. DNY ​

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of surge protection, and particularly relates to a bidirectional surge protection circuit. BACKGROUND

[0002] With the development of charging technology, high voltage and large current become the main features of fast charging technology. In daily application, some non-standard operations may cause the output voltage of the VBUS port to be abnormal. If the abnormal voltage is higher than the tolerance value of the internal chip of the device, the device will be damaged and cannot be recovered. Therefore, a bidirectional TVS that can prevent large surges is connected in parallel to the VBUS port to protect the subsequent sensitive elements in the design. The basic structure of the traditional TVS is composed of a PN junction, Figure 1 TVSV BR shows the I-V characteristic in the forward direction.

[0003] The reverse operating voltage (V RWM ) is also called the operating voltage, which describes the voltage level at which the TVS has no significant impact on the protected circuit. In system design, V RWM is generally higher than the upper limit of the system operating voltage to prevent the system from generating leakage through the clamping TVS during normal operation. The breakdown voltage (V BR ) defines the reverse voltage at which the TVS starts to actively conduct current to clamp the transient event. As more current flows through the TVS, the voltage across the TVS increases linearly due to the existence of the dynamic resistance (R DNY ). During the transient event, the clamping voltage V C on the TVS is composed of the product of the corresponding surge current (I PP ) and the dynamic resistance R DNY , plus the breakdown voltage V BR of the TVS, and their relationship is shown in Equation 1.

[0004] V C =V BR +I PP *R DNY (1)

[0005] The R DNY of the traditional surge clamping TVS is a fixed value, and V C directly depends on the I PP current level. The physical properties of silicon and the junction area of the TVS limit the R DNY of the TVS. Even if the area of the TVS is very large, the R DNY of the 8 / 20us surge test can reach hundreds of milliohms. Therefore, compared with the operating voltage V RWM , the TVS diode usually has a higher clamping voltage V CTherefore, the designer must take additional steps to design a robust system for the subsequent sensitive components that need protection. One approach is to over-design the downstream circuit to withstand high surge clamp voltage, but it results in higher system cost, higher power consumption and increased IC size. The second option is to use a much lower TVS device, but it has to compromise other parameters such as higher capacitance, higher leakage and larger TVS package size. DNY SUMMARY

[0006] In view of the problems in the prior art, the present application provides a bidirectional surge protection circuit, comprising a surge detection circuit, a driving circuit and a surge discharge circuit connected between a first terminal and a second terminal; a surge detection end of the surge detection circuit is connected to the first terminal and the second terminal, a start signal sending end of the surge detection circuit is connected to a start signal receiving end of the driving circuit, a driving signal sending end of the driving circuit is connected to a driving signal receiving end of the surge discharge circuit; when a surge occurs in any direction between the first terminal and the second terminal, the surge detection circuit detects the surge current and amplifies several times to generate a start signal, the driving circuit receives the start signal and amplifies it into a driving signal, and the surge discharge circuit is turned on by the driving signal to discharge the surge current.

[0007] Preferably, the start signal receiving end of the driving circuit comprises a first start signal receiving end and a second start signal receiving end; the surge detection circuit comprises a first current mirror, a first terminal and a second terminal of the first current mirror are connected to the first terminal; a second current mirror, a first terminal and a second terminal of the second current mirror are connected to the second terminal; a forward voltage stabilizing tube string, a first resistor and a reverse voltage stabilizing tube string are connected in series between a third terminal of the first current mirror and a third terminal of the second current mirror; a second resistor is connected in series between a fourth terminal of the first current mirror and a fourth terminal of the second current mirror; the input end and the second start signal receiving end of the driving circuit are connected between the fourth terminal of the first current mirror and the second resistor; the output end and the first start signal receiving end of the driving circuit are connected between the fourth terminal of the second current mirror and the second resistor.

[0008] ​Preferably, the driving circuit comprises: a first PMOS tube, a source of the first PMOS tube is connected to a fourth terminal of the first current mirror, a gate of the first PMOS tube is connected to a fourth terminal of the second current mirror; a second PMOS tube, a source of the second PMOS tube is connected to a fourth terminal of the second current mirror, a gate of the second PMOS tube is connected to a fourth terminal of the first current mirror; a third resistor and a fourth resistor, which are connected in series between drains of the first PMOS tube and the second PMOS tube, a connection point of the third resistor and the fourth resistor is connected to an anode of a first zener diode and an anode of a second zener diode respectively, a cathode of the first zener diode is connected to a drain of the first PMOS tube, a cathode of the second zener diode is connected to a drain of the second PMOS tube; the connection point of the third resistor and the fourth resistor is connected to a driving signal receiving terminal of the surge discharge circuit as the driving signal output terminal.

[0009] Preferably, the driving circuit comprises: a third NMOS tube, a drain of the third NMOS tube is connected to the first terminal, a gate of the third NMOS tube is connected to a fourth terminal of the first current mirror; a fourth NMOS tube, a drain of the fourth NMOS tube is connected to the second terminal, a gate of the fourth NMOS tube is connected to a fourth terminal of the second current mirror; a fifth resistor and a sixth resistor, which are connected in series between sources of the third NMOS tube and the fourth NMOS tube, a connection point of the fifth resistor and the sixth resistor is connected to an anode of a third zener diode and an anode of a fourth zener diode respectively, a cathode of the third zener diode is connected to a source of the third NMOS tube, a cathode of the fourth zener diode is connected to a source of the fourth NMOS tube; the connection point of the fifth resistor and the sixth resistor is connected to a driving signal receiving terminal of the surge discharge circuit as the driving signal output terminal.

[0010] Preferably, the surge detection circuit comprises: a seventh resistor, a forward zener diode string, a reverse zener diode string and an eighth resistor, which are connected in series between the first terminal and the second terminal; or the connection sequence from the first terminal to the second terminal is: the seventh resistor, the forward zener diode string, the reverse zener diode string and the eighth resistor; or the connection sequence from the first terminal to the second terminal is: the forward zener diode string, the seventh resistor, the eighth resistor and the reverse zener diode string.

[0011] Preferably, the driving circuit comprises: a third PMOS tube, a source of the third PMOS tube is connected to one end of the seventh resistor close to the first terminal, a gate of the third PMOS tube is connected to one end of the seventh resistor close to the second terminal; a fourth PMOS tube, a source of the fourth PMOS tube is connected to one end of the eighth resistor close to the second terminal, a gate of the fourth PMOS tube is connected to one end of the eighth resistor close to the first terminal, the seventh resistor and the eighth resistor are connected in series between drains of the third PMOS tube and the fourth PMOS tube, connection points of the seventh resistor and the eighth resistor are connected to anodes of the third zener tube and the fourth zener tube respectively, a cathode of the third zener tube is connected to the drain of the third PMOS tube, a cathode of the fourth zener tube is connected to the drain of the fourth PMOS tube; the connection points of the seventh resistor and the eighth resistor are connected to the driving signal receiving end of the surge discharge circuit as the driving signal output end.

[0012] Preferably, the surge discharge circuit comprises: a first NMOS tube, a drain of the first NMOS tube is connected to the first terminal, a gate of the first NMOS tube is connected to the driving signal output end of the driving circuit; a second NMOS tube, a drain of the second NMOS tube is connected to the second terminal, a gate of the second NMOS tube is connected to the driving signal output end of the driving circuit; a source of the first NMOS tube and a source of the second NMOS tube are connected.

[0013] Preferably, the first current mirror and the second current mirror each comprise a first current mirror PMOS tube and a second current mirror PMOS tube; a source of the first current mirror PMOS tube is the first wiring terminal, a source of the second current mirror PMOS tube is the second wiring terminal, a drain of the first current mirror PMOS tube is the third wiring terminal, a drain of the second current mirror PMOS tube is the fourth wiring terminal; a gate of the first current mirror PMOS tube is connected to a gate of the second current mirror PMOS tube and the drain of the first current mirror PMOS tube.

[0014] The above technical solution has the following advantages or beneficial effects:

[0015] 1. The surge clamping voltage is determined by the surge detection circuit, and the surge detection circuit of the present application only flows a very small current. Therefore, the clamping voltage VC of the present application will not linearly increase with the increase of Ipp as in the traditional TVS, thereby realizing a smooth clamping voltage and providing more effective protection for the subsequent IC.

[0016] 2. The surge discharge circuit is driven by an independent driving circuit, which makes the dynamic resistance (R DNY) is extremely low, as it is mainly determined by the on-resistance of the discharge circuit. This avoids the problem of traditional TVSs having to sacrifice other parameters in order to reduce R DNY and other parameters are optimized while achieving a low clamping voltage. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 I-V characteristic diagram of TVS VBR direction;

[0018] Figure 2 Circuit structure diagram of the bidirectional surge protection circuit in embodiment one;

[0019] Figure 3 、 Figure 4 Current path diagram of the bidirectional surge protection circuit in embodiment one when different direction surges occur;

[0020] Figure 5 Clamping comparison diagram of the bidirectional surge protection circuit of the present application and traditional TVS for symmetric surge test results;

[0021] Figure 6 Clamping comparison diagram of the bidirectional surge protection circuit of the present application and traditional TVS for asymmetric surge test results;

[0022] Figure 7 Circuit structure diagram of the bidirectional surge protection circuit in embodiment two;

[0023] Figure 8 、 Figure 9 Current path diagram of the bidirectional surge protection circuit in embodiment two when different direction surges occur;

[0024] Figure 10 Circuit structure diagram of the bidirectional surge protection circuit in embodiment three;

[0025] Figure 11 Current path diagram of the bidirectional surge protection circuit in embodiment three when surges occur;

[0026] Figure 12 Circuit structure diagram of the bidirectional surge protection circuit in embodiment four;

[0027] Figure 13 Current path diagram of the bidirectional surge protection circuit in embodiment four when surges occur. DETAILED DESCRIPTION

[0028] The present application will be described in detail below with reference to the accompanying drawings and specific embodiments. The present application is not limited to this embodiment, and other embodiments that meet the spirit of the present application can also fall within the scope of the present application.

[0029] In the preferred embodiment of the present application, based on the above-mentioned problems existing in the prior art, a bidirectional surge protection circuit is provided, which comprises a surge detection circuit, a driving circuit and a surge discharge circuit connected between a first terminal and a second terminal; a surge detection end of the surge detection circuit is connected to the first terminal and the second terminal, a start signal sending end of the surge detection circuit is connected to a start signal receiving end of the driving circuit, and a driving signal sending end of the driving circuit is connected to a driving signal receiving end of the surge discharge circuit; when a surge in any direction occurs between the first terminal and the second terminal, the surge detection circuit detects the surge current and amplifies it by several times to generate a start signal, the driving circuit receives the start signal and amplifies it into a driving signal, and the surge discharge circuit is turned on by the driving signal to discharge the surge current.

[0030] Specifically, the bidirectional surge protection circuit provided in the embodiment solves the technical problems existing in the background art by introducing the surge detection circuit, the driving circuit and the surge discharge circuit. The working principle is as follows: surge detection and current amplification: the surge detection circuit includes a string of zener diodes, and when a surge in any direction occurs between the first terminal and the second terminal, the surge detection circuit detects the surge current. Unlike traditional TVS, this circuit only allows a very small current (about 0.1-1 mA) to flow through the string of zener diodes, and uses a PMOS current mirror to amplify this small current by several times, thereby generating a start signal.

[0031] Dynamic adjustment and driving: after receiving the start signal, the driving circuit amplifies it into a driving signal. This driving signal is dynamically adjusted according to the size of the current flowing through it, and its function is to control the gate voltage of the surge discharge circuit, thereby opening the discharge path.

[0032] Low-impedance discharge: once the surge discharge circuit is turned on by the driving signal, the main surge current will be discharged to the ground through this extremely low-impedance path.

[0033] Through this design, the patent circuit effectively solves the problems in the background art:

[0034] 1. Stable clamping voltage is achieved: the present application separates the functions of surge detection and current discharge. The surge clamping voltage is determined by the zener diodes in the surge detection circuit, and only a very small current flows through this part. Therefore, the clamping voltage VC is equal to the voltage on one side of the zener diodes, and does not increase linearly with Ipp as in traditional TVS, thereby achieving a stable clamping voltage and providing more effective protection for subsequent ICs.

[0035] Breaks through the dilemma of design trade-off: the core idea of this circuit is to discharge the large surge current through a low-impedance discharge path, and the conduction of this path is controlled by an independent driving circuit. This makes the dynamic resistance (R DNY) is extremely low, as it is mainly determined by the on-resistance of the discharge circuit. This avoids the problem of traditional TVSs having to sacrifice other parameters in order to reduce R DNY The low clamping voltage is achieved while other parameters are optimized.

[0036] Four embodiments of the bidirectional surge protection circuit are given to illustrate the specific circuit structure and implementation principle.

[0037] Embodiment one:

[0038] In this embodiment, the start signal receiving end of the drive circuit includes a first start signal receiving end and a second start signal receiving end; the surge detection circuit includes: a first current mirror CM1, the first terminal of the first current mirror CM1 is connected to the first terminal; a second current mirror CM2, the first terminal of the second current mirror CM2 is connected to the second terminal; a forward voltage regulator string ZF1-ZFN, a first resistor R1 and a reverse voltage regulator string ZB1-ZBN are connected in series between the third terminal of the first current mirror CM1 and the third terminal of the second current mirror CM2; a second resistor R2 is connected in series between the fourth terminal of the first current mirror CM1 and the fourth terminal of the second current mirror CM2; the input end of the drive circuit and the second start signal receiving end are connected between the fourth terminal of the first current mirror CM1 and the second resistor R2; the output end of the drive circuit and the first start signal receiving end are connected between the fourth terminal of the second current mirror CM2 and the second resistor R2.

[0039] In this embodiment, the drive circuit includes: a first PMOS tube PM1, the source of the first PMOS tube PM1 is connected to the fourth terminal of the first current mirror CM1, the gate of the first PMOS tube PM1 is connected to the fourth terminal of the second current mirror CM2; a second PMOS tube PM2, the source of the second PMOS tube PM2 is connected to the fourth terminal of the second current mirror CM2, the gate of the second PMOS tube PM2 is connected to the fourth terminal of the first current mirror CM1; a third resistor R3 and a fourth resistor R4 are connected in series between the drain of the first PMOS tube PM1 and the drain of the second PMOS tube PM2, the connection point of the third resistor R3 and the fourth resistor R4 is connected to the anode of the first voltage regulator Zp and the anode of the second voltage regulator Zm respectively, the cathode of the first voltage regulator Zp is connected to the drain of the first PMOS tube PM1, the cathode of the second voltage regulator Zm is connected to the drain of the second PMOS tube PM2; the connection point of the third resistor R3 and the fourth resistor R4 is connected to the drive signal receiving end of the surge discharge circuit as the drive signal output end.

[0040] In the embodiment, the surge discharge circuit comprises a first NMOS tube NM1, a drain of the first NMOS tube NM1 is connected to the first terminal, a gate of the first NMOS tube NM1 is connected to a driving signal output end of the driving circuit; a second NMOS tube NM2, a drain of the second NMOS tube is connected to the second terminal, a gate of the second NMOS tube NM2 is connected to the driving signal output end of the driving circuit; a source of the first NMOS tube NM1 and a source of the second NMOS tube NM2 are connected.

[0041] Specifically, the specific circuit structure of the bidirectional surge protection circuit in the embodiment is as shown in Figure 2 The whole is composed of a surge detection unit including a 1:X ratio MOS current mirror and forward and reverse Zener diode strings ZB1~ZBn, ZF1~ZFn, and a first resistor R1 and a second resistor R2, a driving circuit composed of a first PMOS tube PM1, a second PMOS tube PM2, and a third resistor R3, a fourth resistor R4, and a first Zener diode Zp and a second Zener diode Zm, and a surge discharge circuit composed of a first NMOS tube NM1 and a second NMOS tube NM2 with a large area.

[0042] There is a voltage difference between the first terminal and the second terminal, in the embodiment, a high potential is represented by Vin, and a low potential is represented by GND, since the present application provides a bidirectional surge protection circuit, it is suitable for the case that the voltage of the first terminal is higher than the first terminal and the case that the voltage of the second terminal is higher than the first terminal, in the embodiment, the first terminal is taken as the high potential Vin, and the second terminal is taken as the low potential GND for example.

[0043] As shown in Figure 3 The figure contains the flow path of the current in the bidirectional surge protection circuit. When a surge event occurs between Vin and GND, the bus voltage is greater than the breakdown voltage of the Zener diode string Z B1 ~Z Bn , the surge detection unit is started, at this time, the voltage flowing through the Zener diode string Z B1 ~Z Bn and Z F1 ~Z Fn along path 1 from Vin to GND; the first current mirror CM1 amplifies the current on the side of the first PMOS tube PM1 by X times, the amplified current along path 2 from Vin to GND; under the action of the second resistor R2, the first PMOS tube PM1 of the driving unit is turned on, the current from Vin passes through the first PMOS tube PM1, the first Zener diode Zp, the fourth resistor R4 and the body diode of the second PMOS tube PM2 to GND, as shown in Figure 3The voltage drop generated by the fourth resistor R4 can open the first NMOS transistor NM1 of the discharge circuit, so that the subsequent large inrush current is discharged from Vin along the body diode of the first NMOS transistor NM1 and the second NMOS transistor NM2, as shown in path 4 of FIG. 2. Figure 3 The voltage drop generated by the fourth resistor R4 can open the first NMOS transistor NM1 of the discharge circuit, so that the subsequent large inrush current is discharged from Vin along the body diode of the first NMOS transistor NM1 and the second NMOS transistor NM2, as shown in path 4 of FIG. 2.

[0044] Similarly, as shown in path 4 of FIG. 2, the current flow path in the bidirectional surge protection circuit is included. Figure 4 Figure 3

[0045] When the inrush event occurs between GND and Vin, the bus voltage is greater than the breakdown voltage of the Zener tube string Z F1 ~Z Fn , triggering the surge detection unit to start. Under the action of the second resistor R2, the second PMOS transistor PM2 of the driving unit is opened, and the current flows from GND through PM2, the Zener tube Zm, the resistor R3 and the body diode of PM1 to Vin, so that the second NMOS transistor NM2 of the surge discharge circuit is opened, and the subsequent large inrush current is discharged along the body diode of the second NMOS transistor NM2 and NM1.

[0046] The surge detection unit is mainly responsible for the detection of the inrush event and the voltage clamping effect in the surge discharge process, so the 1:X current mirror (two PMOS, referred to as PMOS current mirror) and the PMOS driving unit (the driving unit in this embodiment is composed of PMOS, referred to as PMOS driving circuit) and the first NMOS transistor NM1 and the second NMOS transistor NM2 of the surge discharge circuit are introduced in this application to realize the dynamic regulation of current in the surge discharge process. The final effect of this dynamic regulation is that the current is mainly discharged to the ground through the path 4 of the discharge circuit with the smallest on-resistance, and only 0.1-1 mA of current flows through the Zener tube part of path 1 for surge detection and clamping.

[0047] In addition, the PMOS current mirror functions to amplify the current on one side of the Zener tube of path 1 in proportion, the voltage drop generated by the current of path 2 on the second resistor R2 opens the PMOS driving unit, and the driving unit dynamically adjusts the gate voltage of the first NMOS transistor NM1 and the second NMOS transistor NM2 in the surge discharge circuit according to the size of the current flowing through path 3, so as to ensure that most of the current flows through path 4 from the surge discharge circuit when discharging the inrush current. With the increase of the inrush current (Ipp), the clamping voltage (Vc) is equal to the voltage on one side of the Zener tube, and since the current on one side of the Zener tube of path 1 is small, a stable clamping voltage state is achieved. Compared with the traditional TVS, the clamping voltage (Vc) linearly increases with the increase of Ipp, and the application can achieve a smooth clamping voltage (Vc) to effectively protect the subsequent IC. ​​

[0048] Further, the present application relates to the breakdown voltage BV of single voltage regulator 1uA about 5.5V~6.5V, VF about 0.5~0.8V; in addition, the voltage regulator can be used with diode and other devices with directional breakdown voltage; the resistance of the first resistor R1 is 500ohm~10Kohm; the resistance of the second resistor R2 is about 500ohm~10Kohm; the resistance of the third resistor R3 is about 10Kohm~200Kohm; the resistance of the fourth resistor R4 is about 500ohm~10Kohm; the breakdown voltage BVDS of the first PMOS tube PM1 and the second PMOS tube PM2 at 1uA is 15~200V, and the threshold voltage Vth is-0.6V~-1.2V; the breakdown voltage BVDS of the first NMOS tube NM1 and the second NMOS tube NM2 is 30V~200V, and the threshold voltage Vth is 0.6V~1.2V.

[0049] The surge protection circuit mentioned in the present application has the advantage of stable clamping voltage compared with the traditional TVS. The reason is that the PMOS current mirror and the driving circuit ensure that almost no current flows through the series side of the voltage regulator, and the large current is mainly discharged through the first NMOS tube NM1 and the second NMOS tube NM2 in the surge discharge circuit. NM1 and NM2 both use low on-resistance MOS with on-resistance of about 5~10mΩ, which ensures that the clamping voltage hardly changes with the increase of surge current Ipp.

[0050] The bidirectional surge protection circuit in the embodiment is tested by surge, and compared with the traditional TVS as shown in the figure Figure 5 It can be shown by comparison that the protection scheme proposed in the present application has more stable clamping than the traditional TVS, so that the safety window of the design can be reduced when designing the protected unit, thereby saving the design area.

[0051] By designing the number of forward and reverse voltage regulator strings ZB1~ZBn and ZF1~ZFn, the present application can realize the protection requirement of forward and reverse asymmetric trigger voltage, as shown in the figure Figure 6 The present application realizes a clamping voltage of 30V in the forward direction and a clamping voltage of-15V in the reverse direction, so the present application can be applied to various bidirectional protection application fields.

[0052] Embodiment two:

[0053] In this embodiment, the start signal receiving end of the driving circuit includes a first start signal receiving end and a second start signal receiving end; the surge detection circuit includes: a first current mirror CM1, the first and second terminals of the first current mirror CM1 being connected to a first terminal; a second current mirror CM2, the first and second terminals of the second current mirror being connected to a second terminal; a series of forward Zener diodes ZF1~ZFn, a first resistor R1, and a series of reverse Zener diodes ZB1~ZBn are connected in series between the third terminal of the first current mirror CM1 and the third terminal of the second current mirror CM2; a second resistor R2 is connected in series between the fourth terminal of the first current mirror CM1 and the fourth terminal of the second current mirror CM2; the input terminal of the driving circuit and the second start signal receiving end are connected between the fourth terminal of the first current mirror CM1 and the second resistor R2; the output terminal of the driving circuit and the first start signal receiving end are connected between the fourth terminal of the second current mirror CM2 and the second resistor R2.

[0054] In this embodiment, the driving circuit includes: a third NMOS transistor NM3, the drain of which is connected to the first terminal, and the gate of which is connected to the fourth terminal of the first current mirror CM1; a fourth NMOS transistor NM4, the drain of which is connected to the second terminal, and the gate of which is connected to the fourth terminal of the second current mirror CM2; a fifth resistor R5 and a sixth resistor R6, connected in series between the sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4, the connection point of the fifth resistor R5 and the sixth resistor R6 being connected to the anodes of the third Zener diode Zp and the fourth Zener diode Zm, respectively, the cathode of the third Zener diode Zp being connected to the source of the third NMOS transistor NM3, and the cathode of the fourth Zener diode Zm being connected to the source of the fourth NMOS transistor NM4; the connection point of the fifth resistor R5 and the sixth resistor R6 serving as the driving signal output terminal connected to the driving signal receiving terminal of the surge discharge circuit.

[0055] In this embodiment, the surge discharge circuit includes: a first NMOS transistor NM1, the drain of the first NMOS transistor NM1 is connected to a first terminal, and the gate of the first NMOS transistor NM1 is connected to the drive signal output terminal of the drive circuit; a second NMOS transistor NM2, the drain of the second NMOS transistor is connected to a second terminal, and the gate of the second NMOS transistor NM2 is connected to the drive signal output terminal of the drive circuit; the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are connected.

[0056] Specifically, such as Figure 7 As shown, the surge detection circuit and surge discharge circuit in this embodiment are the same as those in Embodiment 1. The difference between this embodiment and Embodiment 1 is that the MOS transistor in the driving circuit in Embodiment 1 is a PMOS transistor, while the MOS transistor in the driving circuit in this embodiment is an NMOS transistor, and the wiring position is also changed.

[0057] In this embodiment, the first terminal is also taken as high potential Vin, and the second terminal is taken as low potential GND as an example for illustration.

[0058] As shown in Figure 8 , the figure contains the flow path of current in the bidirectional surge protection circuit. When a surge event occurs between Vin and GND, the bus voltage is greater than the breakdown voltage of the Zener diode string ZB1~ZBn, the surge detection unit is started, at this time the voltage flowing through the Zener diode string ZB1~ZBn and ZF1~ZFn along path 1 from Vin to GND; the function of the first current mirror CM1 is to amplify the current on the side of the first PMOS PM1 by X times, and the amplified current along path 2 from Vin to GND; under the action of the second resistor R2, the third NMOS NM3 of the drive unit is turned on, and the current flows from Vin through the third NMOS NM3, the first Zener diode Zp, the sixth resistor R6 and the body diode of the fourth NMOS NM4 to GND, as shown in Figure 8 path 3; the voltage drop generated by the sixth resistor R6 can turn on the first NMOS NM1 of the discharge circuit, so that the subsequent large surge current is discharged from Vin along the body diode of the first NMOS NM1 and the second NMOS NM2, as shown in Figure 8 path 4.

[0059] Similarly, as shown in Figure 9 , the figure contains the flow path of current in the bidirectional surge protection circuit, which is Figure 8 symmetrically reversed.

[0060] When a surge event occurs between GND and Vin, the bus voltage is greater than the breakdown voltage of the Zener diode string ZF1~ZFn, triggering the surge detection unit to start, under the action of the second resistor R2, the fourth NMOS NM4 of the drive unit is turned on, and the current flows from GND through the fourth NMOS NM4, the Zener diode Zm, the fifth resistor R5 and the body diode of the third NMOS NM3 to Vin, so that the second NMOS NM2 of the surge discharge circuit is turned on, and the subsequent large surge current is discharged along the body diode of the second NMOS NM2 and NM1.

[0061] The implementation effect in this embodiment is consistent with the bidirectional surge protection circuit in embodiment one, the difference is that since the NMOS has smaller on-resistance than the PMOS, the drive circuit composed of NMOS in this embodiment can further optimize the area of the drive circuit.

[0062] For the first current mirror and the second current mirror, the first current mirror PMOS tube and the second current mirror PMOS tube are included; the source of the first current mirror PMOS tube is used as the first terminal, the source of the second current mirror PMOS tube is used as the second terminal, the drain of the first current mirror PMOS tube is used as the third terminal, and the drain of the second current mirror PMOS tube is used as the fourth terminal; the gate of the first current mirror PMOS tube is connected with the gate of the second current mirror PMOS tube and the drain of the first current mirror PMOS tube.

[0063] Embodiment three:

[0064] In this embodiment, the surge detection circuit includes a seventh resistor R7, a forward voltage regulator string Z F1 ~Z Fn , a reverse voltage regulator string Z B1 ~Z Bn and an eighth resistor R8 connected in series between the first terminal and the second terminal; the connection sequence from the first terminal to the second terminal is: the seventh resistor R7, the forward voltage regulator string Z F1 ~Z Fn , the reverse voltage regulator string Z B1 ~Z Bn and the eighth resistor R8; the connection point of the seventh resistor R7 and the forward voltage regulator string Z F1 ~Z Fn connects the first start signal receiving end of the driving circuit, and the connection point of the eighth resistor R8 and the reverse voltage regulator string Z B1 ~Z Bn connects the second start signal receiving end of the driving circuit; in this embodiment, the driving circuit includes: a third PMOS tube PM3, the source of the third PMOS tube PM3 is connected to one end of the seventh resistor R7 close to the first terminal, and the gate of the third PMOS tube PM3 is connected to one end of the seventh resistor R7 close to the second terminal; a fourth PMOS tube PM4, the source of the fourth PMOS tube PM4 is connected to one end of the eighth resistor R8 close to the second terminal, and the gate of the fourth PMOS tube PM4 is connected to one end of the eighth resistor R8 close to the first terminal; a ninth resistor R9 and a tenth resistor R10 connected in series between the drains of the third PMOS tube PM3 and the fourth PMOS tube PM4, the connection point of the ninth resistor R9 and the tenth resistor R10 is respectively connected to the anode of the third voltage regulator Zp and the fourth voltage regulator Zm, the cathode of the third voltage regulator Zp is connected to the drain of the third PMOS tube PM3, and the cathode of the fourth voltage regulator Zm is connected to the drain of the fourth PMOS tube PM4; the connection point of the ninth resistor R9 and the tenth resistor R10 is used as the driving signal output end to connect the driving signal receiving end of the surge discharge circuit.

[0065] In the embodiment, the surge discharge circuit comprises a first NMOS tube NM1, a drain of the first NMOS tube NM1 is connected to the first terminal, a gate of the first NMOS tube NM1 is connected to a driving signal output end of the driving circuit; a second NMOS tube NM2, a drain of the second NMOS tube is connected to the second terminal, a gate of the second NMOS tube NM2 is connected to the driving signal output end of the driving circuit; a source of the first NMOS tube NM1 and a source of the second NMOS tube NM2 are connected.

[0066] Embodiment four:

[0067] In the embodiment, the surge detection circuit comprises a seventh resistor R7, a forward voltage stabilizing tube string Z F1 ~Z Fn , a reverse voltage stabilizing tube string Z B1 ~Z Bn and an eighth resistor R8 connected in series between the first terminal and the second terminal; the connection sequence from the first terminal to the second terminal is: the forward voltage stabilizing tube string Z F1 ~Z Fn , the seventh resistor R7, the eighth resistor R8 and the reverse voltage stabilizing tube string Z B1 ~Z Bn ; a connection point of the seventh resistor R7 and the eighth resistor R8 is connected to a first start signal receiving end and a second start signal receiving end of the driving circuit in turn.

[0068] In the embodiment, the driving circuit comprises a third PMOS tube PM3, a source of the third PMOS tube PM3 is connected to one end of the seventh resistor R7 close to the first terminal, a gate of the third PMOS tube PM3 is connected to one end of the seventh resistor R7 close to the second terminal; a fourth PMOS tube PM4, a source of the fourth PMOS tube PM4 is connected to one end of the eighth resistor R8 close to the second terminal, a gate of the fourth PMOS tube PM4 is connected to one end of the eighth resistor R8 close to the first terminal; a ninth resistor R9 and a tenth resistor R10 connected in series between drains of the third PMOS tube PM3 and the fourth PMOS tube PM4, a connection point of the ninth resistor R9 and the tenth resistor R10 is connected to an anode of a third voltage stabilizing tube Zp and a fourth voltage stabilizing tube Zm respectively, a cathode of the third voltage stabilizing tube Zp is connected to the drain of the third PMOS tube PM3, a cathode of the fourth voltage stabilizing tube Zm is connected to the drain of the fourth PMOS tube PM4; the connection point of the ninth resistor R9 and the tenth resistor R10 is connected to a driving signal receiving end of the surge discharge circuit as a driving signal output end.

[0069] In the embodiment, the surge discharge circuit comprises: a first NMOS tube NM1, a drain of the first NMOS tube NM1 is connected to the first terminal, a gate of the first NMOS tube NM1 is connected to a driving signal output end of the driving circuit; a second NMOS tube NM2, a drain of the second NMOS tube is connected to the second terminal, a gate of the second NMOS tube NM2 is connected to the driving signal output end of the driving circuit; a source of the first NMOS tube NM1 and a source of the second NMOS tube NM2 are connected.

[0070] Specifically, the circuit structure of the third embodiment is as shown in Figure 10 The first terminal is high voltage Vin, and the second terminal is low voltage GND, and the current path of the third embodiment is as shown in Figure 11 .

[0071] In the third embodiment, when a surge event occurs between Vin and GND, the bus voltage is greater than the breakdown voltage of the series of Zener diodes ZB1~ZBn, the surge detection unit is started, at this time, the voltage flowing through the series of Zener diodes ZB1~ZBn and ZF1~ZFn is along path 1 from Vin to GND; under the action of the seventh resistor R7, the third PMOS tube PM3 of the driving unit is turned on, and the current flows from Vin through the third PMOS tube PM3, the first Zener diode Zp, the tenth resistor R10 and the body diode of the fourth PMOS tube PM4 to GND, as shown in Figure 11 Path 3; the voltage drop generated by the tenth resistor R10 can turn on the first NMOS tube NM1 of the discharge circuit, so that the subsequent large surge current is discharged along the body diode of the first NMOS tube NM1 and the second NMOS tube NM2, as shown in Figure 11 Path 4.

[0072] When a surge event occurs between GND and Vin, the process is reverse symmetric to the above process, which will not be described here.

[0073] The circuit structure of the fourth embodiment is as shown in Figure 12 The first terminal is high voltage Vin, and the second terminal is low voltage GND, and the current path of the fourth embodiment is as shown in Figure 13 .

[0074] In the fourth embodiment, when a surge event occurs between Vin and GND, the bus voltage is greater than the breakdown voltage of the series of Zener diodes ZB1~ZBn, the surge detection unit is started, at this time, the voltage flowing through the series of Zener diodes ZB1~ZBn and ZF1~ZFn is along path 1 from Vin to GND; under the action of the seventh resistor R7, the third PMOS tube PM3 of the driving unit is turned on, and the current flows from Vin through the third PMOS tube PM3, the first Zener diode Zp, the tenth resistor R10 and the body diode of the fourth PMOS tube PM4 to GND, as shown inFigure 13 The voltage drop generated by the tenth resistor R10 can turn on the first NMOS NM1 of the discharge circuit, so that the subsequent large inrush current is discharged from Vin along the body diode of the first NMOS NM1 and the second NMOS NM2, as shown in path 4. Figure 13

[0075] When the inrush event occurs between GND and Vin, the above process is reversed symmetrically, which will not be described here.

[0076] Embodiments three and four use the same drive circuit and inrush discharge circuit as embodiment one, the difference is that the inrush detection circuit in embodiments three and four does not include a current mirror, but two resistors and forward and reverse voltage stabilizing tubes are connected in series between the first terminal and the second terminal.

[0077] Correspondingly, the connection positions of the input end, the output end, the first start signal receiving end and the second start signal receiving end of the drive circuit in embodiments three and four also change.

[0078] Further, the series order of the forward and reverse voltage stabilizing tubes ZB1-ZBn, ZF1-ZFn and the seventh resistor R7, the eighth resistor R8 in embodiments three and four is also different, but the drain and gate of the third PMOS PM3 of the drive circuit in embodiments three and four are connected across the seventh resistor, and the drain and gate of the fourth PMOS PM4 are connected across the eighth resistor.

[0079] Specifically, a three-stage dynamic adjustment scheme is used in embodiments three and four to further simplify the bidirectional surge protection circuit, the forward and reverse voltage stabilizing tubes ZB1-ZBn, ZF1-ZFn and the seventh resistor R7, the eighth resistor R8 are used to form the inrush detection circuit, the third PMOS PM3 and the fourth PMOS PM4 and the ninth resistor R9, the tenth resistor R10 are used to form the drive circuit, and the first NMOS NM1 and the second NMOS NM2 are used to form the inrush discharge circuit. The advantage of this is that the circuit is relatively simple and easy to implement. However, compared with the four-stage dynamic adjustment scheme of embodiments one and two, embodiments three and four require more current on path 1, so they are more suitable for fields with small inrush current. The reason is that the inrush detection circuit part shown in embodiments three and four is used to open the drive part, the current that can pass through path 2 is related to the current that flows through path 1 of the inrush detection circuit. To keep the large inrush current mainly along the low-conductance path 3, the current required by path 2 needs to be increased, so the current on the side of path 1 needs to be increased synchronously; after the current on path 1 is increased, the clamping voltage of the system increases, and due to the existence of the MOS current mirror in embodiments one and two, the current on path 1 can be amplified by n times, so that the current on path 1 hardly changes with the increase of the discharge inrush current. ​

[0080] Compared with the first and second embodiments, the circuit proposed in the third and fourth embodiments is suitable for the application field of the discharge current demand of 50A or less, while the bidirectional surge protection circuit shown in the first and second embodiments is suitable for the application field of the current of 50A or more. The two types of circuits can be complementary in terms of practicability and cost.

[0081] The above merely describes the preferred embodiments of the present application, but does not limit the implementation manners and protection scope of the present application. It should be understood by those skilled in the art that any equivalent replacement and obvious change made according to the content of the present application should be included in the protection scope of the present application.

Claims

1. A bidirectional surge protection circuit, characterized by, The surge detection circuit, the driving circuit and the surge discharge circuit are connected between the first terminal and the second terminal; The surge detection end of the surge detection circuit is connected with the first terminal and the second terminal, the start signal sending end of the surge detection circuit is connected with the start signal receiving end of the driving circuit, and the driving signal sending end of the driving circuit is connected with the driving signal receiving end of the surge discharge circuit; When a surge occurs between the first terminal and the second terminal, the surge detection circuit detects the surge current to generate a start signal, the driving circuit receives the start signal and amplifies it into a driving signal, and the surge discharge circuit is turned on by the driving signal to discharge the surge current; The start signal receiving end of the driving circuit comprises a first start signal receiving end and a second start signal receiving end; The surge detection circuit comprises: A first current mirror, the first terminal is connected with the first connection end and the second connection end of the first current mirror; A second current mirror, the second terminal is connected with the first connection end and the second connection end of the second current mirror; A forward voltage stabilizing tube string, a first resistor and a reverse voltage stabilizing tube string are connected in series between the third connection end of the first current mirror and the third connection end of the second current mirror; A second resistor is connected in series between the fourth connection end of the first current mirror and the fourth connection end of the second current mirror; The input end and the second start signal receiving end of the driving circuit are connected between the fourth connection end of the first current mirror and the second resistor; The output end and the first start signal receiving end of the driving circuit are connected between the fourth connection end of the second current mirror and the second resistor.

2. The bidirectional surge protection circuit of claim 1, wherein, The driving circuit comprises: A first PMOS tube, the source of the first PMOS tube is connected with the fourth connection end of the first current mirror, and the gate of the first PMOS tube is connected with the fourth connection end of the second current mirror; A second PMOS tube, the source of the second PMOS tube is connected with the fourth connection end of the second current mirror, and the gate of the second PMOS tube is connected with the fourth connection end of the first current mirror; A third resistor and a fourth resistor are connected in series between the drain of the first PMOS tube and the drain of the second PMOS tube, the connection point of the third resistor and the fourth resistor is connected with the anode of a first voltage stabilizing tube and a second voltage stabilizing tube respectively, the cathode of the first voltage stabilizing tube is connected with the drain of the first PMOS tube, and the cathode of the second voltage stabilizing tube is connected with the drain of the second PMOS tube; The connection point of the third resistor and the fourth resistor is connected with the driving signal receiving end of the surge discharge circuit as the driving signal output end.

3. The bidirectional surge protection circuit of claim 1, wherein, The driving circuit comprises: A third NMOS tube, the drain of the third NMOS tube is connected with the first terminal, and the gate of the third NMOS tube is connected with the fourth connection end of the first current mirror; A fourth NMOS tube, the drain of the fourth NMOS tube is connected with the second terminal, and the gate of the fourth NMOS tube is connected with the fourth connection end of the second current mirror; a fifth resistor and a sixth resistor connected in series between the sources of the third NMOS transistor and the fourth NMOS transistor, the connection points of the fifth resistor and the sixth resistor being connected to the anodes of a third Zener diode and a fourth Zener diode respectively, the cathode of the third Zener diode being connected to the source of the third NMOS transistor, and the cathode of the fourth Zener diode being connected to the source of the fourth NMOS transistor; the connection points of the fifth resistor and the sixth resistor being connected to the driving signal receiving end of the surge discharge circuit as the driving signal output end of the driving circuit.

4. The bidirectional surge protection circuit of claim 1, wherein, the starting signal receiving end of the driving circuit comprises a first starting signal receiving end and a second starting signal receiving end; the surge detection circuit comprises a seventh resistor, a forward Zener diode string, a reverse Zener diode string and an eighth resistor connected in series between the first terminal and the second terminal; the connection points of the seventh resistor and the forward Zener diode string are connected to the first starting signal receiving end of the driving circuit, and the connection points of the eighth resistor and the reverse Zener diode string are connected to the second starting signal receiving end of the driving circuit; the connection points of the seventh resistor and the eighth resistor are connected to the first starting signal receiving end and the second starting signal receiving end of the driving circuit in sequence. the driving circuit comprises:

5. The bidirectional surge protection circuit of claim 4, wherein, a third PMOS transistor, the source of the third PMOS transistor being connected to one end of the seventh resistor close to the first terminal, and the gate of the third PMOS transistor being connected to one end of the seventh resistor close to the second terminal; a fourth PMOS transistor, the source of the fourth PMOS transistor being connected to one end of the eighth resistor close to the second terminal, and the gate of the fourth PMOS transistor being connected to one end of the eighth resistor close to the first terminal; a ninth resistor and a tenth resistor connected in series between the drains of the third PMOS transistor and the fourth PMOS transistor, the connection points of the ninth resistor and the tenth resistor being connected to the anodes of a third Zener diode and a fourth Zener diode respectively, the cathode of the third Zener diode being connected to the drain of the third PMOS transistor, and the cathode of the fourth Zener diode being connected to the drain of the fourth PMOS transistor; the connection points of the ninth resistor and the tenth resistor being connected to the driving signal receiving end of the surge discharge circuit as the driving signal output end of the driving circuit. the surge discharge circuit comprises:

6. The bidirectional surge protection circuit of claim 1, wherein, a first NMOS transistor, the drain of the first NMOS transistor being connected to the first terminal, and the gate of the first NMOS transistor being connected to the driving signal output end of the driving circuit; a second NMOS transistor, the drain of the second NMOS transistor being connected to the second terminal, and the gate of the second NMOS transistor being connected to the driving signal output end of the driving circuit; the sources of the first NMOS transistor and the second NMOS transistor being connected. the first current mirror PMOS transistor and the second current mirror PMOS transistor are included in both the first current mirror and the second current mirror; 7. The bidirectional surge protection circuit of claim 1, wherein, ​ The source of the first current mirror PMOS tube is the first terminal, the source of the second current mirror PMOS tube is the second terminal, the drain of the first current mirror PMOS tube is the third terminal, and the drain of the second current mirror PMOS tube is the fourth terminal. The gate of the first current mirror PMOS tube is connected with the gate of the second current mirror PMOS tube and the drain of the first current mirror PMOS tube.

Images