Drive circuit for current regulation and negative voltage charge pump circuit

Abstract

The application belongs to the technical field of electronic circuits, and provides a driving circuit for current regulation and a negative voltage charge pump circuit. The driving circuit comprises a soft start module, a control module, a driving module and a current mirror module; the control module is connected with the source of the fourth power tube in the charge pump circuit respectively through the soft start module and the driving module; the current mirror module is connected with the soft start module and the driving module respectively; the driving module is connected with the gate of the first power tube, the gate of the second power tube, the gate of the third power tube and the gate of the fourth power tube in the charge pump circuit respectively. The driving circuit provided in the application can ensure that the current flowing through the third power tube is small in the initial stage of soft start, thereby ensuring the safety of the charge pump circuit; since the current flowing through the third power tube will gradually increase, after the soft start is completed, the output voltage of the charge pump circuit can reach the target voltage, so that the charge pump circuit can work normally.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a driving circuit for current regulation and a negative voltage charge pump circuit. BACKGROUND

[0002] In today's information society, with the rapid development of LCD (Liquid Crystal Display) technology, LCD liquid crystal display screens have been widely used in various electronic devices. In the driving system of the LCD liquid crystal display screen, VGH (high) and VGL (low) voltage signals are needed to control the gate switch, so the driving system needs to provide positive and negative power supplies at the same time. As a common negative power supply generation method, the negative voltage charge pump plays a key role in the driving system of the LCD liquid crystal display screen.

[0003] However, in the soft start process of the negative voltage charge pump, when the negative voltage charge pump works in the second phase, the drain voltage of the NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) power tube will change (from large to small), and in some processes, the linearity of the NMOS power tube is poor, so that the current flowing through the NMOS power tube also changes (from large to small) when the drain voltage changes, which easily leads to the negative voltage charge pump unable to work normally and safety problems. SUMMARY

[0004] The application embodiment provides a driving circuit for current regulation and a negative voltage charge pump circuit, which can solve the problem that in the soft start process of the current negative voltage charge pump, when the negative voltage charge pump works in the second phase, the drain voltage of the NMOS power tube will change (from large to small), and in some processes, the linearity of the NMOS power tube is poor, so that the current flowing through the NMOS power tube also changes (from large to small) when the drain voltage changes, which easily leads to the negative voltage charge pump unable to work normally and safety problems.

[0005] In a first aspect, the application embodiment provides a driving circuit for current regulation, comprising a soft start module, a control module, a driving module and a current mirror module; the control module is connected with the source of a fourth power tube in a charge pump circuit, the soft start module, the driving module and the current mirror module are connected with the control module respectively, and the driving module is connected with the gate of a first power tube, the gate of a second power tube, the gate of a third power tube and the gate of the fourth power tube in the charge pump circuit respectively.

[0006] The soft start module is configured to output a reference voltage, a first signal and n control signals; when the first signal is at a low level, the current mirror module is configured to output a first current in a step change manner according to the first signal and the n control signals, and output a second current according to the first signal; the control module is configured to output a second signal according to the reference voltage and an output voltage of the charge pump circuit; when the second signal is at a high level, the drive module is configured to control the first power tube to be turned off according to the second signal, the first signal and the second current, control the second power tube to be turned off according to the second signal, control the fourth power tube to be turned on according to the second signal, and gradually increase a gate voltage of the third power tube according to the second signal, the first signal and the first current, so as to gradually increase a current flowing through the third power tube; wherein n is a natural number greater than 0.

[0007] In a possible implementation manner of the first aspect, when the first signal is at a low level and the second signal is at a low level, the drive module is further configured to control the second power tube to be turned on according to the second signal, control the fourth power tube to be turned off according to the second signal, control the third power tube to be turned off according to the second signal, the first signal and the first current, and control a gate voltage of the first power tube according to the second signal, the first signal and the second current, so as to limit a current flowing through the first power tube.

[0008] In a possible implementation manner of the first aspect, the current mirror module comprises a first current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, n current mirror branches and n+1 inverters; a first end of the first current source, a source of the fourth transistor, a source of the sixth transistor and first ends of the n current mirror branches all receive a first voltage, a second end of the first current source is connected with a drain of the first transistor, a gate of the first transistor, a gate of the second transistor and a gate of the fifth transistor respectively, a drain of the second transistor is connected with a source of the third transistor, a drain of the third transistor is connected with the driving module, a drain of the fifth transistor is connected with a drain of the fourth transistor, a gate of the fourth transistor, a gate of the sixth transistor and second ends of the n current mirror branches respectively, third ends of the n current mirror branches are connected with output ends of the n inverters correspondingly, input ends of the n+1 inverters are connected with the soft start module respectively, a gate of the third transistor is connected with an output end of the n+1 inverter, a drain of the sixth transistor and fourth ends of the n current mirror branches are all connected with a source of the seventh transistor, a gate of the seventh transistor is connected with the soft start module, a drain of the seventh transistor is connected with the driving module, a source of the first transistor, a source of the second transistor and a source of the fifth transistor are all grounded.

[0009] The current mirror branch comprises two transistors; wherein a source of the first transistor is the first end of the current mirror branch, a gate of the first transistor is the second end of the current mirror branch, a gate of the second transistor is the third end of the current mirror branch, a drain of the second transistor is the fourth end of the current mirror branch, and a drain of the first transistor is connected with a source of the second transistor.

[0010] In a possible implementation manner of the first aspect, the soft start module comprises a soft start unit and a logic unit, the logic unit is connected with the soft start unit, the current mirror module and the driving module respectively.

[0011] The soft start unit is configured to output a reference voltage and a soft start signal; the logic unit is configured to receive a soft start time, divide the soft start time into n time periods according to the soft start signal, and output a first signal and n control signals corresponding to the n time periods.

[0012] In a possible implementation manner of the first aspect, the driving module comprises a clock generating unit, a first driving unit, a second driving unit, a third driving unit and a fourth driving unit; the clock generating unit is connected with the control module, the first driving unit, the second driving unit, the third driving unit and the fourth driving unit respectively; the first driving unit is connected with the soft start module, the current mirror module and the gate of the first power tube respectively; the second driving unit is configured to be connected with the gate of the second power tube; the third driving unit is connected with the soft start module, the current mirror module and the gate of the third power tube respectively; and the fourth driving unit is configured to be connected with the gate of the fourth power tube.

[0013] The clock generating unit is configured to output a third signal and a fourth signal according to a clock signal and the second signal; when the first signal is at a low level and the second signal is at a high level, the first driving unit is configured to control the first power tube to be turned off according to the third signal, the first signal and the second current; the second driving unit is configured to control the second power tube to be turned off according to the third signal; the third driving unit is configured to control the gate voltage of the third power tube to gradually increase according to the fourth signal, the first signal and the first current, so as to gradually increase the current flowing through the third power tube; and the fourth driving unit is configured to control the fourth power tube to be turned on according to the fourth signal.

[0014] In a possible implementation manner of the first aspect, the third driving unit comprises an NAND gate, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a first resistor; a first input terminal of the NAND gate is connected with the soft start module, an output terminal of the NAND gate is connected with a gate of the twentieth transistor, sources of the eighth transistor, the tenth transistor, the twelfth transistor, the seventeenth transistor and the twentieth transistor all receive a second voltage, a gate of the eighth transistor is connected with the clock generating unit, a gate of the ninth transistor and a second input terminal of the NAND gate respectively, a drain of the eighth transistor is connected with a drain of the ninth transistor, a gate of the tenth transistor and a gate of the eleventh transistor respectively, a drain of the tenth transistor is connected with a drain of the eleventh transistor, a gate of the twelfth transistor and a gate of the thirteenth transistor respectively, a drain of the twelfth transistor is connected with a drain of the thirteenth transistor, a gate of the seventeenth transistor and a gate of the nineteenth transistor respectively, a drain of the seventeenth transistor is connected with a drain of the eighteenth transistor, a source of the eighteenth transistor is connected with a drain of the nineteenth transistor, a first terminal of the first resistor, a drain of the twentieth transistor and a gate of the third power transistor respectively, a gate of the eighteenth transistor is connected with a drain of the fourteenth transistor, a gate of the fourteenth transistor and the current mirror module respectively, a source of the fourteenth transistor is connected with a drain of the fifteenth transistor, a gate of the fifteenth transistor and a gate of the sixteenth transistor respectively, a source of the fifteenth transistor is connected with a drain of the sixteenth transistor, a source of the ninth transistor, a source of the eleventh transistor, a source of the thirteenth transistor, a source of the sixteenth transistor, a source of the nineteenth transistor and a second terminal of the first resistor are all grounded.

[0015] In a possible implementation manner of the first aspect, the first driving unit comprises a first inverter, an AND gate, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor and a second resistor; an input end of the first inverter is connected with the clock generating unit, a gate of the twenty-first transistor and a gate of the twenty-second transistor respectively, an output end of the first inverter is connected with a first input end of the AND gate, a second input end of the AND gate is connected with the soft start module, an output end of the AND gate is connected with a gate of the thirty-third transistor, a source of the twenty-first transistor, a source of the twenty-third transistor, a source of the twenty-fifth transistor, a source of the twenty-seventh transistor, a source of the thirtieth transistor and a first end of the second resistor all receive an input voltage, a drain of the twenty-first transistor is connected with a drain of the twenty-second transistor, a gate of the twenty-third transistor and a gate of the twenty-fourth transistor respectively, a drain of the twenty-third transistor is connected with a drain of the twenty-fourth transistor, a gate of the twenty-fifth transistor and a gate of the twenty-sixth transistor respectively, a drain of the twenty-fifth transistor is connected with a drain of the twenty-sixth transistor, a gate of the thirtieth transistor and a gate of the thirty-second transistor respectively, a drain of the thirtieth transistor is connected with a source of the thirty-first transistor, a second end of the second resistor, a drain of the thirty-third transistor and a gate of the first power transistor respectively, a drain of the thirty-first transistor is connected with a drain of the thirty-second transistor, a gate of the thirty-first transistor is connected with a gate of the twenty-ninth transistor, a drain of the twenty-ninth transistor and the current mirror module respectively, a source of the twenty-ninth transistor is connected with a drain of the twenty-eighth transistor, a gate of the twenty-eighth transistor and a gate of the twenty-seventh transistor respectively, a source of the twenty-eighth transistor is connected with a drain of the twenty-seventh transistor, a source of the twenty-second transistor, a source of the twenty-fourth transistor, a source of the twenty-sixth transistor, a source of the thirty-second transistor and a source of the thirty-third transistor are all grounded.

[0016] In a possible implementation manner of the first aspect, the driving circuit further comprises a power supply module, the power supply module is connected with the driving module and the control module respectively.

[0017] When the second signal is at a high level, the power module is configured to output a second voltage to the driving module according to the second signal; when the first signal is at a high level and the charge pump circuit is in a light load state, the current mirror module is further configured to stop outputting the first current and the second current; and the driving module is further configured to control a gate voltage of the third power tube according to the second signal, the first signal and the second voltage, so as to limit a current flowing through the third power tube.

[0018] In a possible implementation of the first aspect, the power module comprises a second inverter, a second current source, a third current source, a first capacitor and a thirty-fourth transistor; an input end of the second inverter is connected with the control module, the driving module and a control end of the third current source respectively, an output end of the second inverter is connected with a control end of the second current source, a first end of the second current source and a drain of the thirty-fourth transistor receive a first voltage, a second end of the second current source is connected with a first end of the third current source, a first end of the first capacitor and a gate of the thirty-fourth transistor respectively, a second end of the third current source and a second end of the first capacitor are grounded, and a source of the thirty-fourth transistor is connected with the driving module.

[0019] In the second aspect, the embodiments of the present application provide a negative voltage charge pump circuit, comprising the driving circuit in any one of the first aspect.

[0020] In the third aspect, the embodiments of the present application provide a driving system, comprising the negative voltage charge pump circuit in any one of the second aspect.

[0021] In the fourth aspect, the embodiments of the present application provide a display screen, comprising the driving system in any one of the third aspect.

[0022] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0023] The embodiments of the present application provide a driving circuit for current regulation, comprising a soft start module, a control module, a driving module and a current mirror module; the control module is connected with the soft start module, the driving module and a source of a fourth power tube in the charge pump circuit respectively, the current mirror module is connected with the soft start module and the driving module respectively, and the driving module is configured to be connected with a gate of a first power tube, a gate of a second power tube, a gate of a third power tube and a gate of the fourth power tube in the charge pump circuit respectively.

[0024] The soft start module is configured to output a reference voltage, a first signal and n control signals. When the first signal is at a low level, it indicates that the charge pump circuit is in a soft start phase. In this phase, the current mirror module is configured to output a first current in a step change manner according to the first signal and the n control signals, and output a second current according to the first signal. The control module is configured to output a second signal according to the reference voltage and an output voltage of the charge pump circuit. When the second signal is at a high level, it indicates that the charge pump circuit is in a second phase. That is, when the charge pump circuit is in the second phase during the soft start process of the charge pump circuit, the driving module is configured to control the first power tube to be turned off according to the second signal, the first signal and the second current, control the second power tube to be turned off and the fourth power tube to be turned on according to the second signal, and gradually increase the gate voltage of the third power tube according to the second signal, the first signal and the first current, so as to gradually increase the current flowing through the third power tube; wherein n is a natural number greater than 0. In this way, the current flowing through the third power tube can be ensured to be small in the initial stage of the soft start, so as to ensure the safety of the charge pump circuit. Since the current flowing through the third power tube gradually increases, the output voltage of the charge pump circuit can reach a target voltage after the soft start is completed, so that the charge pump circuit can work normally.

[0025] In summary, the driving circuit provided by the embodiments of the present application can solve the problem that, in the soft start process of the current negative voltage charge pump, when the negative voltage charge pump is in the second phase, the drain voltage of the NMOS power tube changes (from large to small), and in some processes, the linearity of the NMOS power tube is poor, so that the current flowing through the NMOS power tube also changes (from large to small) when the drain voltage changes, which easily leads to the problem that the negative voltage charge pump cannot work normally and has safety problems.

[0026] It can be understood that the beneficial effects of the second aspect to the fourth aspect can be referred to the related description in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0028] Figure 1 is a circuit principle diagram of the prior art charge pump circuit;

[0029] Figure 2 is a principle block diagram of the driving circuit provided by an embodiment of the present application;

[0030] Figure 3is a principle block diagram of the driving circuit provided by another embodiment of the present application;

[0031] Figure 4 is a circuit connection diagram of the current mirror module;

[0032] Figure 5 is a circuit connection diagram of the third driving unit;

[0033] Figure 6 is a circuit diagram of the first driving unit;

[0034] Figure 7 is a principle block diagram of the driving circuit provided by another embodiment of the present application;

[0035] Figure 8 is a circuit connection diagram of the power supply module;

[0036] Figure 9 is a circuit connection diagram of the control module.

[0037] In the figure: 1, charge pump circuit; 2, driving circuit; 20, soft start module; 21, soft start unit; 22, logic unit; 30, control module; 40, driving module; 41, clock generation unit; 42, first driving unit; 43, second driving unit; 44, third driving unit; 45, fourth driving unit; 50, current mirror module; 51, current mirror branch; 60, power supply module. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0039] It should be understood that the term "comprising" when used in this specification and the appended claims, indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0040] It should also be understood that the term "and / or" when used in this specification and the appended claims, means any one or more of the associated listed items can be present, and includes multiples of those items that can be present.

[0041] As used in the specification and the appended claims, the term "if' can be interpreted as meaning "when" or "once" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "once it is determined" or "in response to a determination" or "once [the described condition or event] is detected" or "in response to detecting [a described condition or event]," depending on the context.

[0042] In addition, the terms "first", "second", "third", etc. as used in the description of the specification and the appended claims are only used to differentiate descriptions and cannot be understood as indicating or implying relative importance.

[0043] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment", "in some embodiments", "in other embodiments", "in additional embodiments", and so on, in various places in the specification are not necessarily all referring to the same embodiment, unless otherwise specifically specified. The terms "comprising", "including", "having" and their variants are meant to be construed as "including but not limited to", unless otherwise specifically noted.

[0044] Figure 1 The circuit principle diagram of the existing charge pump circuit 1 is shown as follows, Figure 1 As shown, the charge pump circuit 1 mainly includes a first power tube M1, a second power tube M2, a third power tube M3, a fourth power tube M4, a flying capacitor CFLY and an output capacitor COUT. The charge pump circuit 1 has two phases when working, which are a first phase and a second phase respectively. The first power tube M1 and the second power tube M2 are controlled by the first phase, and the third power tube M3 and the fourth power tube M4 are controlled by the second phase. In the first phase, the first power tube M1 and the second power tube M2 are turned on, and the third power tube M3 and the fourth power tube M4 are turned off, so that the flying capacitor CFLY is charged by the input voltage Vin; in the second phase, the first power tube M1 and the second power tube M2 are turned off, and the third power tube M3 and the fourth power tube M4 are turned on, so that the flying capacitor CFLY is connected in conduction with the output capacitor COUT through the fourth power tube M4, and the charge is transferred from the flying capacitor CFLY to the output capacitor COUT, and the output voltage Vneg is obtained, which is a negative voltage.

[0045] However, during the soft start process of the charge pump circuit 1, when the charge pump circuit 1 works in the second phase, the drain voltage of the third power tube M3 gradually decreases, the current of the ideal MOS tube in the saturation region changes little with the drain-source voltage, and the linearity of the NMOS power tube is poor in some processes, that is, the current in the saturation region changes greatly with the drain-source voltage under the same gate-source voltage, so when the drain voltage of the third power tube M3 changes (from large to small), the current flowing through the third power tube M3 also changes (also from large to small). If the current flowing through the third power tube M3 is not regulated, the current flowing through the NMOS power tube in the initial stage of soft start will be too large, which will cause safety problems of the charge pump circuit 1; if a fixed current limiting value is used, the output voltage of the charge pump circuit 1 after soft start will not reach the target voltage, which will eventually cause the charge pump circuit 1 to fail to work normally.

[0046] To solve the above problems, the embodiment of the present application provides a driving circuit for current regulation, as shown in Figure 2 The driving circuit 2 includes a soft start module 20, a control module 30, a driving module 40 and a current mirror module 50; the control module 30 is connected with the soft start module 20, the driving module 40 and the source of the fourth power tube M4 in the charge pump circuit 1 respectively, the current mirror module 50 is connected with the soft start module 20 and the driving module 40 respectively, and the driving module 40 is respectively used for connecting with the gate of the first power tube M1, the gate of the second power tube M2, the gate of the third power tube M3 and the gate of the fourth power tube M4 in the charge pump circuit 1.

[0047] Specifically, the soft start module 20 is configured to output the reference voltage Vref, the first signal SS_END, and the n control signals SS1, SS2,..., and SSn. When the first signal is at a low level, it indicates that the charge pump circuit 1 is in a soft start phase, and in the soft start phase, the reference voltage Vref gradually increases. In this phase, the current mirror module 50 is configured to output the first current IN that changes in steps according to the first signal SS_END and the n control signals SS1, SS2,..., and SSn, and output the second current IP according to the first signal SS_END. The control module 30 is configured to output the second signal D according to the reference voltage Vref and the output voltage Vneg of the charge pump circuit 1, and when the second signal D is at a high level, it indicates that the charge pump circuit 1 is in a second phase. That is, when the charge pump circuit 1 is in the second phase during the soft start process of the charge pump circuit 1, the driving module 40 is configured to control the first power tube M1 to be turned off according to the second signal D, the first signal SS_END, and the second current IP, control the second power tube M2 to be turned off and the fourth power tube M4 to be turned on according to the second signal D, and control the gate voltage of the third power tube M3 to gradually increase according to the second signal D, the first signal SS_END, and the first current IN, so as to gradually increase the current flowing through the third power tube M3. Wherein, n is a natural number greater than 0. In this way, it can be ensured that the current flowing through the third power tube M3 is small in the initial stage of the soft start, thereby ensuring the safety of the charge pump circuit 1. Since the current flowing through the third power tube M3 gradually increases, after the soft start is completed, it can be ensured that the output voltage Vneg of the charge pump circuit 1 reaches the target voltage, so that the charge pump circuit 1 can work normally.

[0048] In summary, the driving circuit 2 provided by the embodiments of the present application can solve the problem that in the soft start process of the charge pump circuit 1, when the charge pump circuit 1 is in the second phase, the drain voltage of the third power tube M3 changes (from large to small), and in some processes, the linearity of the third power tube M3 is poor, so that when the drain voltage changes, the current flowing through the third power tube M3 also changes (from large to small), which can easily cause the negative voltage charge pump to fail to work normally and cause safety problems.

[0049] It should be noted that when the first signal SS_END becomes high, it indicates that the soft start of the charge pump circuit 1 is completed, and at this time, the current mirror module 50 will stop outputting the first current IN and the second current IP, that is, current regulation is no longer needed.

[0050] In some embodiments, during the soft start process of the charge pump circuit 1, when the charge pump circuit 1 is in a first phase, the drain-source voltage VDS of the first power tube M1 is less than the threshold voltage Vth of the first power tube M1, and the driving module 40 is configured to control the first power tube M1 to be turned on according to the second signal D and the first signal SS_END. M1The current change is small, so only the basic current limiting of the current flowing through the first power tube M1 is needed, without segmented control, and the second current IP provided by the current mirror module 50 is the current for limiting the first power tube M1. Specifically, when the first signal SS_END is low and the second signal D is low, it indicates that the charge pump circuit 1 is in the soft start stage, and the charge pump circuit 1 works in the first phase. In this state, the driving module 40 is further configured to control the second power tube M2 to be turned on according to the second signal D, control the fourth power tube M4 to be turned off, control the third power tube M3 to be turned off according to the second signal D, the first signal SS_END and the first current IN, and control the gate voltage of the first power tube M1 according to the second signal D, the first signal SS_END and the second current IP, so as to limit the current flowing through the first power tube M1.

[0051] In some embodiments, as shown in Figure 3 The soft start module 20 includes a soft start unit 21 and a logic unit 22, and the logic unit 22 is connected with the soft start unit 21, the current mirror module 50 and the driving module 40 respectively.

[0052] Specifically, the soft start unit 21 is configured to output a reference voltage Vref and a soft start signal SS. The logic unit 22 is configured to receive a soft start time TS, divide the soft start time TS into n time periods according to the soft start signal SS, and output a first signal SS_END and n control signals SS1, SS2, …, SSn corresponding to the n time periods. It should be noted that the soft start time TS is provided by a digital module, and the present application does not protect the digital module, but only performs related operations according to the output soft start time TS.

[0053] In some embodiments, as shown in Figure 3 The driving module 40 includes a clock generation unit 41, a first driving unit 42, a second driving unit 43, a third driving unit 44 and a fourth driving unit 45; the clock generation unit 41 is connected with the control module 30, the first driving unit 42, the second driving unit 43, the third driving unit 44 and the fourth driving unit 45 respectively, the first driving unit 42 is connected with the soft start module 20, the current mirror module 50 and the gate of the first power tube M1 respectively, the second driving unit 43 is configured to be connected with the gate of the second power tube M2, the third driving unit 44 is connected with the soft start module 20, the current mirror module 50 and the gate of the third power tube M3 respectively, and the fourth driving unit 45 is configured to be connected with the gate of the fourth power tube M4.

[0054] Specifically, the clock generating unit 41 is configured to output the third signal A1 and the fourth signal B1 according to the clock signal CLK and the second signal D. When the first signal SS_END is at low level and the second signal D is at high level, it indicates that the charge pump circuit 1 is in the soft start stage and works in the second phase, and the third signal A1 and the fourth signal B1 are both at high level. In this state, the first driving unit 42 is configured to control the first power transistor M1 to be turned off according to the third signal A1, the first signal SS_END and the second current IP. The second driving unit 43 is configured to control the second power transistor M2 to be turned off according to the third signal A1. The third driving unit 44 is configured to control the gate voltage of the third power transistor M3 to gradually increase according to the fourth signal B1, the first signal SS_END and the first current IN, so as to gradually increase the current flowing through the third power transistor M3. The fourth driving unit 45 is configured to control the fourth power transistor M4 to be turned on according to the fourth signal B1. In the soft start process of the charge pump circuit 1, the current mirror module 50 outputs the first current IN in a step change manner, and the third driving unit 44 controls the current flowing through the third power transistor M3 to gradually increase, so as to solve the problem caused by poor linearity of the third power transistor M3 in some processes, and ensure that the current flowing through the third power transistor M3 is small in the initial stage of the soft start, and thus the safety of the charge pump circuit 1 is ensured. Since the current flowing through the third power transistor M3 gradually increases, after the soft start is completed, the output voltage Vneg of the charge pump circuit 1 can reach the target voltage, so that the charge pump circuit 1 can work normally.

[0055] In some embodiments, as Figure 4As shown, the current mirror module 50 includes a first current source I1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, n current mirror branches 51 and n+1 inverters INV; the first end of the first current source I1, the source of the fourth transistor Q4, the source of the sixth transistor Q6 and the first end of the n current mirror branches 51 all receive a first voltage VDD, the second end of the first current source I1 is connected with the drain of the first transistor Q1, the gate of the first transistor Q1, the gate of the second transistor Q2 and the gate of the fifth transistor Q5 respectively, the drain of the second transistor Q2 is connected with the source of the third transistor Q3, the drain of the third transistor Q3 is connected with the driving module 40, the drain of the fifth transistor Q5 is connected with the drain of the fourth transistor Q4, the gate of the fourth transistor Q4, the gate of the sixth transistor Q6 and the second end of the n current mirror branches 51 respectively, the third end of the n current mirror branches 51 is connected with the output end of the n inverters INV correspondingly, the input end of the n+1 inverters INV is connected with the soft start module 20 respectively, the gate of the third transistor Q3 is connected with the output end of the n+1 inverter INV, the drain of the sixth transistor Q6 and the fourth end of the n current mirror branches 51 are all connected with the source of the seventh transistor Q7, the gate of the seventh transistor Q7 is connected with the soft start module 20, the drain of the seventh transistor Q7 is connected with the driving module 40, the source of the first transistor Q1, the source of the second transistor Q2 and the source of the fifth transistor Q5 are all grounded.

[0056] The current mirror branch 51 includes two transistors Qt1, Qt2; wherein the source of the first transistor Qt1 is the first end of the current mirror branch 51, the gate of the first transistor Qt1 is the second end of the current mirror branch 51, the gate of the second transistor Qt2 is the third end of the current mirror branch 51, the drain of the second transistor Qt2 is the fourth end of the current mirror branch 51, and the drain of the first transistor Qt1 is connected with the source of the second transistor Qt2.

[0057] Specifically, the input end of the first n inverters INV receives n control signals SS1, SS2, …, SSn respectively, and outputs n signals SS1B, SS2B, …, SSnB after being inverted by the inverter INV.

[0058] The input end of the n+1 inverter INV receives a first signal SS_END, and outputs a signal SS_ENDB after being inverted by the inverter INV.

[0059] In the soft start process, the first signal SS_END is low, and the signal SS_ENDB is high.

[0060] The first current source I1 provides current to the first transistor Q1, and then replicates the current to the second transistor Q2 and the fifth transistor Q5. The current flowing through the second transistor Q2 is the second current IP. The fifth transistor Q5 transmits the current to the fourth transistor Q4, and then replicates the current to the sixth transistor Q6 and the n current mirror branches 51.

[0061] The signal SS_ENDB is high, and controls the third transistor Q3 to be turned on, for outputting the second current IP.

[0062] The first signal SS_END is low, and controls the seventh transistor Q7 to be turned on, for outputting the first current IN. When the soft start reaches the first time period, the signal SS1 becomes high, and the signal SS1B becomes low, for controlling the first current mirror branch 51 to be turned on. When the soft start reaches the second time period, the signal SS2 becomes high, and the signal SS2B becomes low, for controlling the second current mirror branch 51 to be turned on. In this way, the first current IN increases step by step with the increase of time.

[0063] When the soft start is finished, the first signal SS_END becomes high, and controls the seventh transistor Q7 to be turned off, so that the output of the first current IN is stopped. The signal SS_ENDB becomes low, and controls the third transistor Q3 to be turned off, so that the output of the second current IP is stopped.

[0064] In some embodiments, as Figure 5As shown, the third driving unit 44 comprises a NAND gate NAND, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, an eighteenth transistor Q18, a nineteenth transistor Q19, a twentieth transistor Q20 and a first resistor R1; a first input terminal of the NAND gate NAND is connected with the soft start module 20, an output terminal of the NAND gate NAND is connected with a gate of the twentieth transistor Q20, sources of the eighth transistor Q8, the tenth transistor Q10, the twelfth transistor Q12, the seventeenth transistor Q17 and the twentieth transistor Q20 all receive the second voltage VPP, a gate of the eighth transistor Q8 is connected with the clock generating unit 41, a gate of the ninth transistor Q9 and a second input terminal of the NAND gate NAND respectively, a drain of the eighth transistor Q8 is connected with a drain of the ninth transistor Q9, a gate of the tenth transistor Q10 and a gate of the eleventh transistor Q11 respectively, a drain of the tenth transistor Q10 is connected with a drain of the eleventh transistor Q11, a gate of the twelfth transistor Q12 and a gate of the thirteenth transistor Q13 respectively, a drain of the twelfth transistor Q12 is connected with a drain of the thirteenth transistor Q13, a gate of the seventeenth transistor Q17 and a gate of the nineteenth transistor Q19 respectively, a drain of the seventeenth transistor Q17 is connected with a drain of the eighteenth transistor Q18, a source of the eighteenth transistor Q18 is connected with a drain of the nineteenth transistor Q19, a first terminal of the first resistor R1, a drain of the twentieth transistor Q20 and a gate of the third power transistor M3 respectively, a gate of the eighteenth transistor Q18 is connected with a drain of the fourteenth transistor Q14, a gate of the fourteenth transistor Q14 and the current mirror module 50 respectively, a source of the fourteenth transistor Q14 is connected with a drain of the fifteenth transistor Q15, a gate of the fifteenth transistor Q15 and a gate of the sixteenth transistor Q16 respectively, a source of the fifteenth transistor Q15 is connected with a drain of the sixteenth transistor Q16, sources of the ninth transistor Q9, the eleventh transistor Q11, the thirteenth transistor Q13, the sixteenth transistor Q16, the nineteenth transistor Q19 and a second terminal of the first resistor R1 are all grounded.

[0065] Specifically, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, the twelfth transistor Q12, the thirteenth transistor Q13, the seventeenth transistor Q17 and the nineteenth transistor Q19 constitute a basic driving unit. The fourteenth transistor Q14, the fifteenth transistor Q15, the sixteenth transistor Q16, the eighteenth transistor Q18 and the first resistor R1 constitute a current mirror with negative feedback of resistance, which plays a role in regulating current. By regulating the first current IN, the resistance value of the first resistor R1, the width-length ratio of the fourteenth transistor Q14 and the eighteenth transistor Q18, and the width and length of the fifteenth transistor Q15 and the sixteenth transistor Q16, the gate voltage of the third power transistor M3 can be changed.

[0066] In the soft start process, the first signal SS_END is low, and no matter whether the fourth signal B1 is high or low, the signal SS_END2 output by the NAND gate is always high, controlling the twentieth transistor Q20 to be turned off. When the second signal D is high (indicating that the charge pump circuit 1 works in the second phase), the fourth signal B1 is also high, and then the gate voltage of the third power transistor M3 is controlled by the current mirror with negative feedback of resistance. When the resistance value of the first resistor R1 and the width-length ratio of the fourteenth transistor Q14 and the eighteenth transistor Q18 are determined, the gate voltage of the third power transistor M3 is controlled by the first current IN. Since the first current IN increases in steps, the gate voltage of the third power transistor M3 will also increase, and then the current flowing through the third power transistor M3 will also increase, solving the problem caused by the poor linearity of the third power transistor M3 under some processes. It can ensure that the current flowing through the third power transistor M3 is small in the initial stage of soft start, and then ensure the safety of the charge pump circuit 1; since the current flowing through the third power transistor M3 will gradually increase, after the soft start is completed, the output voltage Vneg of the charge pump circuit 1 can reach the target voltage, so that the charge pump circuit 1 can work normally.

[0067] After the soft start is completed, the first signal SS_END becomes high, and when the second signal D is high, the fourth signal B1 is high, and then the signal SS_END2 is low, controlling the twentieth transistor Q20 to be turned on, and then the current regulation is released. In this state, the gate voltage of the third power transistor M3 is the second voltage VPP.

[0068] In some embodiments, as Figure 6As shown, the first driving unit 42 comprises a first inverter INV1, an AND gate, a twenty-first transistor Q21, a twenty-second transistor Q22, a twenty-third transistor Q23, a twenty-fourth transistor Q24, a twenty-fifth transistor Q25, a twenty-sixth transistor Q26, a twenty-seventh transistor Q27, a twenty-eighth transistor Q28, a twenty-ninth transistor Q29, a thirtieth transistor Q30, a thirty-first transistor Q31, a thirty-second transistor Q32, a thirty-third transistor Q33 and a second resistor R2; the input end of the first inverter INV1 is connected with the clock generating unit 41, the gate of the twenty-first transistor Q21 and the gate of the twenty-second transistor Q22 respectively, the output end of the first inverter INV1 is connected with the first input end of the AND gate, the second input end of the AND gate is connected with the soft start module 20, the output end of the AND gate is connected with the gate of the thirty-third transistor Q33, the source of the twenty-first transistor Q21, the source of the twenty-third transistor Q23, the source of the twenty-fifth transistor Q25, the source of the twenty-seventh transistor Q27, the source of the thirtieth transistor Q30 and the first end of the second resistor R2 all receive the input voltage VIN, the drain of the twenty-first transistor Q21 is connected with the drain of the twenty-second transistor Q22, the gate of the twenty-third transistor Q23 and the gate of the twenty-fourth transistor Q24 respectively, the drain of the twenty-third transistor Q23 is connected with the drain of the twenty-fourth transistor Q24, the gate of the twenty-fifth transistor Q25 and the gate of the twenty-sixth transistor Q26 respectively, the drain of the twenty-fifth transistor Q25 is connected with the drain of the twenty-sixth transistor Q26, the gate of the thirtieth transistor Q30 and the gate of the thirty-second transistor Q32 respectively, the drain of the thirtieth transistor Q30 is connected with the source of the thirty-first transistor Q31, the second end of the second resistor R2, the drain of the thirty-third transistor Q33 and the gate of the first power transistor M1 respectively, the drain of the thirty-first transistor Q31 is connected with the drain of the thirty-second transistor Q32, the gate of the thirty-first transistor Q31 is connected with the gate of the twenty-ninth transistor Q29, the drain of the twenty-ninth transistor Q29 and the current mirror module 50 respectively, the source of the twenty-ninth transistor Q29 is connected with the drain of the twenty-eighth transistor Q28, the gate of the twenty-eighth transistor Q28 and the gate of the twenty-seventh transistor Q27 respectively, the source of the twenty-eighth transistor Q28 is connected with the drain of the twenty-seventh transistor Q27, the source of the twenty-second transistor Q22, the source of the twenty-fourth transistor Q24, the source of the twenty-sixth transistor Q26, the source of the thirty-second transistor Q32 and the source of the thirty-third transistor Q33 are all grounded.

[0069] Specifically, the twenty-first transistor Q21, the twenty-second transistor Q22, the twenty-third transistor Q23, the twenty-fourth transistor Q24, the twenty-fifth transistor Q25, the twenty-sixth transistor Q26, the thirtieth transistor Q30 and the thirty-second transistor Q32 constitute a basic drive unit. The twenty-seventh transistor Q27, the twenty-eighth transistor Q28, the twenty-ninth transistor Q29, the thirty-first transistor Q31 and the second resistor R2 constitute a current mirror with negative feedback resistance, which functions as a current limiter. The twenty-seventh transistor Q27 and the twenty-eighth transistor Q28 are in diode connection, the twenty-ninth transistor Q29 and the thirty-first transistor Q31 are in current mirror connection, and by adjusting the second current IP, the resistance value of the second resistor R2, the width-length ratio of the twenty-ninth transistor Q29 and the thirty-first transistor Q31, and the width and length of the twenty-seventh transistor Q27 and the twenty-eighth transistor Q28, the gate voltage of the first power transistor M1 can be changed, thereby changing the current limiting value thereof.

[0070] In the soft start process, the first signal SS_END is at a low level, and the signal SS_END1 is at a low level, thereby controlling the thirty-third transistor Q33 to be turned off. When the second signal D is at a low level (indicating that the charge pump circuit 1 is working in the first phase), the third signal A1 is also at a low level, and the gate voltage of the first power transistor M1 is controlled by the current mirror with negative feedback resistance. When the resistance value of the second resistor R2 and the width-length ratio of the twenty-ninth transistor Q29 and the thirty-first transistor Q31 are determined, the gate voltage of the first power transistor M1 is controlled by the second current IP, so as to achieve current limiting.

[0071] After the soft start is completed, the first signal SS_END becomes a high level. When the second signal D is at a low level, the third signal A1 is also at a low level, and the signal A2 is at a high level, the signal SS_END1 is at a high level, thereby controlling the thirty-third transistor Q33 to be turned on, and the current limiting is released, and the gate voltage of the first power transistor M1 is 0V.

[0072] In some embodiments, after the soft start is completed, if the charge pump circuit 1 is in a light load state and works in the second phase, the current flowing through the third power transistor M3 exceeds the requirement of the increase of IVneg, that is, the current flowing through the third power transistor M3 is large, which increases the power consumption of the circuit and has the risk of overcurrent. In order to solve the problem, the power module 60 is arranged in the drive circuit 2. Figure 7 As shown in FIG. 6, the drive circuit 2 further comprises a power module 60, and the power module 60 is connected with the drive module 40 and the control module 30 respectively. Figure 7 It can be known that the power module 60 is specifically connected with the third drive unit 44 in the drive module 40.

[0073] Specifically, when the second signal D is high, it indicates that the charge pump circuit 1 is in the second phase, and the power module 60 is configured to output the second voltage VPP to the drive module 40 according to the second signal D. When the first signal SS_END is high (indicating the end of soft start) and the charge pump circuit 1 is in a light load state (indicating that the load Rload in the charge pump circuit 1 has a small current demand), the current mirror module 50 stops outputting the first current IN and the second current IP. The drive module 40 controls the gate voltage of the third power tube M3 according to the second signal D, the first signal SS_END and the second voltage VPP, so as to limit the current flowing through the third power tube M3, thereby eliminating the risk of overcurrent and reducing the power consumption of the circuit.

[0074] As shown in Figure 8 The power module 60 includes a second inverter INV2, a second current source I2, a third current source I3, a first capacitor C1 and a thirty-fourth transistor Q34. The input terminals of the second inverter INV2 are connected with the control module 30, the drive module 40 and the control terminal of the third current source I3 respectively. The output terminal of the second inverter INV2 is connected with the control terminal of the second current source I2. The first terminal of the second current source I2 and the drain of the thirty-fourth transistor Q34 both receive the first voltage VDD. The second terminal of the second current source I2 is connected with the first terminal of the third current source I3, the first terminal of the first capacitor C1 and the gate of the thirty-fourth transistor Q34 respectively. The second terminal of the third current source I3 and the second terminal of the first capacitor C1 are both grounded. The source of the thirty-fourth transistor Q34 is connected with the drive module 40. It should be noted that the second current source I2 and the third current source I3 are simplified versions of PMOS and NMOS current output respectively.

[0075] Specifically, when the charge pump circuit 1 is in the second phase, the second signal D is high, the third current source I3 is controlled to be closed, and the second current source I2 is controlled to be opened. The second current source I2 charges the first capacitor C1. The thirty-fourth transistor Q34 is a source follower of a high-voltage tube. The second voltage VPP is the upper plate voltage of the first capacitor C1 minus the gate-source voltage of the thirty-fourth transistor Q34. When the charge pump circuit 1 is in the first phase, the second signal D is low, the second current source I2 is controlled to be closed, and the third current source I3 is controlled to be opened. The third current source I3 discharges the first capacitor C1. In the light load state, the charge pump circuit 1 will enter the second phase for several cycles, so the time of the first phase is relatively long, that is, the discharging time of the first capacitor C1 is relatively long, which ensures that the value of the second voltage VPP is relatively low when the charge pump circuit 1 enters the second phase. Since the gate voltage of the third power tube M3 is the second voltage VPP after the end of soft start, the second voltage VPP is relatively low, and the current flowing through the third power tube M3 is relatively low, which not only eliminates the risk of overcurrent, but also reduces the power consumption of the circuit.

[0076] In some embodiments, such as Figure 9 As shown, the control module 30 includes an error amplifier EA, a third resistor R3, a fourth resistor R4, and a comparator CMP. The first input terminal of the error amplifier EA receives a reference voltage Vref. The second input terminal of the error amplifier EA is connected to both the output terminal of the error amplifier EA and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to both the first terminal of the fourth resistor R4 and the first input terminal of the comparator CMP. The second input terminal of the comparator CMP is grounded. The second terminal of the fourth resistor R4 receives the output voltage Vneg. The output terminal of the comparator CMP outputs a second signal D. In this embodiment, the first input terminal of the error amplifier EA is a positive input terminal, and the second input terminal is a negative input terminal. The first input terminal of the comparator CMP is a positive input terminal, and the second input terminal is a negative input terminal.

[0077] Specifically, the input of the error amplifier EA is the reference voltage Vref, which is used to output the voltage Vref1. Assuming the resistance ratio of the fourth resistor R4 to the third resistor R3 is K, then when the charge pump circuit 1 operates in the first phase, when |Vneg| > K × Vref1, the second signal D is at a low level; when the charge pump circuit 1 operates in the second phase, when |Vneg| < K × Vref1, the second signal D is at a high level.

[0078] In summary, the driving circuit 2 provided in this application provides a step-changing first current IN output by the current mirror module 50 during the soft-start process of the charge pump circuit 1. Controlled by the third driving unit 44, the current flowing through the third power transistor M3 gradually increases, solving the problem caused by the poor linearity of the third power transistor M3 under certain process conditions. This ensures that the current flowing through the third power transistor M3 is small in the initial stage of soft-start, thereby guaranteeing the safety of the charge pump circuit 1. Since the current flowing through the third power transistor M3 gradually increases, after the soft-start is completed, the output voltage Vneg of the charge pump circuit 1 can reach the target voltage, enabling the charge pump circuit 1 to operate normally. Simultaneously, the power module 60 outputs a second voltage VPP, reducing the gate voltage of the third power transistor M3 when the charge pump circuit 1 is under light load, thereby reducing the current flowing through the third power transistor M3. This eliminates the risk of overcurrent and reduces circuit power consumption.

[0079] This application also provides a negative voltage charge pump circuit, including the driving circuit described above. Since the negative voltage charge pump circuit provided in this application includes the driving circuit described above, it has the advantages of being safe and reliable, operating stably, and having low power consumption.

[0080] The embodiment of the present application further provides a driving system comprising the negative voltage charge pump circuit. The driving system provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, and thus has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0081] The embodiment of the present application further provides a display screen comprising the driving system. The display screen provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, and thus has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0082] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0083] The above embodiments are only used to illustrate the technical solutions of the present application, rather than limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A drive circuit for current regulation, characterized by The soft start module, the control module, the driving module and the current mirror module are included; the control module is connected with the soft start module, the driving module and the source of the fourth power tube in the charge pump circuit respectively; the current mirror module is connected with the soft start module and the driving module respectively; the driving module is used for connecting with the gate of the first power tube, the gate of the second power tube, the gate of the third power tube and the gate of the fourth power tube in the charge pump circuit respectively; The soft start module is used for outputting a reference voltage, a first signal and n control signals; when the first signal is at a low level, the current mirror module is used for outputting a first current with step change according to the first signal and the n control signals, and outputting a second current according to the first signal; the control module is used for outputting a second signal according to the reference voltage and the output voltage of the charge pump circuit; when the second signal is at a high level, the driving module is used for controlling the first power tube to be turned off according to the second signal, the first signal and the second current, controlling the second power tube to be turned off and the fourth power tube to be turned on according to the second signal, and controlling the gate voltage of the third power tube to gradually increase according to the second signal, the first signal and the first current, so as to gradually increase the current flowing through the third power tube; wherein n is a natural number greater than 0.

2. The drive circuit according to claim 1, characterized in that, When the first signal is at a low level and the second signal is at a low level, the driving module is further used for controlling the second power tube to be turned on and the fourth power tube to be turned off according to the second signal, controlling the third power tube to be turned off according to the second signal, the first signal and the first current, and controlling the gate voltage of the first power tube according to the second signal, the first signal and the second current, so as to limit the current flowing through the first power tube.

3. The drive circuit according to claim 1 or 2, characterized in that, The current mirror module includes a first current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, n current mirror branches and n+1 inverters; The first end of the first current source, the source of the fourth transistor, the source of the sixth transistor and the first end of the n current mirror branches all receive a first voltage, the second end of the first current source is connected with the drain of the first transistor, the gate of the first transistor, the gate of the second transistor and the gate of the fifth transistor respectively, the drain of the second transistor is connected with the source of the third transistor, the drain of the third transistor is connected with the driving module, the drain of the fifth transistor is connected with the drain of the fourth transistor, the gate of the fourth transistor, the gate of the sixth transistor and the second end of the n current mirror branches respectively, the third end of the n current mirror branches is connected with the output end of the n inverters correspondingly, the input end of the n+1 inverters is connected with the soft start module respectively, the gate of the third transistor is connected with the output end of the n+1 inverter, the drain of the sixth transistor and the fourth end of the n current mirror branches are all connected with the source of the seventh transistor, the gate of the seventh transistor is connected with the soft start module, the drain of the seventh transistor is connected with the driving module, the source of the first transistor, the source of the second transistor and the source of the fifth transistor are all grounded; The current mirror branch comprises two transistors; The source of the first transistor is used as the first end of the current mirror branch, the gate of the first transistor is used as the second end of the current mirror branch, the gate of the second transistor is used as the third end of the current mirror branch, the drain of the second transistor is used as the fourth end of the current mirror branch, and the drain of the first transistor is connected with the source of the second transistor.

4. The drive circuit according to claim 1 or 2, characterized in that, The soft start module comprises a soft start unit and a logic unit, and the logic unit is connected with the soft start unit, the current mirror module and the driving module respectively; The soft start unit is used for outputting a reference voltage and a soft start signal, and the logic unit is used for receiving a soft start time, dividing the soft start time into n time periods according to the soft start signal, and outputting a first signal and n control signals corresponding to the n time periods.

5. The drive circuit according to claim 1 or 2, characterized in that, The driving module comprises a clock generation unit, a first driving unit, a second driving unit, a third driving unit and a fourth driving unit, the clock generation unit is connected with the control module, the first driving unit, the second driving unit, the third driving unit and the fourth driving unit respectively, the first driving unit is connected with the gate of the first power transistor, the gate of the second power transistor and the gate of the fourth power transistor respectively, the second driving unit is used for being connected with the gate of the second power transistor, the third driving unit is connected with the gate of the third power transistor, and the fourth driving unit is used for being connected with the gate of the fourth power transistor. The clock generating unit is configured to output a third signal and a fourth signal according to the clock signal and the second signal; when the first signal is at a low level and the second signal is at a high level, the first driving unit is configured to control the first power tube to be turned off according to the third signal, the first signal and the second current; the second driving unit is configured to control the second power tube to be turned off according to the third signal; the third driving unit is configured to control the gate voltage of the third power tube to gradually increase according to the fourth signal, the first signal and the first current, so as to gradually increase the current flowing through the third power tube; and the fourth driving unit is configured to control the fourth power tube to be turned on according to the fourth signal.

6. The drive circuit according to claim 5, characterized in that, The third driving unit comprises an NAND gate, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a first resistor; a first input end of the NAND gate is connected with the soft start module, an output end of the NAND gate is connected with a gate of the twentieth transistor, sources of the eighth transistor, the tenth transistor, the twelfth transistor, the seventeenth transistor and the twentieth transistor all receive a second voltage, a gate of the eighth transistor is connected with the clock generating unit, a gate of the ninth transistor and a second input end of the NAND gate respectively, a drain of the eighth transistor is connected with a drain of the ninth transistor, a gate of the tenth transistor and a gate of the eleventh transistor respectively, a drain of the tenth transistor is connected with a drain of the eleventh transistor, a gate of the twelfth transistor and a gate of the thirteenth transistor respectively, a drain of the twelfth transistor is connected with a drain of the thirteenth transistor, a gate of the seventeenth transistor and a gate of the nineteenth transistor respectively, a drain of the seventeenth transistor is connected with a drain of the eighteenth transistor, a source of the eighteenth transistor is connected with a drain of the nineteenth transistor, a first end of the first resistor, a drain of the twentieth transistor and a gate of the third power tube respectively, a gate of the eighteenth transistor is connected with a drain of the fourteenth transistor, a gate of the fourteenth transistor and the current mirror module respectively, a source of the fourteenth transistor is connected with a drain of the fifteenth transistor, a gate of the fifteenth transistor and a gate of the sixteenth transistor respectively, a source of the fifteenth transistor is connected with a drain of the sixteenth transistor, a source of the ninth transistor, a source of the eleventh transistor, a source of the thirteenth transistor, a source of the sixteenth transistor, a source of the nineteenth transistor and a second end of the first resistor are all grounded.

7. The drive circuit according to claim 5, characterized by The first driving unit includes a first inverter, an AND gate, a 21st transistor, a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, a 26th transistor, a 27th transistor, a 28th transistor, a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, and a second resistor; an input end of the first inverter is connected with the clock generating unit, a gate of the 21st transistor and a gate of the 22nd transistor respectively, an output end of the first inverter is connected with a first input end of the AND gate, a second input end of the AND gate is connected with the soft start module, an output end of the AND gate is connected with a gate of the 33rd transistor, a source of the 21st transistor, a source of the 23rd transistor, a source of the 25th transistor, a source of the 27th transistor, a source of the 30th transistor and a first end of the second resistor all receive an input voltage, a drain of the 21st transistor is connected with a drain of the 22nd transistor, a gate of the 23rd transistor and a gate of the 24th transistor respectively, a drain of the 23rd transistor is connected with a drain of the 24th transistor, a gate of the 25th transistor and a gate of the 26th transistor respectively, a drain of the 25th transistor is connected with a drain of the 26th transistor, a gate of the 30th transistor and a gate of the 32nd transistor respectively, a drain of the 30th transistor is connected with a source of the 31st transistor, a second end of the second resistor, a drain of the 33rd transistor and a gate of the first power transistor respectively, a drain of the 31st transistor is connected with a drain of the 32nd transistor, a gate of the 31st transistor is connected with a gate of the 29th transistor, a drain of the 29th transistor and the current mirror module respectively, a source of the 29th transistor is connected with a drain of the 28th transistor, a gate of the 28th transistor and a gate of the 27th transistor respectively, a source of the 28th transistor is connected with a drain of the 27th transistor, and a source of the 22nd transistor, a source of the 24th transistor, a source of the 26th transistor, a source of the 32nd transistor and a source of the 33rd transistor are all grounded.

8. The drive circuit according to claim 1 or 2, characterized in that, The driving circuit further includes a power supply module, the power supply module is connected with the driving module and the control module respectively; when the second signal is a high level, the power supply module is configured to output a second voltage to the driving module according to the second signal; when the first signal is a high level and the charge pump circuit is in a light load state, the current mirror module is further configured to stop outputting the first current and the second current; and the driving module is further configured to control a gate voltage of the third power transistor according to the second signal, the first signal and the second voltage, so as to limit the current flowing through the third power transistor.

9. The drive circuit according to claim 8, characterized in that, The power module comprises a second inverter, a second current source, a third current source, a first capacitor and a thirty-fourth transistor; an input end of the second inverter is connected with the control module, the driving module and a control end of the third current source respectively, an output end of the second inverter is connected with a control end of the second current source, a first end of the second current source and a drain of the thirty-fourth transistor both receive a first voltage, a second end of the second current source is connected with a first end of the third current source, a first end of the first capacitor and a gate of the thirty-fourth transistor respectively, a second end of the third current source and a second end of the first capacitor are both grounded, and a source of the thirty-fourth transistor is connected with the driving module.

10. A negative voltage charge pump circuit, characterized by, A display device comprising the driving circuit of any one of claims 1-9.

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