A low-jitter sub-sampling phase-locked loop based on feedforward phase noise cancellation technique

Abstract

The application belongs to the technical field of digital-analog hybrid integrated circuit design, and particularly discloses a low-jitter sub-sampling phase-locked loop based on feedforward phase noise cancellation technology, which comprises a sub-sampling phase-locked loop, a noise cancellation path and a calibration path; the phase noise signal is extracted at the output of the sub-sampling phase discriminator of the sub-sampling phase-locked loop, the phase noise signal is converted in level and amplified in the noise cancellation path, the feedforward noise signal is then fed to the sub-sampling phase-locked loop and superimposed with the inherent noise signal in the sub-sampling phase-locked loop, the feedforward phase noise compensation of the sub-sampling phase-locked loop is completed, and thus the phase noise of the sub-sampling phase-locked loop is significantly suppressed; the phase noise signal is extracted through the calibration path, and a control signal is output to the noise cancellation path to eliminate the gain mismatch in the noise cancellation path caused by process, voltage and temperature changes; compared with the conventional phase-locked loop based on the noise cancellation module, the application eliminates the limitation on the working frequency and power consumption, and avoids the complex calibration.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital-analog hybrid integrated circuit design, and particularly relates to a low-jitter sub-sampling phase-locked loop based on a feedforward phase noise cancellation technology. BACKGROUND

[0002] With the rapid growth of communication data rate, more and more stringent jitter performance requirements are imposed on clock signals. As an important component in modern system-on-chip, it is necessary to design a phase-locked loop with low jitter, low power consumption and small area. The phase-locked loop based on a ring oscillator is concerned due to its multiple advantages, including wide tuning range, compact chip area and the ability to generate multiple-phase outputs. However, compared with LC oscillators, the ring oscillator itself has poor phase noise, resulting in large jitter. Therefore, how to effectively eliminate the phase noise of the ring oscillator has become a bottleneck for the development of the phase-locked loop based on the ring oscillator.

[0003] The feedforward noise cancellation technology is a solution to reduce the jitter of the ring oscillator, which opens a feedforward noise compensation channel outside the phase-locked loop: extracts the phase noise component from the output of the ring oscillator, generates an inverted signal through an adjustable gain network, and injects it into the noise cancellation module, so as to offset the intrinsic noise of the oscillator without destroying the stability of the closed loop. However, the noise cancellation module limits the working frequency and power consumption of the sub-sampling phase-locked loop, and the gain of the noise cancellation module needs to be manually calibrated. SUMMARY

[0004] In view of the problems in the prior art, the application provides a low-jitter sub-sampling phase-locked loop based on a feedforward phase noise cancellation technology, which comprises:

[0005] a sub-sampling phase-locked loop;

[0006] a noise cancellation path, which comprises a level shifter and a variable gain amplifier, the input end of the level shifter is connected with the sub-sampling phase-locked loop, the output end of the level shifter is connected with the first input end of the variable gain amplifier, the level shifter is used for extracting the phase noise signal of the output of the sub-sampling phase-locked loop and performing level conversion; and the variable gain amplifier is used for amplifying the phase noise signal after level conversion and outputting the noise signal to the sub-sampling phase-locked loop;

[0007] a calibration path, the input end of which is connected with the first output end, the second output end, the third output end and the fourth output end of the sub-sampling phase-locked loop, and the calibration path outputs a control signal to the variable gain amplifier;

[0008] The noise cancellation path and the calibration path extract the phase noise signal output by the sub-sampling phase-locked loop while the sub-sampling phase-locked loop is in phase locking; the noise cancellation path feeds the phase noise signal to the sub-sampling phase-locked loop after level conversion and amplification, and superimposes the phase noise signal with the inherent noise signal in the sub-sampling phase-locked loop, thereby completing the sub-sampling phase-locked loop feedforward phase noise compensation and realizing phase noise cancellation; the calibration path generates a control signal for adjusting the variable gain amplifier by sequentially performing mixing, filtering and amplification on the phase noise signal, thereby realizing gain self-calibration of the noise signal.

[0009] Further, the calibration path comprises a polyphase filter, a mixer, a bandpass filter and an operational amplifier.

[0010] The input end of the polyphase filter is connected with the first output end, the second output end, the third output end and the fourth output end of the sub-sampling phase-locked loop; the polyphase filter is used to make the signal output by the polyphase filter be in quadrature phase.

[0011] The first input end, the second input end, the third input end and the fourth input end of the mixer are respectively connected with the first output end, the second output end, the third output end and the fourth output end of the polyphase filter; the mixer is used to extract the phase noise signal output by the sub-sampling phase-locked loop and perform mixing.

[0012] The positive input end of the bandpass filter is connected with the first output end of the mixer, and the negative input end of the bandpass filter is connected with the second output end of the mixer; the bandpass filter is used to filter out the unwanted mixer output frequency.

[0013] The operational amplifier is connected in parallel with the bandpass filter, the output end of the operational amplifier is connected with the second input end of the variable gain amplifier, and the output end of the operational amplifier outputs a control signal.

[0014] Further, the level shifter comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and an inverter.

[0015] The drain and gate of the first NMOS transistor and the drain and gate of the second NMOS transistor are connected to a power supply; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the fourth NMOS transistor; the source of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the sixth NMOS transistor and the output of the level shifter; the input of the level shifter is connected to the gate of the fifth NMOS transistor and the input of the inverter; the output of the inverter is connected to the gate of the sixth NMOS transistor; the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to ground.

[0016] Further, the variable gain amplifier comprises a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a first resistor, a second resistor and a current source;

[0017] One end of the first resistor is connected to a power supply, and the other end is connected to the drain of the seventh NMOS transistor, the drain of the ninth NMOS transistor and the output of the variable gain amplifier;

[0018] One end of the second resistor is connected to a power supply, and the other end is connected to the drain of the eighth NMOS transistor and the drain of the tenth NMOS transistor;

[0019] The first input of the variable gain amplifier is connected to the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor; the drain of the eleventh NMOS transistor is connected to the source of the eighth NMOS transistor and the source of the ninth NMOS transistor; the drain of the twelfth NMOS transistor is connected to the source of the seventh NMOS transistor and the source of the tenth NMOS transistor;

[0020] The positive input of the second input of the variable gain amplifier is connected to the gate of the eleventh NMOS transistor, and the negative input of the second input of the variable gain amplifier is connected to the gate of the twelfth NMOS transistor; the input of the current source is connected to the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor; the output of the current source is connected to ground.

[0021] Further, the mixer comprises a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a first capacitor and a second capacitor;

[0022] The first input end of the mixer is connected to the drain of the thirteenth NMOS transistor and the drain of the fifteenth NMOS transistor; the second input end of the mixer is connected to the gate of the thirteenth NMOS transistor and the gate of the sixteenth NMOS transistor; the third input end of the mixer is connected to the gate of the fourteenth NMOS transistor and the gate of the fifteenth NMOS transistor; the fourth input end of the mixer is connected to the drain of the fourteenth NMOS transistor and the drain of the sixteenth NMOS transistor;

[0023] One end of the first capacitor is grounded, and the other end is connected to the source of the thirteenth NMOS transistor and the source of the fourteenth NMOS transistor, and is the first output end of the mixer; one end of the second capacitor is grounded, and the other end is connected to the source of the fifteenth NMOS transistor and the source of the sixteenth NMOS transistor, and is the second output end of the mixer.

[0024] Further, the band-pass filter comprises a first-stage trans-impedance amplifier, a second-stage trans-impedance amplifier, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a third resistor and a fourth resistor;

[0025] The positive input end of the second-stage trans-impedance amplifier is the positive input end of the band-pass filter, and the negative input end of the second-stage trans-impedance amplifier is the negative input end of the band-pass filter;

[0026] One end of the fifth capacitor is grounded, and the other end is connected to the negative input end of the first-stage trans-impedance amplifier and the negative output end of the second-stage trans-impedance amplifier; one end of the sixth capacitor is grounded, and the other end is connected to the positive input end of the first-stage trans-impedance amplifier and the positive output end of the second-stage trans-impedance amplifier;

[0027] The positive output end of the first-stage trans-impedance amplifier is the positive output end of the band-pass filter, and the negative output end of the first-stage trans-impedance amplifier is the negative output end of the band-pass filter;

[0028] The positive input end of the operational amplifier is connected to the positive input end of the band-pass filter, and the negative input end of the operational amplifier is connected to the negative input end of the band-pass filter; the positive output end of the operational amplifier is connected to the positive output end of the band-pass filter, and the negative output end of the operational amplifier is connected to the negative output end of the band-pass filter;

[0029] One end of the third capacitor is connected to the positive input terminal of the operational amplifier, and the other end is connected to the positive output terminal of the operational amplifier; one end of the third resistor is connected to the positive input terminal of the operational amplifier, and the other end is connected to the positive output terminal of the operational amplifier; one end of the fourth capacitor is connected to the negative input terminal of the operational amplifier, and the other end is connected to the negative output terminal of the operational amplifier; one end of the fourth resistor is connected to the negative input terminal of the operational amplifier, and the other end is connected to the negative output terminal of the operational amplifier.

[0030] Further, the sub-sampling phase-locked loop comprises a frequency-locked loop and a sub-sampling phase-locked loop; the sub-sampling phase-locked loop is used to realize the locking of phase, and the frequency-locked loop is used to realize the locking of frequency; during the locking process of the sub-sampling phase-locked loop signal, the frequency locking is completed first, and then the phase locking is completed.

[0031] Further, the sub-sampling phase-locked loop comprises a ring oscillator, a sub-sampling phase detector, a transconductance amplifier, a low-pass filter and a buffer.

[0032] The input end of the sub-sampling phase detector is connected to a reference signal and the third output end of the ring oscillator, the output end of the sub-sampling phase detector is connected to the input end of the transconductance amplifier and the input end of the level shifter, the output end of the transconductance amplifier is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the input end of the ring oscillator, and the second output end of the ring oscillator is connected to the buffer.

[0033] The first output end, the second output end, the third output end and the fourth output end of the ring oscillator are the first output end, the second output end, the third output end and the fourth output end of the sub-sampling phase-locked loop.

[0034] Further, while the sub-sampling phase-locked loop is locking the phase, the phase noise signal generated by the ring oscillator is extracted at the output of the sub-sampling phase detector and the output of the ring oscillator for the noise cancellation path and the calibration path, and the noise signal fed forward by the noise cancellation path is superimposed with the noise signal inherent in the input end of the ring oscillator.

[0035] Further, the frequency-locked loop comprises a frequency / phase detector, a charge pump and a frequency divider.

[0036] The input end of the frequency divider is connected with the fourth output end of the ring oscillator, the input end of the frequency discriminator is connected with a reference signal and the output end of the frequency divider, the output end of the frequency discriminator is connected with the input end of the charge pump, the output end of the charge pump is connected with the input end of the low-pass filter, and the frequency divider, the frequency discriminator, the charge pump, the low-pass filter and the ring oscillator form a frequency-locked loop.

[0037] Compared with the prior art, the present application has the following beneficial technical effects:

[0038] Firstly, the present application extracts the phase noise signal at the output of the sub-sampling phase discriminator and cancels it at the input of the ring oscillator through the noise cancellation path, thereby realizing the effective frequency limitation of the traditional feedforward noise cancellation technology.

[0039] Thirdly, the present application avoids the noise cancellation module added at the output of the ring oscillator required by the traditional feedforward noise cancellation technology, and greatly reduces the power consumption.

[0040] Secondly, the present application effectively eliminates the gain mismatch in the feedforward noise cancellation path caused by the process, voltage and temperature changes through the self-calibration path. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be known that the drawings described below only relate to some embodiments of the present disclosure, not limit the present disclosure, wherein:

[0042] Figure 1 is a structure diagram of a low-jitter sub-sampling phase-locked loop based on feedforward phase noise cancellation technology proposed by the present application;

[0043] Figure 2 is a specific structure diagram of a low-jitter sub-sampling phase-locked loop based on feedforward phase noise cancellation technology proposed by the present application;

[0044] Figure 3 is a principle diagram of a noise cancellation path core module proposed by the present application, wherein (a) is a principle diagram of a level shifter, and (b) is a principle diagram of a variable gain amplifier;

[0045] Figure 4 is a principle diagram of a calibration path core module proposed by the present application, wherein (a) is a principle diagram of a mixer, and (b) is a principle diagram of a polyphase filter. DETAILED DESCRIPTION

[0046] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application.

[0047] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0048] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present application is usually placed, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" and the like are only used for differentiation in description and cannot be understood as indicating or implying relative importance.

[0049] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "set", "mount", "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0050] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0051] As Figures 1-4 shown, the present application proposes a low-jitter sub-sampling phase-locked loop based on feedforward phase noise cancellation technology, which comprises:

[0052] a sub-sampling phase-locked loop;

[0053] The noise cancellation path comprises a level shifter and a variable gain amplifier, the input end of the level shifter is connected with the subsampling phase-locked loop, the output end of the level shifter is connected with the first input end of the variable gain amplifier, and the level shifter is used for extracting a phase noise signal output by the subsampling phase-locked loop and performing level conversion; the variable gain amplifier is used for amplifying the phase noise signal after the level conversion and outputting the noise signal to the subsampling phase-locked loop;

[0054] The calibration path is connected with the first output end, the second output end, the third output end and the fourth output end of the subsampling phase-locked loop, and outputs a control signal to the variable gain amplifier;

[0055] While the subsampling phase-locked loop is in phase locking, the noise cancellation path and the calibration path extract a phase noise signal in the subsampling phase-locked loop; the noise cancellation path feeds forward the phase noise signal to the subsampling phase-locked loop after level conversion and amplification, and superimposes the phase noise signal with inherent noise signals in the subsampling phase-locked loop, so as to complete phase noise compensation of the subsampling phase-locked loop and realize phase noise cancellation; the calibration path generates a control signal for adjusting the variable gain amplifier by sequentially performing mixing, filtering and amplification on the phase noise signal, so as to realize gain self-calibration of the noise signal.

[0056] In some embodiments of the present application, the noise cancellation path and the calibration path are used to eliminate the limitation of traditional noise cancellation technology on the working frequency and power consumption of the phase-locked loop and realize gain self-calibration; in the locked state, the ideal sampling voltage of the subsampling phase detector should be zero; however, the random fluctuation of the ring oscillator zero-crossing point caused by the phase noise will cause the sampling voltage of the subsampling phase detector to be randomly variable around zero; thus, the phase noise signal can be effectively extracted from the output of the sampling phase detector; after level conversion and amplification, the extracted noise signal is superimposed with the inherent noise of the input end of the ring oscillator; this feedforward compensation eliminates the noise propagated to the control line of the ring oscillator, thereby reducing the jitter of the subsampling phase-locked loop; the noise cancellation of the feedforward noise cancellation path is completed before the ring oscillator; therefore, it avoids introducing an additional noise cancellation module at the output end of the subsampling phase-locked loop, thereby eliminating the frequency and power consumption limitations while ensuring effective phase noise cancellation; however, the gain of the variable gain amplifier will seriously affect the effectiveness of the phase noise cancellation. Therefore, the gain needs to be calibrated to optimize the noise cancellation.

[0057] Specifically, the calibration path comprises a polyphase filter, a mixer, a band-pass filter and an operational amplifier; the input end of the polyphase filter is connected with the first output end, the second output end, the third output end and the fourth output end of the sub-sampling phase-locked loop; the polyphase filter is used to make the output signal thereof be in quadrature phase; the first input end, the second input end, the third input end and the fourth input end of the mixer are respectively connected with the first output end out1, the second output end out2, the third output end out3 and the fourth output end out4 of the polyphase filter; the mixer is used to extract the phase noise signal output by the sub-sampling phase-locked loop and mix the same; the positive input end of the band-pass filter is connected with the first output end of the mixer, and the negative input end of the band-pass filter is connected with the second output end of the mixer; the band-pass filter is used to filter out the frequency of the mixer output which is not needed; the operational amplifier is connected in parallel with the band-pass filter, the output end of the operational amplifier is connected with the second input end of the variable gain amplifier, and the output end of the operational amplifier outputs a control signal.

[0058] In some embodiments of the present application, the calibration path of the present application uses a delay line discriminator-based architecture to extract the phase noise; the phase noise signal output by the ring oscillator is first mixed by a mixer, and then filtered and amplified by a band-pass filter and an operational amplifier to generate a control signal for adjusting the gain of the variable gain amplifier; and the calibration path is mainly composed of passive circuits, and has very small power consumption, with the minimum power consumption being only 0.8mW; the noise cancellation loop of the present application is independent of process, voltage and temperature changes, and does not need other calibration.

[0059] As shown in Figure 3 The level shifter comprises a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6 and an inverter; the drain and gate of the first NMOS transistor N1 and the drain and gate of the second NMOS transistor N2 are connected with a power supply VDD; the source of the first NMOS transistor N1 is connected with the drain of the third NMOS transistor N3; the source of the second NMOS transistor N2 is connected with the drain of the fourth NMOS transistor N4; the source of the third NMOS transistor N3 is connected with the drain of the fifth NMOS transistor N5 and the gate of the fourth NMOS transistor N4; the source of the fourth NMOS transistor N4 is connected with the gate of the third NMOS transistor N3, the drain of the sixth NMOS transistor N6 and the output end of the level shifter; the source of the fourth NMOS transistor N4 is connected with the drain of the sixth NMOS transistor N6 and the output end of the level shifter; the input end of the level shifter is connected with the gate of the fifth NMOS transistor N5 and the input end of the inverter; the output end of the inverter is connected with the gate of the sixth NMOS transistor N6; the source of the fifth NMOS transistor N5 and the source of the sixth NMOS transistor N6 are both grounded.

[0060] In some embodiments of the present application, the level shifter is a level shifting circuit based on Wilson current mirror, which uses current mirror to limit the current, thereby weakening the pull-up ability of the pull-up tube when discharging the output node, while avoiding the extra power consumption caused by large constant current; the level shifter moves the error signal with common-mode level of zero extracted by the sub-sampling phase discriminator to the common-mode level suitable for the operation of the variable gain amplifier.

[0061] The variable gain amplifier comprises a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a first resistor R1, a second resistor R2 and a current source; one end of the first resistor R1 is connected to a power supply, and the other end thereof is connected to a drain of the seventh NMOS transistor N7, a drain of the ninth NMOS transistor N9 and an output end of the variable gain amplifier; one end of the second resistor R2 is connected to the power supply, and the other end thereof is connected to a drain of the eighth NMOS transistor N8 and a drain of the tenth NMOS transistor N10; a first input end of the variable gain amplifier is connected to a gate of the seventh NMOS transistor N7, a gate of the eighth NMOS transistor N8, a gate of the ninth NMOS transistor N9 and a gate of the tenth NMOS transistor N10; a drain of the eleventh NMOS transistor N11 is connected to a source of the eighth NMOS transistor N8 and a source of the ninth NMOS transistor N9; a drain of the twelfth NMOS transistor N12 is connected to a source of the seventh NMOS transistor N7 and a source of the tenth NMOS transistor N10; a positive input end of a second input end of the variable gain amplifier is connected to a gate of the eleventh NMOS transistor N11, and a negative input end of the second input end of the variable gain amplifier is connected to a gate of the twelfth NMOS transistor N12; an input end of the current source is connected to a source of the eleventh NMOS transistor N11 and a source of the twelfth NMOS transistor N12; and an output end of the current source is grounded.

[0062] In some embodiments of the present application, the variable gain amplifier is based on the structure of Gilbert cell, and the gain thereof is controlled by a calibration path, which not only significantly improves the gain adjustment range, nonlinear distortion, noise suppression, bandwidth expansion and the like, but also provides a wider dynamic range, and is suitable for a high-precision circuit such as a phase-locked loop.

[0063] As Figure 4As shown, the mixer comprises a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a first capacitor C1 and a second capacitor C2; a first input end of the mixer is connected to a drain of the thirteenth NMOS transistor N13 and a drain of the fifteenth NMOS transistor N15; a second input end of the mixer is connected to a gate of the thirteenth NMOS transistor N13 and a gate of the sixteenth NMOS transistor N16; a third input end of the mixer is connected to a gate of the fourteenth NMOS transistor N14 and a gate of the fifteenth NMOS transistor N15; a fourth input end of the mixer is connected to a drain of the fourteenth NMOS transistor N14 and a drain of the sixteenth NMOS transistor N16; one end of the first capacitor C1 is grounded, and the other end thereof is connected to a source of the thirteenth NMOS transistor N13 and a source of the fourteenth NMOS transistor N14, and is a first output end of the mixer; one end of the second capacitor C2 is grounded, and the other end thereof is connected to a source of the fifteenth NMOS transistor N15 and a source of the sixteenth NMOS transistor N16, and is a second output end of the mixer.

[0064] In some embodiments of the present application, the mixer is a Gilbert cell structure mixer, which can better suppress unwanted signal components and further reduce the noise figure, has high linearity and wide dynamic frequency conversion range, and can maintain stable performance under different signal intensities.

[0065] The band-pass filter comprises a first-stage trans-impedance amplifier, a second-stage trans-impedance amplifier, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a third resistor R3 and a fourth resistor R4; a positive input end of the second-stage trans-impedance amplifier is a positive input end of the band-pass filter, and a negative input end of the second-stage trans-impedance amplifier is a negative input end of the band-pass filter; one end of the fifth capacitor C5 is grounded, and the other end of the fifth capacitor C5 is connected with a negative input end of the first-stage trans-impedance amplifier and a negative output end of the second-stage trans-impedance amplifier; one end of the sixth capacitor C6 is grounded, and the other end of the sixth capacitor C6 is connected with a positive input end of the first-stage trans-impedance amplifier and a positive output end of the second-stage trans-impedance amplifier; a positive output end of the first-stage trans-impedance amplifier is a positive output end of the band-pass filter and is connected with a positive input end of a second input end of the variable gain amplifier, and a negative output end of the first-stage trans-impedance amplifier is a negative output end of the band-pass filter and is connected with a negative input end of the second input end of the variable gain amplifier; a positive input end of an operational amplifier is connected with the positive input end of the band-pass filter, and a negative input end of the operational amplifier is connected with the negative input end of the band-pass filter; a positive output end of the operational amplifier is connected with the positive output end of the band-pass filter, and a negative output end of the operational amplifier is connected with the negative output end of the band-pass filter; one end of the third capacitor C3 is connected with the positive input end of the operational amplifier, and the other end of the third capacitor C3 is connected with the positive output end of the operational amplifier; one end of the third resistor R3 is connected with the positive input end of the operational amplifier, and the other end of the third resistor R3 is connected with the positive output end of the operational amplifier; one end of the fourth capacitor C4 is connected with the negative input end of the operational amplifier, and the other end of the fourth capacitor C4 is connected with the negative output end of the operational amplifier; one end of the fourth resistor R4 is connected with the negative input end of the operational amplifier, and the other end of the fourth resistor R4 is connected with the negative output end of the operational amplifier.

[0066] In some embodiments of the present application, the band-pass filter is an active filter of Gm-C structure, which replaces the resistance with a trans-impedance amplifier and replaces the voltage signal with a current signal, thereby avoiding the significant static power consumption caused by the large resistance and greatly reducing the power consumption.

[0067] The sub-sampling phase-locked loop comprises a frequency-locked loop and a sub-sampling phase-locked loop; the sub-sampling phase-locked loop is used for realizing phase locking, and the frequency-locked loop is used for realizing frequency locking; in the process of locking the signal of the sub-sampling phase-locked loop, the frequency locking is completed first, and then the phase locking is completed.

[0068] Specifically, the sub-sampling phase-locked loop comprises a ring oscillator, a sub-sampling phase detector, a trans-impedance amplifier, a low-pass filter and a buffer; an input end of the sub-sampling phase detector is connected with a reference signal and a third output end of the ring oscillator, an output end of the sub-sampling phase detector is connected with an input end of the trans-impedance amplifier and an input end of a level shifter, an output end of the trans-impedance amplifier is connected with an input end of the low-pass filter, an output end of the low-pass filter is connected with an input end of the ring oscillator, and a second output end of the ring oscillator is connected with the buffer; a first output end, a second output end, a third output end and a fourth output end of the ring oscillator are first output end, a second output end, a third output end and a fourth output end of the sub-sampling phase-locked loop.

[0069] The frequency-locked loop comprises a frequency discriminator, a charge pump and a frequency divider; an input end of the frequency divider is connected with the fourth output end of the ring oscillator, an input end of the frequency discriminator is connected with the reference signal and an output end of the frequency divider, an output end of the frequency discriminator is connected with an input end of the charge pump, an output end of the charge pump is connected with an input end of the low-pass filter, and the frequency divider, the frequency discriminator, the charge pump, the low-pass filter and the ring oscillator form the frequency-locked loop.

[0070] When the sub-sampling phase-locked loop is in phase locking, the phase noise signal generated by the ring oscillator is extracted at the output end of the sub-sampling phase detector and the output end of the ring oscillator for a noise cancellation path and a calibration path, the noise signal is fed forward to the input end of the ring oscillator through the noise cancellation path, and the noise signal fed forward by the noise cancellation path is superimposed with the noise signal inherent in the input end of the ring oscillator.

[0071] In some embodiments of the present application, the phase and frequency locking of the sub-sampling phase-locked loop are realized by the sub-sampling phase-locked loop and the frequency-locked loop; the frequency-locked loop and the sub-sampling phase-locked loop work simultaneously, the frequency is locked first, then the phase is locked, at this time, the frequency-locked loop enters a stable state, the sub-sampling phase-locked loop performs phase tracking and finally realizes phase locking; in the sub-sampling phase-locked loop, the sub-sampling phase detector implements sub-sampling on the oscillator output signal by means of a low-frequency reference signal, and converts the phase error between the reference signal and the oscillator output signal into a voltage signal; the voltage signal containing phase error information is converted into a current signal through the trans-impedance amplifier, and then a smooth voltage signal is generated through the low-pass filter, so as to accurately adjust the phase of the ring oscillator output signal and ensure phase locking; at the same time of phase locking, the random fluctuation of the ring oscillator zero-crossing point caused by the phase noise makes the sampling voltage of the sub-sampling phase detector randomly fluctuate around zero; and then the level shifter in the noise cancellation path effectively extracts the phase noise signal from the output of the sampling phase detector, and the mixer in the calibration path effectively extracts the phase noise signal from the output of the ring oscillator.

[0072] The low-jitter sub-sampling phase-locked loop based on the feedforward phase noise cancellation technology adopts 28nm CMOS technology, the sub-sampling phase-locked loop adopts 0.8V power supply, the frequency is 2.4GHz, and the power consumption is 7.5mW. The noise cancellation path and the calibration path consume 0.9mW and 0.8mW respectively. For the out-of-band phase noise contributed by the ring oscillator, the feedforward noise cancellation technology reduces the phase noise at 2.1MHz frequency offset by 9.2dB, and the power consumption only increases by 1.7mW, which proves the excellent performance and power efficiency improvement of the sub-sampling phase-locked loop based on the feedforward phase noise cancellation technology.

[0073] The above embodiments are preferred examples for implementing the present application, and the present application is not limited to the above embodiments. Any non-essential addition, replacement made by the person skilled in the art according to the technical features of the technical scheme of the present application shall fall within the protection scope of the present application.

Claims

1. A low-jitter sub-sampling phase-locked loop based on feed-forward phase noise cancellation technique, characterized in that, The application relates to a phase-locked loop (PLL) circuit, which comprises: a sub-sampling phase-locked loop; a noise cancellation path, which comprises a level shifter and a variable gain amplifier, the input end of the level shifter being connected with the sub-sampling phase-locked loop, the output end of the level shifter being connected with the first input end of the variable gain amplifier, and the level shifter being used for extracting a phase noise signal output by the sub-sampling phase-locked loop and performing level conversion; the variable gain amplifier being used for amplifying the phase noise signal after level conversion and outputting the noise signal to the sub-sampling phase-locked loop; a calibration path, the input end of which being connected with the first output end, the second output end, the third output end and the fourth output end of the sub-sampling phase-locked loop, and the output end of the calibration path outputting a control signal to the variable gain amplifier; the calibration path comprises a polyphase filter, a mixer, a band-pass filter and an operational amplifier; the input end of the polyphase filter is connected with the first output end, the second output end, the third output end and the fourth output end of the sub-sampling phase-locked loop; the polyphase filter is used for making the output signal thereof be in quadrature phase; the first input end, the second input end, the third input end and the fourth input end of the mixer are respectively connected with the first output end, the second output end, the third output end and the fourth output end of the polyphase filter; the mixer is used for extracting the phase noise signal output by the sub-sampling phase-locked loop and performing frequency mixing; the positive input end of the band-pass filter is connected with the first output end of the mixer, and the negative input end of the band-pass filter is connected with the second output end of the mixer; the band-pass filter is used for filtering out the frequency of the output of the mixer which is not needed; the operational amplifier is connected with the band-pass filter in parallel, the output end of the operational amplifier is connected with the second input end of the variable gain amplifier, and the output end of the operational amplifier outputs the control signal; the noise cancellation path and the calibration path extract the phase noise signal output by the sub-sampling phase-locked loop while the sub-sampling phase-locked loop is in phase locking; after the phase noise signal is converted in level and amplified by the noise cancellation path, the noise signal is fed forward to the sub-sampling phase-locked loop and superimposed with the noise signal inherent in the sub-sampling phase-locked loop, so as to complete the phase noise compensation of the sub-sampling phase-locked loop and realize the phase noise cancellation; the calibration path generates the control signal for adjusting the variable gain amplifier by sequentially performing frequency mixing, filtering and amplifying the phase noise signal, so as to realize the gain self-calibration of the noise signal.

2. The low-jitter sub-sampling phase-locked loop based on the feedforward phase noise cancellation technique according to claim 1, characterized in that, The level shifter comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and an inverter. The drain and gate of the first NMOS transistor and the drain and gate of the second NMOS transistor are connected to a power supply; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the fourth NMOS transistor; The source of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the sixth NMOS transistor and the output of the level shifter; the input of the level shifter is connected to the gate of the fifth NMOS transistor and the input of the inverter; the output of the inverter is connected to the gate of the sixth NMOS transistor; the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to ground.

3. The low-jitter sub-sampling phase-locked loop based on the feedforward phase noise cancellation technique according to claim 1, characterized in that, The variable gain amplifier comprises a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a first resistor, a second resistor and a current source; One end of the first resistor is connected to a power supply, and the other end is connected to the drain of the seventh NMOS transistor, the drain of the ninth NMOS transistor and the output of the variable gain amplifier; One end of the second resistor is connected to a power supply, and the other end is connected to the drain of the eighth NMOS transistor and the drain of the tenth NMOS transistor; The first input of the variable gain amplifier is connected to the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor; the drain of the eleventh NMOS transistor is connected to the source of the eighth NMOS transistor and the source of the ninth NMOS transistor; The drain of the twelfth NMOS transistor is connected to the source of the seventh NMOS transistor and the source of the tenth NMOS transistor; The positive input of the second input of the variable gain amplifier is connected to the gate of the eleventh NMOS transistor, and the negative input of the second input of the variable gain amplifier is connected to the gate of the twelfth NMOS transistor; the input of the current source is connected to the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor; The output of the current source is connected to ground.

4. The low-jitter sub-sampling phase-locked loop based on feedforward phase noise cancellation technology according to claim 1, characterized in that, The mixer comprises a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a first capacitor and a second capacitor; The first input end of the mixer is connected with the drain of the thirteenth NMOS transistor and the drain of the fifteenth NMOS transistor; the second input end of the mixer is connected with the gate of the thirteenth NMOS transistor and the gate of the sixteenth NMOS transistor; the third input end of the mixer is connected with the gate of the fourteenth NMOS transistor and the gate of the fifteenth NMOS transistor; and the fourth input end of the mixer is connected with the drain of the fourteenth NMOS transistor and the drain of the sixteenth NMOS transistor. One end of the first capacitor is grounded, and the other end of the first capacitor is connected with the source of the thirteenth NMOS transistor and the source of the fourteenth NMOS transistor, and is the first output end of the mixer; one end of the second capacitor is grounded, and the other end of the second capacitor is connected with the source of the fifteenth NMOS transistor and the source of the sixteenth NMOS transistor, and is the second output end of the mixer.

5. The low-jitter sub-sampling phase-locked loop based on feed-forward phase noise cancellation technique of claim 1, wherein, The band-pass filter comprises a first-stage trans-impedance amplifier, a second-stage trans-impedance amplifier, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a third resistor and a fourth resistor; The positive input end of the second-stage trans-impedance amplifier is the positive input end of the band-pass filter, and the negative input end of the second-stage trans-impedance amplifier is connected with the negative input end of the band-pass filter; One end of the fifth capacitor is grounded, and the other end of the fifth capacitor is connected with the negative input end of the first-stage trans-impedance amplifier and the negative output end of the second-stage trans-impedance amplifier; one end of the sixth capacitor is grounded, and the other end of the sixth capacitor is connected with the positive input end of the first-stage trans-impedance amplifier and the positive output end of the second-stage trans-impedance amplifier; The positive output end of the first-stage trans-impedance amplifier is the positive output end of the band-pass filter, and the negative output end of the first-stage trans-impedance amplifier is the negative output end of the band-pass filter; The positive input end of the operational amplifier is connected with the positive input end of the band-pass filter, and the negative input end of the operational amplifier is connected with the negative input end of the band-pass filter; the positive output end of the operational amplifier is connected with the positive output end of the band-pass filter, and the negative output end of the operational amplifier is connected with the negative output end of the band-pass filter; One end of the third capacitor is connected with the positive input end of the operational amplifier, and the other end of the third capacitor is connected with the positive output end of the operational amplifier; one end of the third resistor is connected with the positive input end of the operational amplifier, and the other end of the third resistor is connected with the positive output end of the operational amplifier; one end of the fourth capacitor is connected with the negative input end of the operational amplifier, and the other end of the fourth capacitor is connected with the negative output end of the operational amplifier; one end of the fourth resistor is connected with the negative input end of the operational amplifier, and the other end of the fourth resistor is connected with the negative output end of the operational amplifier.

6. The low-jitter sub-sampling phase-locked loop based on feed-forward phase noise cancellation technique of claim 1, wherein, The sub-sampling phase-locked loop comprises a frequency-locked loop and a sub-sampling phase-locked loop; the sub-sampling phase-locked loop is used for realizing phase locking, and the frequency-locked loop is used for realizing frequency locking; in the signal locking process of the sub-sampling phase-locked loop, the frequency locking is completed first, and then the phase locking is completed.

7. A low-jitter sub-sampling phase-locked loop based on feed-forward phase noise cancellation technology according to claim 6, characterized in that, The sub-sampling phase-locked loop comprises a ring oscillator, a sub-sampling phase discriminator, a trans-impedance amplifier, a low-pass filter and a buffer. The input end of the sub-sampling phase detector is connected with a reference signal and a third output end of the ring oscillator, the output end of the sub-sampling phase detector is connected with an input end of the trans-impedance amplifier and an input end of the level shifter, the output end of the trans-impedance amplifier is connected with an input end of the low-pass filter, the output end of the low-pass filter is connected with an input end of the ring oscillator, and a second output end of the ring oscillator is connected with the buffer; The first output end, the second output end, the third output end and the fourth output end of the ring oscillator are the first output end, the second output end, the third output end and the fourth output end of the sub-sampling phase-locked loop.

8. A low-jitter sub-sampling phase-locked loop based on feed-forward phase noise cancellation technology according to claim 7, characterized in that, When the sub-sampling phase-locked loop is in phase locking, the phase noise signal generated by the ring oscillator is extracted at the output end of the sub-sampling phase detector and the output end of the ring oscillator for the noise cancellation path and the calibration path, the noise signal fed forward by the noise cancellation path is superimposed with the noise signal inherent in the input end of the ring oscillator.

9. The low-jitter sub-sampling phase-locked loop based on the feedforward phase noise cancellation technique according to claim 7, characterized in that, The frequency-locked loop comprises a frequency discriminator, a charge pump and a frequency divider; The input end of the frequency divider is connected with the fourth output end of the ring oscillator, the input end of the frequency discriminator is connected with a reference signal and the output end of the frequency divider, the output end of the frequency discriminator is connected with the input end of the charge pump, the output end of the charge pump is connected with the input end of the low-pass filter, and the frequency divider, the frequency discriminator, the charge pump, the low-pass filter and the ring oscillator form a frequency-locked loop.

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