A method and device for synchronous acquisition and processing of a phased array system, and electronic equipment

Abstract

The application relates to the technical field of communication engineering, and discloses a synchronous acquisition and processing method of a phased array system, wherein the phased array system comprises multiple acquisition channels; delay synchronization is performed on the acquisition channels to achieve a preliminary synchronization state; inter-channel phase synchronization is performed on the acquisition channels in the case that the acquisition channels reach the preliminary synchronization state and further phase synchronization is needed; for a first synchronization consistency requirement, on the basis that the acquisition channels reach the preliminary synchronization state through delay synchronization, a first phase synchronization operation is performed to achieve a first phase synchronization state; for a second synchronization consistency requirement, on the basis that the acquisition channels reach the preliminary synchronization state through delay synchronization, a second phase synchronization operation is performed to achieve a second phase synchronization state. The beneficial effect is that the acquisition channels can be subjected to targeted synchronization operations, and the synchronization degree among the acquisition channels in the phased array system is significantly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic and communication engineering, and particularly relates to a synchronization acquisition and processing method and device of a phased array system and electronic equipment. BACKGROUND

[0002] In the fields of, for example, radio astronomy, radar, ultrasonic detection imaging or meteorological detection, in order to improve the accuracy of observation results, a conventional technology usually increases the number of acquisition channels and synchronously receives and transmits signals through multiple acquisition channels to increase the amount of collected data and improve the quality of collected signals. A phased array system is an advanced technology for precisely controlling the phases and amplitudes of multiple antenna elements in an array to accurately control electromagnetic wave transmission and reception. The number of acquisition channels in the phased array system can be from dozens to thousands, and these acquisition channels are deployed in different acquisition board cards. The synchronization between the acquisition channels determines whether the observation results are accurate. In actual situations, the synchronization between the acquisition channels is affected by multiple factors, and a single synchronization processing scheme cannot be applied to all application scenarios.

[0003] In the related art, the technical scheme for synchronously processing the phased array system still needs to be improved in terms of application scenarios. SUMMARY

[0004] The present application provides a synchronization acquisition and processing method and device of a phased array system and electronic equipment. According to the application scenarios and corresponding synchronization consistency requirements of each acquisition channel in the phased array system, corresponding channel synchronization operations are performed on each acquisition channel, so that targeted synchronization operations can be performed on the acquisition channels, and the synchronization degree between each acquisition channel in the phased array system is significantly improved.

[0005] In order to achieve the above-mentioned purpose, the main technical scheme adopted by the present application includes:

[0006] In a first aspect, the present application provides a synchronization acquisition and processing method of a phased array system, characterized in that the phased array system includes multiple acquisition channels; and the method includes:

[0007] Delay synchronization is performed on each acquisition channel, so that all acquisition channels of the phased array system reach a preliminary synchronization state;

[0008] In the case where each acquisition channel reaches the preliminary synchronization state and further phase synchronization is required, inter-channel phase synchronization is performed on each acquisition channel; wherein:

[0009] For the first synchronization consistency requirement, on the basis that the delay synchronization makes the acquisition channels reach the preliminary synchronization state, a first phase synchronization operation is performed to make the acquisition channels reach a first phase synchronization state corresponding to the first synchronization consistency requirement;

[0010] For the second synchronization consistency requirement, on the basis that the delay synchronization makes the acquisition channels reach the preliminary synchronization state, a second phase synchronization operation is performed to make the acquisition channels reach a second phase synchronization state corresponding to the second synchronization consistency requirement; wherein the second phase synchronization operation includes a synchronization operation of phase and iterative correction.

[0011] The synchronization acquisition and processing method of the phased array system provided in the embodiments of the present application first performs delay synchronization on the acquisition channels to ensure that the acquisition channels in the phased array system reach a preliminary synchronization state; and on this basis, for the acquisition channels that need to be further phase synchronized, corresponding phase synchronization operations are performed according to the synchronization consistency requirements to make the acquisition channels reach a phase synchronization state corresponding to the synchronization consistency requirements. Compared with the related art, the present application judges the synchronization operation to be used according to the application scenarios of the acquisition channels and the corresponding synchronization consistency requirements, realizes targeted synchronization processing of the acquisition channels, not only effectively reduces the synchronization cost consumed in the synchronization process of the phased array system, improves the synchronization efficiency, but also significantly improves the synchronization degree between the acquisition channels, and provides a reliable synchronization basis for the application of the phased array system.

[0012] Optionally, the first phase synchronization operation is performed by the following steps:

[0013] The phase information of the acquisition channels is calculated, and the inter-channel phase difference between the acquisition channels and a selected reference channel is calculated based on the phase information of the selected reference channel;

[0014] The channel phase adjustment value corresponding to the acquisition channels is determined according to the inter-channel phase difference;

[0015] The NCO initial phase of the acquisition channels is updated using the channel phase adjustment value, and the first phase synchronization operation is completed.

[0016] Optionally, the second phase synchronization operation is performed by the following steps:

[0017] The phase information of the acquisition channels is calculated, and the inter-channel phase difference between the acquisition channels and a selected reference channel is calculated based on the phase information of the selected reference channel;

[0018] It is judged whether the inter-channel phase difference converges or not;

[0019] if converging, ending the iterative correction process of the second phase synchronization operation;

[0020] if not converging, determining a channel phase adjustment value corresponding to each acquisition channel according to the inter-channel phase difference; updating the NCO initial phase of each acquisition channel by using the channel phase adjustment value; repeating the steps of calculating the phase information, the inter-channel phase difference and the convergence judgment until the inter-channel phase difference of each acquisition channel reaches a converging state.

[0021] Optionally, the delay synchronization of each acquisition channel comprises:

[0022] calculating the delay value of each acquisition channel, and unifying the delay values of each acquisition channel to obtain a unified delay value;

[0023] delay configuring each acquisition channel according to the unified delay value, and completing the delay synchronization of each acquisition channel.

[0024] Optionally, the phased array system comprises a timing control board, a frequency synthesis board and an acquisition board card; the timing control board is connected with the acquisition board card through a first connection cable, and all the first connection cables require stable phase and strict equal length;

[0025] the frequency synthesis board is connected with the timing control board and the acquisition board card through a second connection cable respectively, and all the second connection cables require stable phase and strict equal length.

[0026] Optionally, the frequency synthesis board sends a reference clock signal with the same source, high stability and phase reference to the timing control board and the acquisition board card; the acquisition board card comprises the plurality of acquisition channels; the method further comprises:

[0027] taking the reference clock signal as a clock reference, sending a synchronization control pulse signal to the acquisition board card through the timing control board to trigger the phased array system to perform subsequent synchronization preprocessing of signals.

[0028] Optionally, in the case that the acquisition channel reaches a preset synchronization state, ending the synchronization process of the phased array system, and the preset synchronization state comprises the preliminary synchronization state.

[0029] The acquisition board card adopts a first type board card, the first type board card does not have a digital quadrature demodulation function, and the acquisition channel in the first type board card does not need to be further phase synchronized.

[0030] The number of the first type board cards is N, and the N is a positive integer.

[0031] Optionally, in a case where the acquisition channels reach a preset synchronization state, ending the synchronization process of the phased array system, the preset synchronization state includes the preliminary synchronization state and a target phase synchronization state; the target phase synchronization state is a first phase synchronization state or a second phase synchronization state.

[0032] The acquisition board card adopts a second type board card, the second type board card has a digital quadrature demodulation function, and the inter-channel phase difference of each acquisition channel in the second type board card does not converge, and further phase synchronization needs to be performed.

[0033] The number of the second type board cards is N, and the N is a positive integer.

[0034] In a second aspect, an embodiment of the present application provides a synchronization acquisition and processing device of a phased array system, characterized in that the phased array system includes a plurality of acquisition channels; the device includes:

[0035] A delay synchronization module is configured to perform delay synchronization on each acquisition channel, so that all acquisition channels of the phased array system reach a preliminary synchronization state.

[0036] An inter-channel phase synchronization module is configured to perform inter-channel phase synchronization on each acquisition channel in a case where each acquisition channel reaches the preliminary synchronization state and further phase synchronization is needed; wherein:

[0037] A first phase synchronization unit is configured to perform a first phase synchronization operation on the basis that each acquisition channel reaches the preliminary synchronization state through the delay synchronization, so that each acquisition channel reaches a first phase synchronization state corresponding to a first synchronization consistency requirement.

[0038] A second phase synchronization unit is configured to perform a second phase synchronization operation on the basis that each acquisition channel reaches the preliminary synchronization state through the delay synchronization, so that each acquisition channel reaches a second phase synchronization state corresponding to a second synchronization consistency requirement; wherein the second phase synchronization operation includes a synchronization operation of a phase and an iterative correction.

[0039] In a third aspect, an embodiment of the present application provides an electronic device, including a memory and a processor, which are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method in any one of the above embodiments.

[0040] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the method in any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0042] Figure 1a The use scenario diagram of the synchronous acquisition and processing method of the phased array system provided by the embodiments of the present application is shown in the figure.

[0043] Figure 1b The step diagram of the synchronous acquisition and processing method of the phased array system provided by the embodiments of the present application is shown in the figure.

[0044] Figure 2 The schematic diagram of the synchronous control pulse signal containing a synchronous pulse in the embodiments of the present application is shown in the figure.

[0045] Figure 3 The step diagram of the first phase synchronization operation in the embodiments of the present application is shown in the figure.

[0046] Figure 4 The schematic diagram of the synchronous control pulse signal containing a sampling phase pulse in the embodiments of the present application is shown in the figure.

[0047] Figure 5 The step diagram of the second phase synchronization operation in the embodiments of the present application is shown in the figure.

[0048] Figure 6 The step diagram of the delay synchronization in the embodiments of the present application is shown in the figure.

[0049] Figure 7a The structural block diagram of the phased array system in the embodiments of the present application is shown in the figure.

[0050] Figure 7b The hardware block diagram of the frequency synthesis board in the embodiments of the present application is shown in the figure.

[0051] Figure 7c The hardware block diagram of the timing control board in the embodiments of the present application is shown in the figure.

[0052] Figure 8 The clock tree structure diagram on the acquisition board card in the embodiments of the present application is shown in the figure.

[0053] Figure 9A schematic diagram of a synchronization control pulse signal containing a reset pulse in an embodiment of the present application;

[0054] Figure 10 A module diagram of a synchronization acquisition and processing device of a phased array system provided in an embodiment of the present application;

[0055] Figure 11 A structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0057] In the fields such as radio astronomy, radar, ultrasonic detection imaging, or meteorological detection, to improve the accuracy of observation results, a conventional technology usually increases the number of acquisition channels and synchronously receives and transmits signals through multiple acquisition channels to increase the amount of collected data and improve the quality of collected signals. A phased array system is an advanced technology that precisely controls the phases and amplitudes of multiple antenna elements in an array to accurately control the emission and reception of electromagnetic waves. The number of acquisition channels in a phased array system can vary from several tens to thousands, and these acquisition channels are deployed in different acquisition boards. The synchronization between the acquisition channels determines whether the observation results are accurate. In actual situations, the synchronization between the acquisition channels is affected by multiple factors, and a single synchronization processing scheme cannot be applied to all application scenarios. The adaptive ability of the technical solution for synchronously processing the phased array system in the related art still needs to be improved.

[0058] Based on the above problems, the present application provides a synchronization acquisition and processing method of a phased array system, the phased array system comprising a plurality of acquisition channels; delaying and synchronizing each acquisition channel; in the case that each acquisition channel reaches a preliminary synchronization state and further phase synchronization is required, performing inter-channel phase synchronization on each acquisition channel; wherein: for a first synchronization consistency requirement, on the basis that each acquisition channel reaches a preliminary synchronization state through delay synchronization, a first phase synchronization operation is performed to make each acquisition channel reach a first phase synchronization state; for a second synchronization consistency requirement, on the basis that each acquisition channel reaches a preliminary synchronization state through delay synchronization, a second phase synchronization operation is performed to make each acquisition channel reach a second phase synchronization state.

[0059] The application also provides an embodiment of a synchronous acquisition and processing method of a phased array system. The use scenario of the embodiment is shown in the figure. Figure 1a The embodiment is applicable to a phased array system, which includes a timing control board, an acquisition board card and a frequency synthesis board. The timing control board sends a synchronous control pulse signal to each RFSoC board through an SMA cable. All cables require stable phase, i.e., phase stability, and the cables are strictly equal in length. The frequency synthesis board sends a homologous and phase-referenced 10MHz reference clock to each RFSoC board and the timing control board through an SMA cable. All cables require stable phase, i.e., phase stability, and the cables are strictly equal in length. The PS end of the timing control board is also connected to an upper computer through a gigabit network port. Figure 1a The dashed box in the figure represents a synchronization process performed on the acquisition board card.

[0060] First, the phased array system is powered on for power-on initialization. After the frequency synthesis board is powered on, it does not need to load a program and can always output a 10MHz reference clock signal, providing a high-stable, homologous and phase-referenced clock signal for the acquisition board card and the timing control board. Each acquisition board card performs a program loading and clock module configuration initialization process. The timing control board performs program loading to complete power-on initialization.

[0061] Second, the upper computer sends a synchronization calibration instruction to the phased array system. After receiving the synchronization calibration instruction, the PS end of the timing control board sends a synchronous control pulse signal to each acquisition board card. After receiving the synchronization calibration instruction through the gigabit network port, the PS end of each acquisition board card starts a synchronization process, calculates the delay value of each acquisition channel, and sends the delay value of all channels to the timing control board. The timing control board collects the delay values of all acquisition channels, unifies the delay values of all channels, obtains a unified delay value, and records it as T_total. The timing control board sends the unified delay value to each acquisition board card. Each acquisition board card performs acquisition channel delay configuration according to the received unified delay value, thereby realizing delay synchronization.

[0062] Then, the PL end of each acquisition board card receives the synchronization control pulse signal sent by the timing control board, and analyzes the synchronization control pulse signal to obtain trigger pulses including a synchronization pulse, a reset pulse and a phase sampling pulse. The synchronization pulse is used to ensure that the clock edges of each channel output by each acquisition board card are aligned, the reset pulse is used to perform synchronization processing after the RFdcIP core of the acquisition board card outputs data, and the phase sampling pulse is used to trigger phase synchronization or adaptive calibration. It should be noted that the phased array system corresponds to three use scenarios, and different use scenarios are defined according to the phase convergence threshold. In the first use scenario, the acquisition board card does not have a digital function, the phased array system performs demodulation at the analog end, and this use scenario has the lowest requirement for channel synchronization consistency and only needs to perform delay synchronization. In the second use scenario, the acquisition board card has a digital function, the phased array system performs digital quadrature demodulation on the acquisition board card, and this use scenario has a moderate requirement for channel synchronization consistency. In addition to delay synchronization, phase synchronization is also needed, but the phase does not need to be iteratively corrected. In the third use scenario, the acquisition board card has a digital function, the phased array system performs digital quadrature demodulation on the acquisition board card, and this use scenario has the highest requirement for channel synchronization consistency. In addition to delay synchronization, phase synchronization is also needed, and the phase needs to be iteratively corrected multiple times until the phases of the acquisition channels reach a convergence state.

[0063] For example, the inter-channel phase convergence threshold of the first use scenario can be 30°, and the synchronization process can be completed when the inter-channel phase difference is less than 30°. The inter-channel phase convergence threshold of the second use scenario can be 20°, and the synchronization process can be completed when the inter-channel phase difference is less than 20°. The inter-channel phase convergence threshold of the third use scenario can be 2°, and the synchronization process can be completed when the inter-channel phase difference is less than 2°.

[0064] The phase synchronization can be only one inter-channel phase difference calculation and phase adjustment, which is suitable for the second use scenario. The phase information of each acquisition channel is calculated by the PS end of each acquisition board card and sent to the timing control board. The timing control board collects the phase information of all channels of the phased array system, takes the phase information of the selected reference channel as a reference, calculates the phase difference between all channels, and sends the obtained channel phase adjustment value to each acquisition board card. The PS end of each acquisition board card updates the delay configuration of the initial phase of each channel NCO according to the received channel phase adjustment value, and completes the synchronization process in this use scenario.

[0065] The phase adaptive calibration can include multiple inter-channel phase difference calculation and adjustment iterations to control the inter-channel phase difference within a preset range, so as to achieve a phase convergence state. The phase adaptive calibration is applicable to the third use scenario. The phase information of each acquisition channel is calculated at the PS end of each acquisition board card and sent to the timing control board. The timing control board collects the phase information of all channels of the phased array system, takes the phase information of the selected reference channel as a reference, calculates the inter-channel phase difference of all channels, judges whether the inter-channel phase difference converges, and ends the phase adaptive calibration if the inter-channel phase difference converges. If the inter-channel phase difference does not converge, the channel phase adjustment value is obtained according to the inter-channel phase difference and sent to each acquisition board card. The PS end of each acquisition board card updates the initial phase of the NCO of each channel according to the received channel phase adjustment value. After the update, the phase information of each acquisition channel is recalculated and sent to the timing control board. The timing control board collects the phase information of all channels of the phased array system, takes the phase information of the selected reference channel as a reference, calculates the inter-channel phase difference of all channels, and judges whether the inter-channel phase difference converges. Repeat the above process until the inter-channel phase difference converges.

[0066] The synchronization acquisition and processing method of the phased array system provided in the present application first synchronizes the delay of each acquisition channel to ensure that the acquisition channels in the phased array system achieve a preliminary synchronization state. On this basis, for acquisition channels that need further phase synchronization, the corresponding phase synchronization operation is performed according to the synchronization consistency requirement, so that each acquisition channel reaches the phase synchronization state corresponding to the synchronization consistency requirement.

[0067] Compared with related technologies, the present application judges the synchronization operation to be used according to the application scenario and the corresponding synchronization consistency requirement of each acquisition channel, realizes targeted synchronization processing of the acquisition channel, not only effectively reduces the synchronization cost consumed in the synchronization process of the phased array system, improves the synchronization efficiency, but also significantly improves the synchronization degree between each acquisition channel, and provides a reliable synchronization basis for the application of the phased array system.

[0068] The synchronization acquisition and processing method of the phased array system provided in the present application can be applied to the phased array system, which can be used in the fields of radio astronomy, radar, ultrasonic detection imaging, meteorological detection and other fields. In the field of radio astronomy, the phased array system can be used to build a phased array radio telescope to realize high-speed, real-time and synchronous acquisition and preprocessing of large-scale and wide-band radio frequency signals. It can be understood that after adaptive modification, the synchronization acquisition and processing method of the phased array system provided in the present application can also be used for synchronous processing of other devices that acquire signals through multiple channels.

[0069] According to the embodiment of the present application, a method for synchronous acquisition and processing of a phased array system is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0070] In the present embodiment, a method for synchronous acquisition and processing of a phased array system is provided, which can be used in the phased array system described above. Referring to Figure 1b As shown, the phased array system includes a plurality of acquisition channels; the method includes:

[0071] S100. Delay synchronization is performed on each acquisition channel, so that all acquisition channels of the phased array system reach a preliminary synchronization state.

[0072] S200. In the case that each acquisition channel reaches the preliminary synchronization state and further phase synchronization is required, inter-channel phase synchronization is performed on each acquisition channel; wherein:

[0073] S300. For the first synchronization consistency requirement, on the basis of the preliminary synchronization state reached by each acquisition channel through delay synchronization, a first phase synchronization operation is performed, so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement.

[0074] S400. For the second synchronization consistency requirement, on the basis of the preliminary synchronization state reached by each acquisition channel through delay synchronization, a second phase synchronization operation is performed, so that each acquisition channel reaches a second phase synchronization state corresponding to the second synchronization consistency requirement; wherein, the second phase synchronization operation includes a synchronization operation of phase and iterative correction.

[0075] The preliminary synchronization state can be a state in which all acquisition channels in the phased array system are configured with the same delay value, so as to ensure that each acquisition channel can be aligned in time, and improve the timing synchronization of the phased array system in the process of signal acquisition and processing. It can be understood that after reaching the preliminary synchronization state, the acquisition signals in each acquisition channel can be synchronized to enter the ready output state after the same delay value, so as to realize the synchronous output of the multi-channel signals in the phased array system, and significantly improve the synchronization in the phased array system.

[0076] The first synchronization consistency requirement and the second synchronization consistency requirement can be different synchronization thresholds for synchronization consistency of the acquisition channels in the phased array system, and the synchronization threshold of the second synchronization consistency requirement can be higher than the synchronization threshold of the first synchronization consistency requirement. In some embodiments, in addition to the first synchronization consistency requirement and the second synchronization consistency requirement, there can be a third synchronization consistency requirement, and the synchronization threshold of the third synchronization consistency requirement can be lower than the synchronization threshold of the first synchronization consistency requirement. To illustrate the difference between the multiple synchronization consistency requirements, according to the clock period of the acquisition signal, the synchronization error between the acquisition channels is divided into an integer part containing a complete clock period and a decimal part containing a partial clock period, and then the first synchronization consistency requirement and the second synchronization consistency requirement can be requirements focusing on the decimal part of the synchronization error, and the third synchronization consistency requirement can be a requirement focusing on the integer part of the synchronization error, and in some cases the phase difference between the acquisition channels can directly meet the synchronization threshold of the third synchronization consistency requirement. For example, the synchronization threshold of the first synchronization consistency requirement can be a 20° inter-channel phase difference, the synchronization threshold of the second synchronization consistency requirement can be a 3° inter-channel phase difference, and the synchronization threshold of the third synchronization consistency requirement can be a 30° inter-channel phase difference.

[0077] The first phase synchronization operation can be an operation process of synchronizing the phases of the acquisition channels to meet the first synchronization consistency requirement, so that the acquisition channels reach a first phase synchronization state. The first phase synchronization state can be a state in which all acquisition channels in the phased array system correspond to the same phase, so as to ensure that the acquisition channels can be aligned in phase, and the synchronization degree between the acquisition channels in the first phase synchronization state corresponds to the synchronization threshold of the first synchronization consistency requirement. Similarly, the second phase synchronization operation can be an operation process of synchronizing the phases of the acquisition channels to meet the second synchronization consistency requirement, so that the acquisition channels reach a second phase synchronization state. The second phase synchronization state can be a state in which all acquisition channels in the phased array system correspond to the same phase, so as to ensure that the acquisition channels can be aligned in phase, and the synchronization degree between the acquisition channels in the second phase synchronization state corresponds to the synchronization threshold of the second synchronization consistency requirement.

[0078] Specifically, before starting the synchronization process of the phased array system, the phased array system is powered on and initialized to ensure that the phased array system can work normally and be ready for the synchronization process. After the power-on initialization is completed, the host computer sends a synchronization calibration instruction to the phased array system to start the synchronization process of the phased array system.

[0079] It should be noted that the plurality of acquisition channels in the phased array system can be integrated on one or more acquisition board cards, a single clock chip is used to build a synchronous clock tree on each acquisition board card, and the plurality of acquisition channels on the acquisition board card are synchronized by the plurality of clock signals sent by the synchronous clock tree. Therefore, the synchronization between the plurality of clock signals in the synchronous clock tree has an important influence on the synchronization process. Based on the above reasons, the synchronous control pulse signal containing the synchronization pulse is sent to the acquisition board card in the phased array system, and the clock chip on the acquisition board card is triggered by the synchronization pulse to synchronize and reset the plurality of output pins of the clock chip, so that the clock chip can synchronously output the plurality of clock signals, improve the synchronization between the plurality of clock signals, and further provide a synchronization signal basis for the subsequent synchronization process.

[0080] The synchronous control pulse signal can be a pulse signal containing different types of trigger pulses for triggering each acquisition channel to control the synchronization processing of each acquisition channel. Different types of trigger pulses can correspond to different pulse widths. Figure 2 As shown in FIG. 8, the synchronization pulse can be a trigger pulse with a third pulse width, and the third pulse width corresponds to a pulse width of 3 clock cycles. After receiving the synchronization pulse, the clock chip is triggered to perform clock synchronization reset.

[0081] Further, the synchronization error between the acquisition channels can include a delay error and a phase error. The delay error can be an error that constitutes an integer part of the synchronization error, and the phase error can be an error that constitutes a decimal part of the synchronization error. It can be understood that, in order to minimize the synchronization error between the acquisition channels and improve the synchronization between the acquisition channels, delay synchronization needs to be performed on each acquisition channel under any synchronization consistency requirement to eliminate the influence of the delay error on the synchronization between the acquisition channels.

[0082] After the clock chip on the acquisition board card can synchronously output the plurality of clock signals, the clock chip sends a synchronous analog clock signal and a synchronous logic clock signal to each acquisition channel on the acquisition board card to perform delay synchronization on each acquisition channel by the synchronous analog clock signal and the synchronous logic clock signal. Each acquisition channel on each acquisition board card is configured with the same delay value to eliminate the timing deviation between the acquisition channels, so that all acquisition channels of the phased array system reach a preliminary synchronization state. It should be noted that the synchronous analog clock signal and the synchronous logic clock signal can be low-frequency clock signals. The synchronous analog clock signal is used for clock alignment of the analog signal part of the acquisition board card, and the synchronous logic clock signal is used for clock alignment of the programmable logic part of the acquisition board card. The synchronous analog clock signal and the synchronous logic clock signal have the same clock frequency, and the phase relationship between them is constant.

[0083] Further, on the basis of all the acquisition channels reaching the preliminary synchronization state, it is judged whether the acquisition channels meet the synchronization consistency requirement corresponding to the current application scenario. If the current application scenario corresponds to the third synchronization consistency requirement, at this time the acquisition channels have reached the synchronization degree required by the current application scenario, and the synchronization processing of the phased array system can be stopped. If the current application scenario corresponds to the first synchronization consistency requirement or the second synchronization consistency requirement, and the synchronization states corresponding to the first synchronization consistency requirement and the second synchronization consistency requirement also include the corresponding phase synchronization state, at this time the acquisition channels do not reach the synchronization degree required by the current application scenario, and further phase synchronization needs to be performed.

[0084] In the case where the current application scenario corresponds to the first synchronization consistency requirement, for the first synchronization consistency requirement, the first phase synchronization operation is performed on the acquisition channels that have reached the preliminary synchronization state, so as to align the phases of the acquisition channels, eliminate the phase difference between the acquisition channels, and make the acquisition channels reach the first phase synchronization state corresponding to the first synchronization consistency requirement.

[0085] In the case where the current application scenario corresponds to the second synchronization consistency requirement, for the second synchronization consistency requirement, the second phase synchronization operation is performed on the acquisition channels that have reached the preliminary synchronization state, so as to align the phases of the acquisition channels, eliminate the phase difference between the acquisition channels, and make the acquisition channels reach the second phase synchronization state corresponding to the second synchronization consistency requirement. The second phase synchronization operation includes the synchronization operation of the phase and the iterative correction. It should be noted that since the synchronization threshold of the second synchronization consistency requirement can be higher than that of the first synchronization consistency requirement, after the synchronization operation of the phase is performed on the acquisition channels, the acquisition channels can not reach the second phase synchronization state corresponding to the second synchronization consistency requirement. Therefore, in the second phase synchronization operation process, further phase iterative correction needs to be performed on the acquisition channels on the basis of the synchronization operation of the phase. By repeatedly correcting the phase of the acquisition channels, the synchronization degree between the acquisition channels is gradually improved, so that the acquisition channels can reach the second phase synchronization state and reach the synchronization degree required by the current application scenario.

[0086] The synchronization acquisition and processing method of the phased array system provided in the embodiment first performs delay synchronization on the acquisition channels to ensure that the acquisition channels in the phased array system reach the preliminary synchronization state; and on this basis, for the acquisition channels that need to be further phase-synchronized, the corresponding phase synchronization operation is performed according to the synchronization consistency requirement, so that the acquisition channels reach the phase synchronization state corresponding to the synchronization consistency requirement.

[0087] Compared with the related art, the application judges the synchronization operation to be adopted according to the application scene and the corresponding synchronization consistency requirement of each acquisition channel, realizes the targeted synchronization processing of the acquisition channel, effectively reduces the synchronization cost consumed in the synchronization process of the phased array system, improves the synchronization efficiency, significantly improves the synchronization degree between the acquisition channels, and provides a reliable synchronization basis for the application of the phased array system.

[0088] Referring to Figure 3 As shown in FIG. 1, as an embodiment of the application, the first phase synchronization operation is executed by the following steps:

[0089] S310. Calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0090] S320. Determine the channel phase adjustment value corresponding to each acquisition channel according to the inter-channel phase difference.

[0091] S330. Update the NCO initial phase of each acquisition channel using the channel phase adjustment value, and complete the first phase synchronization operation.

[0092] Specifically, the synchronization control pulse signal containing the sampling phase pulse is sent to the acquisition board card in the phased array system, and all acquisition channels on the acquisition board card are triggered by the sampling phase pulse, so that each acquisition channel can calculate and feedback the phase information of itself as the data basis of the first phase synchronization operation. After the phase information of all acquisition channels in the phased array system is calculated, a selected reference channel is determined from all acquisition channels, and the phase difference between the selected reference channel and the remaining acquisition channels is calculated based on the phase information of the selected reference channel, to obtain the inter-channel phase difference between each acquisition channel and the selected reference channel. Referring to Figure 4 As shown in FIG. 2, the sampling phase pulse can be a trigger pulse with a pulse width satisfying a first pulse width condition, and the first pulse width condition corresponds to a pulse width of 1 clock cycle. After receiving the sampling phase pulse, the acquisition board card triggers each acquisition channel to calculate the phase information.

[0093] Further, according to the inter-channel phase difference, the phase compensation calculation is performed on each acquisition channel to determine the channel phase adjustment value corresponding to each acquisition channel. It can be understood that the channel phase adjustment value is used to align the phase information of each acquisition channel with the phase information of the selected reference channel, reduce the phase difference between each acquisition channel and the selected reference channel, and thus improve the phase synchronization between all acquisition channels.

[0094] Further, the channel phase adjustment value is used to update the initial phase of the NCO (Numerically Controlled Oscillator) of each acquisition channel, and the updated initial phase of the NCO is triggered to take effect by the synchronous analog clock signal, to complete the first phase operation. It should be noted that before the updated initial phase of the NCO is triggered to take effect by the synchronous analog clock signal, it is necessary to ensure that each acquisition channel can synchronously receive the synchronous analog clock signal, so as to reduce the synchronization error generated when the synchronous analog clock signal triggers each acquisition channel. Based on the above reasons, the clock signal receiver of each acquisition channel is closed, and each acquisition channel is controlled to synchronously stop receiving the synchronous analog clock signal. The mixing trigger source of each acquisition channel is set to the synchronous analog clock signal, and after the setting is completed, the clock signal receiver of each acquisition channel is opened, and each acquisition channel is controlled to synchronously start receiving the synchronous analog clock signal, so that the synchronous analog clock signal can synchronously trigger each acquisition channel, and the synchronization in the first phase synchronization operation process is improved.

[0095] In some embodiments, the process of triggering the updated initial phase of the NCO to take effect by the synchronous analog clock signal can include: each acquisition channel performs pulse detection on the received synchronous analog clock signal, triggers each acquisition channel based on the rising edge of the pulse signal in the synchronous analog clock signal, so as to activate the initial phase of the NCO in each acquisition channel. At the same time, the number of cycles of the pulse signal is determined based on the rising edge of the pulse signal in the synchronous analog clock signal, and after detecting at least two cycles of the pulse signal, it is determined that the initial phase of the NCO has been activated, the triggering process to take effect is stopped, and the first phase synchronization operation is completed. It can be understood that the degree of synchronization between each acquisition channel at this time meets the synchronization threshold of the first synchronization consistency requirement, and each acquisition channel reaches the first phase synchronization state corresponding to the first synchronization consistency requirement.

[0096] Referring to Figure 5 As shown in FIG. 4, as an embodiment of the present application, the second phase synchronization operation is performed by the following steps:

[0097] S410. Calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0098] S420. Determine whether the inter-channel phase difference converges.

[0099] S430. If the convergence is reached, the iterative correction process of the second phase synchronization operation is ended.

[0100] S440. If not converged, determining a channel phase adjustment value corresponding to each acquisition channel according to the inter-channel phase difference; updating the NCO initial phase of each acquisition channel by using the channel phase adjustment value; repeating the steps of calculating the phase information, the inter-channel phase difference and the convergence judgment until the inter-channel phase difference of each acquisition channel reaches a converged state.

[0101] Specifically, in the phased array system, a synchronization control pulse signal containing a phase acquisition pulse is sent to the acquisition board card, and all acquisition channels on the acquisition board card are triggered by the phase acquisition pulse, so that each acquisition channel can calculate and feed back its own phase information as the data basis of the first phase synchronization operation. After calculating the phase information of all acquisition channels in the phased array system, a selected reference channel is determined from all acquisition channels, and the phase information of the selected reference channel is used as a reference to calculate the phase difference between the remaining acquisition channels and the selected reference channel, thereby obtaining the inter-channel phase difference between each acquisition channel and the selected reference channel.

[0102] In this embodiment, in order to determine whether the synchronization degree between each acquisition channel meets the synchronization threshold of the second synchronization consistency requirement, the inter-channel phase difference is compared with the synchronization threshold of the second synchronization consistency requirement, and whether the inter-channel phase difference converges is determined according to the comparison result. If the inter-channel phase difference of each acquisition channel does not exceed the synchronization threshold of the second synchronization consistency requirement, it is determined that the inter-channel phase difference converges, and at this time, each acquisition channel has reached the second phase synchronization state corresponding to the second synchronization consistency requirement, and the iterative correction process of the second phase synchronization operation is ended.

[0103] If the inter-channel phase difference of each acquisition channel exceeds the synchronization threshold of the second synchronization consistency requirement, it is determined that the inter-channel phase difference does not converge, and the phase of each acquisition channel needs to be iteratively corrected. According to the inter-channel phase difference, the phase compensation calculation is performed on each acquisition channel to determine a channel phase adjustment value corresponding to each acquisition channel. The NCO initial phase of each acquisition channel is updated by using the channel phase adjustment value, and the updated NCO initial phase is triggered to take effect by a synchronization digital clock signal, thereby completing the updating process of the NCO initial phase.

[0104] It should be noted that before the triggering effect of the synchronous analog clock signal is utilized, it is necessary to ensure that each acquisition channel can synchronously receive the synchronous analog clock signal and reduce the synchronization error generated when the synchronous analog clock signal triggers each acquisition channel. Based on the above reasons, the clock signal receiver of each acquisition channel is closed to control each acquisition channel to synchronously stop receiving the synchronous analog clock signal. The mixing trigger source of each acquisition channel is set to the synchronous analog clock signal, and after the setting is completed, the clock signal receiver of each acquisition channel is opened to control each acquisition channel to synchronously start receiving the synchronous analog clock signal, so that the synchronous analog clock signal can synchronously trigger each acquisition channel and improve the synchronization in the second phase synchronization operation process.

[0105] In some embodiments, the process of triggering the updated NCO initial phase by the synchronous analog clock signal to take effect can include: each acquisition channel performs pulse detection on the received synchronous analog clock signal, triggers each acquisition channel based on the rising edge of the pulse signal in the synchronous analog clock signal, thereby activating the NCO initial phase in each acquisition channel. At the same time, the number of cycles of the pulse signal is determined based on the rising edge of the pulse signal in the synchronous analog clock signal, and after detecting at least two cycles of the pulse signal, it is determined that the NCO initial phase has completed updating, and the triggering process to take effect is stopped.

[0106] Further, after the updating of the NCO initial phase is completed, the phase information calculation process of each acquisition channel is iteratively performed, and it is determined whether the inter-channel phase difference between each acquisition channel and the selected reference channel converges. It can be understood that the selected reference channel in each iteration round is the same acquisition channel. If the inter-channel phase difference does not converge, the channel phase adjustment value corresponding to each acquisition channel needs to be further calculated to iteratively correct the NCO initial phase of each acquisition channel.

[0107] The iterative correction process can be represented by the following formula:

[0108]

[0109] wherein i is the number of the acquisition channel; k is the iteration number; is the NCO initial phase of the i-th acquisition channel in the k-th iteration round; is the NCO initial phase of the i-th acquisition channel in the k-1-th iteration round; is the channel phase adjustment value of the i-th acquisition channel in the k-th iteration round. The channel phase adjustment value can be calculated according to the inter-channel phase difference in the current iteration round, to correct the NCO initial phase in the previous iteration round by the channel phase adjustment value, so as to obtain the NCO initial phase in the current iteration round, so that the phase information obtained after digital quadrature demodulation of the i-th acquisition channel is closer to the phase information of the selected reference acquisition channel. The NCO initial phase is updated according to the channel phase adjustment value, so as to correct the phase of each acquisition channel, and reduce or eliminate the phase error between the acquisition channel and the selected reference channel. Through multiple repetition of the steps of calculating the phase information, the inter-channel phase difference and the convergence judgment, the phase information of all acquisition channels is finally aligned, and the phase synchronization between the acquisition channels is improved.

[0110] It can be understood that in any iteration round, if it is determined that the inter-channel phase difference converges, each acquisition channel has reached the second phase synchronization state corresponding to the second synchronization consistency requirement, and the iteration correction process of the second phase synchronization operation can be ended.

[0111] Referring to Figure 6 As shown in FIG. 1, as an embodiment of the present application, the delay synchronization of each acquisition channel includes:

[0112] S210. Calculate the delay value of each acquisition channel, and unify the delay values of each acquisition channel to obtain a unified delay value.

[0113] S220. Delay configuration is performed on each acquisition channel according to the unified delay value, and the delay synchronization of each acquisition channel is completed.

[0114] Specifically, the synchronous analog clock signal and the synchronous logic clock signal are received by the control of each acquisition channel, the analog signal part of the acquisition board card is clocked by using the synchronous analog clock signal, and the programmable logic part of the acquisition board card is clocked by using the synchronous logic clock signal. After clocking, the delay value calculation instruction is issued to each acquisition channel by the programmable logic part of the acquisition board card, so as to calculate the delay value of each acquisition channel.

[0115] Further, the delay values of the acquisition channels are unified to obtain a unified delay value. In some embodiments, if the delay values of the acquisition channels are equal, it indicates that the acquisition channels have been synchronized in time. At this time, the delay value shared by the acquisition channels is taken as the unified delay value to ensure that the acquisition channels are in a preliminary synchronization state through delay configuration, and the delay synchronization of the acquisition channels is completed. If there is a difference between the delay values of the acquisition channels, it indicates that the delay synchronization is needed to reduce the time deviation between the acquisition channels. At this time, the delay values of the acquisition channels are screened, the maximum delay value is selected as the target delay value from all delay values, and the unified delay value is obtained based on the target delay value. Exemplarily, the redundant design can be to increase a plurality of clock cycles based on the target delay value, and the number of the increased clock cycles can be 16.

[0116] Further, after obtaining the unified delay value, the acquisition channels are configured with the unified delay value based on the synchronous analog clock signal as the clock reference, so that all acquisition channels are configured with the same unified delay value, the time deviation between the acquisition channels is eliminated, and all acquisition channels can reach a preliminary synchronization state.

[0117] As an embodiment of the present application, the phased array system includes a timing control board, a frequency synthesis board and acquisition board cards; the timing control board is connected with the acquisition board cards through first connection cables, and all the first connection cables require stable phase and strict equal length; the frequency synthesis board is connected with the timing control board and the acquisition board cards through second connection cables respectively, and all the second connection cables require stable phase and strict equal length.

[0118] Referring to Figure 7a The phased array system includes a timing control board, a frequency synthesis board and acquisition board cards, and the acquisition board cards are integrated with acquisition channels. The number of the acquisition board cards can be one or more. The output end of the frequency synthesis board is connected with the input end of the timing control board and the input end of the acquisition board cards through second connection cables respectively, the output end of the timing control board is connected with the input end of the acquisition board cards through first connection cables, and the timing control board and the acquisition board cards are connected in a direct coupling manner to reduce signal glitches and improve signal transmission quality. It should be noted that all the first connection cables require stable phase and strict equal length, so that the clock signals outputted by the frequency synthesis board to the timing control board and the acquisition board cards are in phase and stable. Similarly, all the second connection cables require stable phase and strict equal length, so that the clock signals outputted by the frequency synthesis board to the acquisition board cards are in phase and stable

[0119] The frequency synthesis board is used to generate a homologous, high-stable and phase-referenced reference clock signal, and output the reference clock signal to the timing control board, so that the timing control board controls the collection board card according to the reference clock signal. The frequency synthesis board also sends the reference clock signal to the collection board card, so that the collection board card can use the reference clock signal as a signal to synchronize the processing. It can be understood that the clock signal output by the single frequency synthesis board effectively reduces the timing error between the clock signals generated by different clock sources, and improves the timing consistency and stability of the multi-channel clock signal. In addition, the single frequency synthesis board also simplifies the hardware design in the phased array system, reduces the hardware complexity of the phased array system, and improves the hardware stability and use convenience of the phased array system.

[0120] Exemplarily, referring to Figure 7b As shown in the figure, the frequency synthesis board can be a board card including one rubidium atomic clock frequency standard source and two 1 / 16 frequency standard distributors. The rubidium atomic clock frequency standard source has a GPS Beidou satellite taming function and can receive GPS Beidou satellite signals, so that the rubidium oscillator outputs a frequency synchronized with the clock signal of the GPS Beidou satellite signal, thereby providing a cesium atomic clock level high-precision time frequency signal. The clock signal output by the rubidium atomic clock frequency standard source passes through two 1 / 16 frequency standard distributors respectively, and a plurality of clock signals are obtained to provide stable reference clock signals for a plurality of collection board cards respectively, thereby ensuring the stable and synchronous operation of the collection board cards.

[0121] The timing control board is used to generate a synchronous control pulse signal, and after receiving the reference clock signal output by the frequency synthesis board, the timing control board outputs the synchronous control pulse signal to each collection board card as a clock reference, and controls each collection board card to perform corresponding operations. The timing control board is connected with the collection board card through a separate first connection cable and sends signals, and also effectively reduces the number of wirings between the timing control board and the collection board card, reduces the complexity of the phased array system, and improves the reliability of the phased array system.

[0122] Exemplarily, referring to Figure 7cAs shown, the timing control board can be a board card including a Zynq SoC series FPGA module, a KU series pure PL FPGA module, and an input end, etc. The input end is used to receive a reference clock signal output by the frequency synthesis board, and send the reference clock signal to the Zynq SoC series FPGA module and the KU series pure PL FPGA module as a clock reference of the two. The Zynq SoC series FPGA module is in communication connection with the upper computer or the plurality of acquisition board cards, so as to realize interaction of signal data between the Zynq SoC series FPGA module and the upper computer or the plurality of acquisition board cards. For example, the Zynq SoC series FPGA module and the upper computer or the plurality of acquisition board cards can be in communication connection through a PS end gigabit network port. The KU series pure PL FPGA module has an output end connected with the plurality of acquisition board cards respectively, and is used to output a synchronous control pulse signal to each acquisition board card as a clock reference, so as to control the plurality of acquisition board cards synchronously. The Zynq SoC series FPGA module is connected with the KU series pure PL FPGA module, and sends a trigger signal to the KU series pure PL FPGA module based on an instruction issued by the upper computer, so as to trigger the KU series pure PL FPGA module to send the synchronous control pulse signal to the acquisition board card.

[0123] The acquisition board card is used to receive a reference clock signal, and generate a plurality of clock signals for synchronous processing based on the reference clock signal through a clock chip, so as to realize synchronous signal acquisition among the plurality of acquisition board cards. The acquisition board card includes a programmable logic part and a processing system part, wherein: the programmable logic part is provided with an RFDC IP core, and the RFDC IP core includes one or more acquisition channels for signal acquisition. The programmable logic part is also used to receive a synchronous control pulse signal output by the timing control board, and analyze the synchronous control pulse signal, so as to determine a corresponding operation to be performed according to a trigger pulse contained in the synchronous control pulse signal. The processing system part can configure a clock signal of the acquisition board card by calling an API driver software, and start a required logic file. The processing system part is also used to receive information such as a delay reference or a channel phase acquired from the acquisition board card. The processing system part interacts with the programmable logic part through an AXI interface, and sends a signal instruction to the programmable logic part.

[0124] Reference Figure 8As shown, a synchronous clock tree based on a single clock chip can be designed in the acquisition board card, and the hardware structure of the synchronous clock tree includes a clock chip, a PL MMCM frequency divider, a radio frequency clock chip and an RFDC IP core. The RFDC IP core includes a plurality of acquisition channels, represented by an ADC unit. All acquisition channels work in the same working mode and are configured with the same working parameters. The output end of the clock chip is connected with the input end of the radio frequency clock chip, and the output end of the radio frequency clock chip and the output end of the clock chip are respectively connected with the input end of the RFDC IP core. The input end of the PL MMCM frequency divider is connected with the output end of the clock chip.

[0125] The clock chip serves as the basis of the synchronous clock tree, is used to generate a plurality of homologous clock signals, and is sent to a plurality of modules on the acquisition board card to provide clock references for the plurality of modules. The plurality of clock signals includes a synchronous pulse period signal AMS_SYSREF and a logic pulse period signal PL_SYSREF. The clock chip sends the synchronous pulse period signal AMS_SYSREF and the logic pulse period signal PL_SYSREF to the RFDC IP core through the connection with the RFDC IP core for delay synchronization and phase synchronization of each acquisition channel. Exemplarily, the frequency of the synchronous pulse period signal AMS_SYSREF and the logic pulse period signal PL_SYSREF can be 10 MHz.

[0126] It can be understood that the unified output of the plurality of clock signals by the single clock chip reduces the clock drift and error between the plurality of clock signals, and improves the timing consistency between the clock signals in the board. In addition, the single clock chip also simplifies the hardware design on the acquisition board card, reduces the module complexity, and improves the hardware stability and use convenience of the acquisition board card.

[0127] The PL MMCM frequency divider is used to perform frequency division operation on the clock signal output by the clock chip, to generate an ADC parallel data output clock AXIS_clock and a back-end signal processing clock USER_clock, to control the output and processing of the acquisition signal, and to ensure the synchronization between different acquisition signals. The functions of the PL MMCM frequency divider can also include clock frequency conversion, clock phase control, clock frequency division and multiplication, and clock synchronization, etc. It can be understood that the acquisition signal is synchronously output to the RFSoC FPGA processing chip on the acquisition board card to perform signal processing on the acquisition signal. Exemplarily, the frequency of the ADC parallel data output clock AXIS_clock can be 250 MHz, and the frequency of the back-end signal processing clock USER_clock can be 350 MHz.

[0128] The radio frequency clock chip is configured to receive a clock signal transmitted by the clock chip, and obtain a collection clock signal based on the clock signal to be transmitted to the RFDC IP core for synchronization, so as to provide a synchronous clock basis in a signal collection process for the collection channel, so that the collection channel can perform synchronous signal collection. The radio frequency clock chip can obtain the collection clock signal by clock operation on the clock signal. The frequency of the collection clock signal is outside the clock frequency range corresponding to the clock chip, so the clock chip cannot directly generate the collection clock signal for the RFDC IP core. The radio frequency clock chip needs to perform clock operation on the clock signal to generate a collection clock signal that meets the actual needs. Exemplarily, the clock operation can be clock frequency multiplication or clock phase adjustment.

[0129] The RFDC IP core is configured to receive the collection clock signal transmitted by the radio frequency clock chip, and synchronously distribute the collection clock signal to a plurality of collection channels, so that all the collection channels can perform synchronous signal collection based on the collection clock signal. The collection channel can be an analog-to-digital converter (ADC) unit, which converts an analog signal obtained through signal collection into a digital signal for subsequent further signal processing and analysis. Exemplarily, the frequency of the collection clock signal can be 4 GHz.

[0130] As an embodiment of the present application, the frequency synthesis board transmits a reference clock signal with the same source, high stability, and phase reference to the timing control board and the collection board card; the collection board card includes a plurality of collection channels; the method further includes:

[0131] S500. Taking the reference clock signal as a clock reference, the timing control board transmits a synchronous control pulse signal to the collection board card to trigger the phased array system to perform subsequent synchronous preprocessing of signals.

[0132] Specifically, the output ends of the collection channels in the collection board card are connected with the signal processing unit, and the signal processing unit includes a plurality of processing channels. The number of the processing channels is the same as that of the collection channels, and each processing channel corresponds to one collection channel. In order to ensure that the clocks of the processing channels are uniform when the collection signals enter the signal processing unit, the signal processing unit also needs to perform subsequent synchronous preprocessing of signals, so that the processing channels in the signal processing unit are time-synchronous.

[0133] Further, before the collection signals of each collection channel reach the signal processing unit, a synchronization control pulse signal containing a reset pulse is sent to the collection board card, so that each processing channel in the signal processing unit can synchronously receive the synchronization control pulse signal. The synchronization control pulse signal is pulse detected, and after the trigger pulse is detected, its pulse width is measured, and the type of the trigger pulse is determined according to the measurement result. If the type of the trigger pulse is a reset pulse, the rising edge of the reset pulse is taken as a reference point, each processing channel is triggered, and each processing channel is controlled to synchronously reset and align the respective clock signals, so that the collection signals in each collection channel can be synchronously processed after entering the signal processing unit, and the synchronization between the collection signals is improved. Referring to Figure 9 As shown, the reset pulse can be a trigger pulse with a pulse width satisfying a second pulse width condition, and the second pulse width condition corresponds to a pulse width of 2 clock cycles. After receiving the reset pulse, the signal processing unit triggers each processing channel to perform subsequent synchronization preprocessing of the signal.

[0134] As an embodiment of the present application, in the case that the collection channel reaches a preset synchronization state, the synchronization process of the phased array system is ended, and the preset synchronization state includes a preliminary synchronization state. The collection board card adopts a first type board card, the first type board card does not have a digital quadrature demodulation function, and the collection channel in the first type board card does not need to be further phase synchronized. The number of first type board cards is N, and N is a positive integer.

[0135] Specifically, the collection board card in the phased array system can adopt a first type board card, and the first type board card does not have a digital function and cannot perform digital quadrature demodulation on the collection signals in each collection channel. Therefore, for the first type board card, the requirement for the phase synchronization between the collection channels is relatively low, which is usually applicable to the third synchronization consistency requirement, and further phase synchronization is not needed. The number of first type board cards can be one or more, and the specific number can be determined according to the actual application scenario.

[0136] Further, for the first type board card applicable to the third synchronization consistency requirement, since further phase synchronization is not needed, the corresponding preset synchronization state only includes the preliminary synchronization state. When the first type board card reaches the preliminary synchronization state, the synchronization process of the phased array system is ended.

[0137] As an embodiment of the present application, in the case that the acquisition channels reach a preset synchronization state, the synchronization process of the phased array system is ended, the preset synchronization state includes a preliminary synchronization state and a target phase synchronization state; the target phase synchronization state is a first phase synchronization state or a second phase synchronization state; the acquisition board card adopts a second type board card, the second type board card has a digital quadrature demodulation function, the inter-channel phase difference of each acquisition channel in the second type board card has not converged, and further phase synchronization is needed; the number of the second type board cards is N, and N is a positive integer.

[0138] Specifically, the acquisition board card in the phased array system can adopt a second type board card, the second type board card has a digital function and can perform digital quadrature demodulation on the acquisition signals in each acquisition channel. Therefore, for the second type board card, the requirement for the phase synchronization between the acquisition channels is relatively high, and it is usually suitable for the first synchronization consistency requirement or the second synchronization consistency requirement, and further phase synchronization is needed for each acquisition channel. The number of the second type board cards can be one or more, and the specific number can be determined according to the actual application scenario.

[0139] Further, for the second type board card suitable for the first synchronization consistency requirement, the corresponding preset synchronization state includes a preliminary synchronization state and a first phase synchronization state. When the second type board card reaches the preliminary synchronization state and the first phase synchronization state, the synchronization process of the phased array system is ended. Similarly, for the second type board card suitable for the second synchronization consistency requirement, the corresponding preset synchronization state includes a preliminary synchronization state and a second phase synchronization state. When the second type board card reaches the preliminary synchronization state and the second phase synchronization state, the synchronization process of the phased array system is ended.

[0140] Correspondingly, please refer to Figure 10 The embodiment of the present application provides a synchronization acquisition and processing device of a phased array system, the phased array system includes a plurality of acquisition channels; the device includes:

[0141] The delay synchronization module 1010 is used for performing delay synchronization on each acquisition channel, so that all the acquisition channels of the phased array system reach a preliminary synchronization state.

[0142] The inter-channel phase synchronization module 1020 is used for performing inter-channel phase synchronization on each acquisition channel in the case that each acquisition channel reaches the preliminary synchronization state and further phase synchronization is needed; wherein:

[0143] The first phase synchronization unit 1030 is used for, for the first synchronization consistency requirement, on the basis that each acquisition channel reaches the preliminary synchronization state through delay synchronization, performing a first phase synchronization operation, so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement.

[0144] The second phase synchronization unit 1040 is configured to, for the second synchronization consistency requirement, perform a second phase synchronization operation on the basis of the preliminary synchronization state of each acquisition channel achieved by the delay synchronization, so that each acquisition channel reaches a second phase synchronization state corresponding to the second synchronization consistency requirement; wherein the second phase synchronization operation comprises a synchronization operation of the phase and an iterative correction.

[0145] In some optional embodiments, the first phase synchronization unit 1030 comprises:

[0146] The phase information unification subunit is configured to calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0147] The phase adjustment determination subunit is configured to determine the channel phase adjustment value corresponding to each acquisition channel according to the inter-channel phase difference.

[0148] The initial phase update subunit is configured to update the NCO initial phase of each acquisition channel by using the channel phase adjustment value, and complete the first phase synchronization operation.

[0149] In some optional embodiments, the second phase synchronization unit 1040 comprises:

[0150] The inter-channel phase difference calculation subunit is configured to calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0151] The phase difference convergence judgment subunit is configured to judge whether the inter-channel phase difference converges.

[0152] The convergence operation subunit is configured to perform corresponding operation according to whether the inter-channel phase difference converges, and if the inter-channel phase difference converges, end the iterative correction process of the second phase synchronization operation.

[0153] The non-convergence operation subunit is configured to perform corresponding operation according to whether the inter-channel phase difference converges, and if the inter-channel phase difference does not converge, determine the channel phase adjustment value corresponding to each acquisition channel according to the inter-channel phase difference; update the NCO initial phase of each acquisition channel by using the channel phase adjustment value; repeat the steps of calculating the phase information, the inter-channel phase difference and the convergence judgment until the inter-channel phase difference of each acquisition channel reaches a convergence state.

[0154] In some optional embodiments, the inter-channel phase synchronization module 1020 comprises:

[0155] The delay value unification unit is configured to calculate the delay value of each acquisition channel, and unify the delay values of each acquisition channel to obtain a unified delay value.

[0156] delay configuration unit, configured to configure each acquisition channel with a uniform delay value, so as to complete delay synchronization of each acquisition channel.

[0157] In some optional embodiments, the phased array system comprises a timing control board, a frequency synthesis board and acquisition board cards; the timing control board is connected with the acquisition board cards through first connection cables, and all the first connection cables require stable phase and strict equal length;

[0158] The frequency synthesis board is connected with the timing control board and the acquisition board cards through second connection cables respectively, and all the second connection cables require stable phase and strict equal length.

[0159] In some optional embodiments, the device further comprises a synchronization preprocessing module, comprising:

[0160] The synchronization reset alignment unit is configured to take the reference clock signal as a clock reference, send a synchronization control pulse signal to the acquisition board cards through the timing control board, so as to trigger the phased array system to perform subsequent synchronization preprocessing of signals.

[0161] In some optional embodiments, the synchronization process of the phased array system is ended when the acquisition channels reach a preset synchronization state, and the preset synchronization state comprises a preliminary synchronization state; the acquisition board cards adopt first type board cards, the first type board cards do not have digital quadrature demodulation function, and the acquisition channels in the first type board cards do not need to be further phase synchronized; the number of the first type board cards is N, and N is a positive integer.

[0162] In some optional embodiments, the synchronization process of the phased array system is ended when the acquisition channels reach a preset synchronization state, and the preset synchronization state comprises a preliminary synchronization state and a target phase synchronization state; the target phase synchronization state is a first phase synchronization state or a second phase synchronization state; the acquisition board cards adopt second type board cards, the second type board cards have digital quadrature demodulation function, the inter-channel phase difference of the acquisition channels in the second type board cards has not converged, and further phase synchronization is needed; the number of the second type board cards is N, and N is a positive integer.

[0163] The further function description of each module and unit is the same as that of the above-mentioned corresponding embodiments, and will not be repeated here.

[0164] The synchronization acquisition and processing device of the phased array system in the embodiment is presented in the form of a functional unit, and the unit here refers to an ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit) circuit, a processor and a memory executing one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.

[0165] Referring now to the drawings Figure 11 , Figure 11 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. As shown in the diagram, the electronic device includes one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively connected with each other by using different buses, and can be mounted on a common main board or mounted in other manners as needed. The processor can process instructions executed within the electronic device, including instructions stored in the memory or on the memory to display graphical information of a GUI on an external input / output device, such as a display device coupled to the interface. In some optional embodiments, multiple processors and / or buses can be used together with multiple memories and multiple memory banks, if needed. Similarly, multiple electronic devices can be connected, each providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 11 The processor 10 is taken as an example in the embodiment.

[0166] The processor 10 can be a central processor, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0167] The memory 20 stores instructions executable by the at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0168] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function; and the data storage area can store data created according to the use of the electronic device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some optional embodiments, the memory 20 can optionally include a memory remotely arranged with respect to the processor 10, and these remote memories can be connected to the electronic device by a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0169] The memory 20 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state disk; and the memory 20 can further include a combination of the above kinds of memories.

[0170] The electronic device also includes a communication interface 30 for the electronic device to communicate with other devices or communication networks.

[0171] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer code originally stored in a remote storage medium or non-transitory machine readable storage medium and downloaded to a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, processor, microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the method shown in the above embodiments.

[0172] The embodiments of the application provide a computer program product, which includes computer instructions stored in a computer readable storage medium. A processor of an electronic device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the electronic device to perform the method of any of the embodiments of the application. Although the embodiments of the application are described in conjunction with the accompanying drawings, various modifications and changes can be suggested by those skilled in the art without departing from the spirit and scope of the application, and such modifications and changes are intended to fall within the scope of the appended claims.

[0173] The system, apparatus, module or unit illustrated in the above embodiments can be specifically implemented by a computer chip or entity, or by a product with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0174] For the convenience of description, the above apparatus is described in various units by function. Of course, the functions of each unit can be implemented in the same or more software and / or hardware when implementing the application.

[0175] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, a system or a computer program product. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer readable program code.

[0176] The present application is described in reference to the flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams block or blocks.

[0177] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart illustrations and / or block diagrams block or blocks.

[0178] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams block or blocks.

[0179] It is also noted that the term "comprising" or "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. An element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article or apparatus that comprises the recited element.

[0180] The various embodiments described in this specification are described using a numbering of embodiments approach: this means that each feature can be present in each embodiment, and the various features of the embodiments can be combined in any combination, unless the context clearly indicates otherwise. The descriptions and illustrations herein teach those skilled in the art the best way to make and use the application. Although the application has been described in detail with reference to certain embodiments, variations and modifications exist within the spirit and scope of the application as described and defined in the following claims.

[0181] The application described herein is not limited to the embodiments described above. It should be appreciated by persons skilled in the art that changes and modifications can be made to the embodiments described herein without departing from the spirit and scope of the application as defined in the following claims. In addition, where features, components or steps are described as being optional, it should be understood that such features, components or steps can be provided in some embodiments.

[0182] Although the application has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the scope of the appended claims.

Claims

1. A method for synchronous acquisition and processing of a phased array system, characterized in that, The phased array system comprises a plurality of acquisition channels; the method comprises: delay synchronization is performed on each acquisition channel, so that all acquisition channels of the phased array system reach a preliminary synchronization state; in the case that each acquisition channel reaches the preliminary synchronization state and further phase synchronization is required, inter-channel phase synchronization is performed on each acquisition channel; wherein: for a first synchronization consistency requirement, on the basis of each acquisition channel reaching the preliminary synchronization state through the delay synchronization, a first phase synchronization operation is performed, so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement; for a second synchronization consistency requirement, on the basis of each acquisition channel reaching the preliminary synchronization state through the delay synchronization, a second phase synchronization operation is performed, so that each acquisition channel reaches a second phase synchronization state corresponding to the second synchronization consistency requirement; wherein the second phase synchronization operation comprises a synchronization operation of phase and iterative correction.

2. The method of claim 1, wherein, The first phase synchronization operation is performed by the following steps: phase information of each acquisition channel is calculated, and inter-channel phase difference between each acquisition channel and a selected reference channel is calculated based on phase information of the selected reference channel; a channel phase adjustment value corresponding to each acquisition channel is determined according to the inter-channel phase difference; NCO initial phase of each acquisition channel is updated by using the channel phase adjustment value, and the first phase synchronization operation is completed.

3. The method of claim 1, wherein, The second phase synchronization operation is performed by the following steps: phase information of each acquisition channel is calculated, and inter-channel phase difference between each acquisition channel and a selected reference channel is calculated based on phase information of the selected reference channel; it is judged whether the inter-channel phase difference converges; if it converges, the iterative correction process of the second phase synchronization operation is ended; if it does not converge, a channel phase adjustment value corresponding to each acquisition channel is determined according to the inter-channel phase difference; NCO initial phase of each acquisition channel is updated by using the channel phase adjustment value; the steps of calculating phase information, inter-channel phase difference and judging convergence are repeated until the inter-channel phase difference of each acquisition channel reaches a convergence state.

4. The method of claim 1, wherein, The delay synchronization of each acquisition channel comprises: delay values of each acquisition channel are calculated, and the delay values of each acquisition channel are unified to obtain a unified delay value; delay configuration is performed on each acquisition channel according to the unified delay value, and delay synchronization of each acquisition channel is completed.

5. The method of claim 1 wherein, The phased array system comprises a timing control board, a frequency synthesis board and an acquisition board; the timing control board is connected with the acquisition board through a first connection cable, and all first connection cables require stable phase and strict equal length; the frequency synthesis board is connected with the timing control board and the acquisition board through a second connection cable respectively, and all second connection cables require stable phase and strict equal length.

6. The method of claim 5, wherein, The frequency synthesis board sends a reference clock signal with the same source, high stability and phase reference to the timing control board and the acquisition board; the acquisition board comprises the plurality of acquisition channels; The method further comprises: The time sequence control board sends a synchronization control pulse signal to the acquisition board card based on the reference clock signal, so as to trigger the phased array system to perform subsequent synchronization preprocessing of a signal.

7. The method of claim 6, wherein, The synchronization process of the phased array system is ended when the acquisition channel reaches a preset synchronization state, and the preset synchronization state includes the preliminary synchronization state. The acquisition board card is a first type board card, the first type board card does not have a digital quadrature demodulation function, and the acquisition channel in the first type board card does not need to be further phase synchronized. The number of the first type board cards is N, and N is a positive integer.

8. The method of claim 6, wherein, The synchronization process of the phased array system is ended when the acquisition channel reaches a preset synchronization state, and the preset synchronization state includes the preliminary synchronization state and a target phase synchronization state. The target phase synchronization state is a first phase synchronization state or a second phase synchronization state. The acquisition board card is a second type board card, the second type board card has a digital quadrature demodulation function, and the channel-to-channel phase difference of each acquisition channel in the second type board card has not converged and needs to be further phase synchronized. The number of the second type board cards is N, and N is a positive integer.

9. A synchronous acquisition and processing apparatus for a phased array system, characterized by The phased array system includes a plurality of acquisition channels; and the device includes: a delay synchronization module configured to perform delay synchronization on each acquisition channel, so that all acquisition channels of the phased array system reach a preliminary synchronization state; a channel-to-channel phase synchronization module configured to perform channel-to-channel phase synchronization on each acquisition channel when the acquisition channel reaches the preliminary synchronization state and needs to be further phase synchronized; and wherein: a first phase synchronization unit configured to, for a first synchronization consistency requirement, perform a first phase synchronization operation based on the delay synchronization so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement; a second phase synchronization unit configured to, for a second synchronization consistency requirement, perform a second phase synchronization operation based on the delay synchronization so that each acquisition channel reaches a second phase synchronization state corresponding to the second synchronization consistency requirement; and wherein the second phase synchronization operation includes a synchronization operation of a phase and an iterative correction.

10. An electronic device, comprising: The device includes: a memory and a processor, which are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method of any one of claims 1 to 8.

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