Multi-memory chip packaging structure and packaging method
By removing the SRAM chip from the SoC into an independent chip and performing wafer-level packaging with the DRAM chip, the problem of limited SRAM area is solved, efficient data transmission and computing speed are achieved, and costs are reduced.
Patent Information
- Application Number
- CN202510860973.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-10-03
AI Technical Summary
In existing technologies, SRAM chips are limited in area and cannot meet the data transmission requirements of high-speed AI computing. After integration with the CPU, the CPU area increases and the yield is reduced. At the same time, HBM memory alternatives are expensive and difficult to apply on a large scale.
A multi-memory chip packaging structure is designed, in which the SRAM chip is removed from the SoC as an independent chip, and a new packaging structure is formed with the SoC chip through flip-chip welding. The chip is then packaged with the DRAM chip at the wafer level, and the surface redistribution layer is used to increase the data transmission speed and reduce the substrate design.
It achieves efficient data transmission speed, reduces SoC chip area, improves computing speed, avoids the use of HBM memory, and reduces costs.
Smart Images
Figure CN120751707A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip packaging, in particular to a multi-storage chip packaging structure and a packaging method. Background Art
[0002] AI applications are not completely inseparable from HBM. As of now, many GPUs still use GDDR memory, which can also achieve a memory bandwidth of 800-960GB / s. Although it is far less than the rate of HBM3E, it is sufficient for large language models with smaller-scale reasoning. If GDDR is not enough, SRAM and system scale expansion have also been proven to be effective alternatives to HBM. Companies such as Cerebras and Groq have demonstrated this by allocating a large amount of SRAM to each chip and connecting the chips together using high-speed interconnects or wafer-level packaging. This has achieved extremely high AI reasoning throughput speeds, even exceeding some systems using independent HBM memory.
[0003] Conventional SRAM is typically integrated into the SoC, but due to limitations in SRAM area and process node, its size is typically limited. An example of increasing the SRAM chip area is shown in the AMD MI300 series architecture. The SRAM chip is flip-flopped onto the SoC using C2W Hybrid Bonding. The non-SRAM area is flattened using SiO2 deposition, and I / O is subsequently connected using SiO2 / TSV. Summary of the Invention
[0004] In order to overcome the deficiencies of the prior art, the present invention provides a multi-storage chip packaging structure and a packaging method.
[0005] To achieve the above purpose, a multi-memory chip packaging structure is designed, including a Soc chip and a Dram chip. The Soc chip is respectively provided with a solder pad and a conductive structure. The Soc chip is connected to the SRAM chip through the solder pad, and the Soc chip is connected to the redistribution layer through the conductive structure. The surface of the DRAM chip is connected to the redistribution layer through an electrical connection structure. One side of the redistribution layer is connected to the solder ball through the UBM layer, and the other side of the redistribution layer is provided with a plastic packaging layer.
[0006] The number of the DRAM chip is one, and the electrical connection structure uses micro-bumps.
[0007] There are two DRAM chips, including Dram chip 1 and Dram chip 2. One side of the surface of Dram chip 1 is connected to the redistribution layer through conductive structure 2. Dram chip 2 is provided on the other side of the surface of Dram chip 1. The surface of Dram chip 2 is connected to the redistribution layer through micro-bumps.
[0008] To achieve the above object, a packaging method for a multi-memory chip packaging structure is designed, comprising the following steps: S1, providing a carrier board and forming a peeling layer on one surface of the carrier board; S2, forming a PI layer on one side of the peeling layer; S3, attaching the Soc chip and the DRAM chip to the surface of the PI layer, forming a pad and a conductive structure 1 on the surface of the Soc chip, and forming an electrical connection structure on the surface of the DRAM chip; S4, flip-flop the SRAM chip on the surface of the Soc chip; S5, plastic seal, S6, thinning process until the end surface of the conductive structure 1 and the electrical connection structure is exposed; S7, forming a redistribution layer on the thinned surface, and forming solder balls on the redistribution layer through the UBM layer; S8, remove the carrier board and peel off the layer.
[0009] In the steps S3-S4, the height of the conductive structure is greater than the thickness of the SRAM chip by 50 μm; and the highest point of the electrical connection structure is higher than the overall height of the SRAM chip after flip-sticking.
[0010] In the step S5, the thickness of the plastic package exceeds the thickness of the SRAM chip by 100 μm.
[0011] In the step S6, the plastic encapsulation layer and the silicon surface of the SRAM chip are thinned.
[0012] The method further includes step S9, a second thinning step for thinning the silicon surfaces of the Soc chip and the DRAM chip.
[0013] In the step S3, there is one DRAM chip, and an electrical connection structure is formed on the surface of the DRAM chip.
[0014] In step S3, there are two DRAM chips, including Dram chip 1 and Dram chip 2. Conductive structure 2 is formed on one side of the surface of Dram chip 1, and Dram chip 2 is attached to the other side of the surface of Dram chip 1. Micro bumps are formed on Dram chip 2.
[0015] Compared with the prior art, the present invention realizes SoC / SRAM / DRAM multi-chip fan-out integration by placing a large-size SRAM chip externally on the SoC; and improves the cache computing speed by using a large-size SRAM or multiple SRAMs. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 This is a structural diagram of embodiment 1 of the present invention.
[0017] Figure 2This is a flow chart of the first embodiment of the present invention.
[0018] Figure 3 This is a result diagram of Example 2 of the present invention.
[0019] Figure 4 This is a plan view of embodiment 2 of the present invention.
[0020] Figure 5 Schematic diagram of the prior art AMD structure before improvement by the present invention. DETAILED DESCRIPTION
[0021] The present invention will be further described below with reference to the accompanying drawings. Example 1
[0022] like Figure 1 As shown, the Soc chip 4 is provided with a pad 6 and a conductive structure 7 respectively. The Soc chip 4 is connected to the SRAM chip 9 through the pad 6, and the Soc chip 4 is connected to the redistribution layer 10 through the conductive structure 7. The surface of the DRAM chip 5 is connected to the redistribution layer 10 through the electrical connection structure 8. One side of the redistribution layer 10 is connected to the solder ball 12 through the UBM layer 11, and the other side of the redistribution layer 10 is provided with a plastic packaging layer 13.
[0023] In this embodiment, the number of the DRAM chip 5 is one, and the electrical connection structure 8 is a micro-bump.
[0024] like Figure 2 As shown, the packaging method of the multi-memory chip packaging structure includes the following steps: S1 , providing a carrier board 1 , and forming a peeling layer 2 on one side surface of the carrier board 1 .
[0025] S2, forming the PI layer 3 on the surface of the release layer 2 side.
[0026] S3, the Soc chip 4 and the Dram chip 5 are attached to the surface of the PI layer 3, a solder pad 6 and a conductive structure 7 are formed on the surface of the Soc chip 4, and an electrical connection structure 8 is formed on the surface of the Dram chip 5. The height of the conductive structure 7 is greater than the thickness of the SRAM chip 9 by 50um; the highest point of the electrical connection structure 8 is higher than the overall height of the SRAM chip 9 after inverted attachment.
[0027] S4, flip-flop the SRAM chip 9 on the surface of the Soc chip 4.
[0028] S5, plastic packaging, the thickness of the plastic packaging exceeds the thickness of the SRAM chip 9 by 100um.
[0029] S6, thinning process, thinning the plastic packaging layer 13 and the silicon surface of the SRAM chip 9 until the end surface of the conductive structure 7 and one side of the electrical connection structure 8 is exposed.
[0030] S7 , forming a redistribution layer 10 on the thinned surface, and forming solder balls 12 on the redistribution layer 10 through the UBM layer 11 to form an electrical connection with the outside world.
[0031] S8, take out the carrier board 1 and the peeling layer 2.
[0032] S9, the second thinning, thinning the silicon surface of the Soc chip 4 and the DRAM chip 5.
[0033] During specific use, the number of the SRAM chips 9 is one or more.
[0034] This embodiment forms a multi-chip fan-out packaging structure, in which the SRAM chip and the DRAM chip are co-packaged to serve the high-speed inference AI chip model.
[0035] Currently, SRAM chips are typically integrated into the CPU itself. However, AI thrust computing demands increasingly faster data transmission speeds. Therefore, using an SRAM + DRAM module requires a higher SRAM chip integration density, meaning a larger area. However, increasing the SRAM area and integrating it simultaneously with the CPU increases the CPU area itself, which in turn reduces the CPU manufacturing yield. In this implementation, the SRAM chip is separated from the SoC unit into a separate chip. This is interconnected via FC and flipped onto the SoC chip to form a new packaging structure, reducing the SoC chip area and providing high-speed signal transmission. The SRAM chip is combined with the DRAM chip to increase data transmission speed and avoid the use of HBM. By post-molding, the conductive structures required for the SoC chip are arranged around the SoC chip, primarily for power I / O and DRAM chip interconnect I / O, with a reduced number of surface wiring layers. The DRAM chip and SoC / SRAM chip are packaged at the wafer level, eliminating the substrate. Furthermore, a surface redistribution layer is used to improve data transmission between the DRAM chip and the SoC chip. Example 2
[0036] This embodiment only describes the differences from the first embodiment, and the similarities are not described again.
[0037] The difference between this embodiment and the first embodiment is that Figures 3 and 4 As shown, there are two DRAM chips 5, including a Dram chip 1 5-1 and a Dram chip 2 5-2. One side of the surface of the Dram chip 1 5-1 is connected to the redistribution layer 10 through a conductive structure 2 5-3. The other side of the surface of the Dram chip 1 5-1 is provided with a Dram chip 2 5-2. The surface of the Dram chip 2 5-2 is connected to the redistribution layer 10 through a micro bump 5-4.
[0038] In the packaging method, in step S3, a conductive structure 2 5-3 is formed on one side of the surface of the DRAM chip 1 5-1, a DRAM chip 2 5-2 is attached to the other side of the surface of the DRAM chip 1 5-1, and micro bumps 5-4 are formed on the DRAM chip 2 5-2.
Claims
1. A multi-memory chip packaging structure, characterized in that: The invention comprises a Soc chip (4) and a Dram chip (5), wherein the Soc chip (4) is provided with a solder pad (6) and a conductive structure (7), the Soc chip (4) is connected to the SRAM chip (9) via the solder pad (6), the Soc chip (4) is connected to the redistribution layer (10) via the conductive structure (7), the surface of the DRAM chip (5) is connected to the redistribution layer (10) via the electrical connection structure (8), one side of the redistribution layer (10) is connected to the solder ball (12) via the UBM layer (11), and the other side of the redistribution layer (10) is provided with a plastic sealing layer (13).
2. The multi-memory chip packaging structure according to claim 1, wherein: The number of the DRAM chip (5) is one, and the electrical connection structure (8) is a micro-bump.
3. The multi-memory chip packaging structure according to claim 1, wherein: The number of the DRAM chips (5) is two, including a Dram chip 1 (5-1) and a Dram chip 2 (5-2). One side of the surface of the Dram chip 1 (5-1) is connected to the redistribution layer (10) via a conductive structure 2 (5-3). The other side of the surface of the Dram chip 1 (5-1) is provided with a Dram chip 2 (5-2). The surface of the Dram chip 2 (5-2) is connected to the redistribution layer (10) via a micro-bump (5-4).
4. A packaging method for a multi-memory chip packaging structure, characterized in that: The steps include: S1, providing a carrier plate (1), and forming a peeling layer (2) on one side surface of the carrier plate (1); S2, forming a PI layer (3) on one surface of the peeling layer (2); S3, a Soc chip (4) and a Dram chip (5) are attached to the surface of the PI layer (3), a solder pad (6) and a conductive structure (7) are formed on the surface of the Soc chip (4), and an electrical connection structure (8) is formed on the surface of the Dram chip (5); S4, flip-stick the SRAM chip (9) on the surface of the Soc chip (4); S5, plastic seal, S6, thinning process until the end surface of one side of the conductive structure (7) and the electrical connection structure (8) is exposed; S7, forming a redistribution layer (10) on the thinned surface, and forming solder balls (12) on the redistribution layer (10) through the UBM layer (11); S8, taking out the carrier plate (1) and the peeling layer (2).
5. The packaging method of a multi-memory chip packaging structure according to claim 4, wherein: In the steps S3-S4, the height of the conductive structure 1 (7) is greater than the thickness of the SRAM chip (9) by 50 μm; and the highest point of the electrical connection structure (8) is higher than the overall height of the SRAM chip (9) after flip-sticking.
6. The packaging method of a multi-memory chip packaging structure according to claim 4, wherein: In the step S5, the thickness of the plastic package exceeds the thickness of the SRAM chip (9) by 100 μm.
7. The packaging method of a multi-memory chip packaging structure according to claim 4, characterized in that: In the step S6, the plastic encapsulation layer (13) and the silicon surface of the SRAM chip (9) are thinned.
8. The packaging method of a multi-memory chip packaging structure according to claim 4, wherein: The method further includes step S9, a second thinning step for thinning the silicon surface of the Soc chip (4) and the DRAM chip (5).
9. The packaging method of a multi-memory chip packaging structure according to claim 4, wherein: In the step S3, the number of the DRAM chip (5) is one, and an electrical connection structure (8) is formed on the surface of the DRAM chip (5).
10. The packaging method of a multi-memory chip packaging structure according to claim 4, characterized in that: In the step S3, the number of DRAM chips (5) is two, including Dram chip 1 (5-1) and Dram chip 2 (5-2), a conductive structure 2 (5-3) is formed on one side of the surface of Dram chip 1 (5-1), and Dram chip 2 (5-2) is attached to the other side of the surface of Dram chip 1 (5-1), and micro bumps (5-4) are formed on Dram chip 2 (5-2).