Process implementation method for parallel integration of magnetic storage and magnetic calculation

Abstract

The invention discloses a magnetic storage and magnetic calculation parallel integration process implementation method, which belongs to the field of integrated circuit manufacturing, and comprises the following steps: S1, bottom electrode construction and dielectric filling; s2, differentiated MTJ stack construction is carried out; S3, double-section zoning annealing is carried out; and S4, rear-section interconnection and packaging are carried out. According to the invention, a method of directional etching after deposition of a whole lightweight stack and local supplementation of a heavy stack is provided, so that two MTJ devices with different film thicknesses and material combinations can be formed; a partition annealing scheme combining hard mask heat insulation and rapid short-time thermal annealing is adopted, and the dual goals of high-temperature crystallization in an MRAM region and low-temperature maintenance in a p-bit region are achieved. Through two core technologies of differential stacking and partition annealing, a high-delta MRAM storage unit and a low-delta p-bit probability calculation unit can be integrated on the same chip, and a process line does not need to be separated or an external module does not need to be added, so that the chip area and the system cost are remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a process implementation method for parallel integration of magnetic storage and magnetic computing. Background Art

[0002] In recent years, with the growing demand for energy efficiency and parallel processing capabilities in artificial intelligence, the Internet of Things, and high-performance computing, traditional CMOS technology has gradually reached bottlenecks in terms of power consumption, speed, and integration. Magnetic tunnel junctions (MTJs), based on the principles of spin electronics, enable high-speed, non-volatile data storage, providing excellent performance for magnetoresistive random access memory (MRAM). However, relying solely on MRAM cannot meet the needs in areas such as probabilistic computing, random number generation, and processing complex optimization problems. Therefore, researchers have proposed the concept of expanding MTJ technology into a "probabilistic bit" (p-bit) device. By reducing the energy barrier, the p-bit device can achieve controllable random flipping under thermal activation conditions, making it a hardware-level probabilistic computing unit capable of efficiently processing related tasks.

[0003] Currently, mainstream MRAM processes are capable of fabricating MTJ devices with dimensions ranging from 20 to 50 nanometers at 28nm, 16nm, and even more advanced CMOS nodes. These devices typically rely on a back-end annealing process at 300 to 400°C to achieve a high thermal stability factor (Δ) ≥ 60kBT and a large tunnel magnetoresistance (TMR) ratio (TMR) ≥ 100%. For p-bit devices, the required thermal stability factor (Δ) is typically between 2 and 20kBT to ensure MHz-level random switching rates. This requires thinning or weakening the MgO and CoFeB free layers, and controlling the annealing temperature between 150 and 250°C to avoid excessive Δ. The two device types differ significantly in material selection, annealing procedures, and other process parameters. Therefore, directly applying the MRAM process to the fabrication of p-bit devices would make it difficult to achieve both storage and probabilistic computing capabilities.

[0004] In summary, there is an urgent need for an integrated semiconductor manufacturing process that takes into account both high-ΔMRAM and low-Δp-bit devices, which can provide long-term, stable and reliable non-volatile storage on the same chip and efficiently support hardware-level probabilistic computing, thereby laying a solid process foundation for the deep integration of magnetic storage and magnetic computing. Summary of the Invention

[0005] In response to some existing problems, the purpose of the present invention is to provide a process implementation method for the parallel integration of magnetic storage and magnetic computing, so as to solve the problems of integrating high-Δ MTJ, low-Δ MTJ and CMOS circuits on the same wafer, realizing differentiated MTJ stack materials and film thicknesses, and resolving the conflict between the annealing processes of the two MTJ devices.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A process for implementing parallel integration of magnetic storage and magnetic computing, comprising the following steps:

[0008] S1. Bottom electrode construction and dielectric filling: forming a bottom electrode pattern on a silicon substrate; depositing a buffer insulating film to fill the gaps between the bottom electrodes to ensure electrical isolation of the device; removing excess dielectric material to expose the top surface of the bottom electrode;

[0009] S2. Differentiated MTJ stack construction: A stack is deposited across the entire wafer on the bottom electrode to form a p-bit region and an MRAM region. Directional etching and high-Δ stack deposition are performed in the MRAM region to differentiate the stacks between the two regions. Two types of MTJs are patterned across the entire wafer.

[0010] S3, dual-stage partition annealing: the MRAM area in the whole wafer that has been differentiated in step S2 is first annealed at high temperature for a short time, and then the whole wafer is annealed at low temperature;

[0011] S4. Back-end interconnection and packaging: Complete the back-end interconnection process in sequence to eventually form a complete magnetic computing chip and complete the packaging.

[0012] As a further solution of the present invention: the process of the bottom electrode pattern in step S1 is: after completing the CMOS front-end process on the silicon substrate, depositing the bottom electrode metal, and forming the bottom electrode pattern in the MTJ device area by photolithography and etching.

[0013] As a further solution of the present invention: the process of the buffer insulating film in step S1 is: depositing a layer of bottom buffer insulating film by plasma enhanced chemical vapor deposition (PECVD).

[0014] As a further solution of the present invention: the process of removing excess dielectric material in step S1 is a chemical mechanical polishing (CMP) process.

[0015] As a further solution of the present invention: Step S2 is specifically as follows:

[0016] S21. In the low ΔMTJ stack, a “lightweight” stack is deposited over the entire wafer area using magnetron sputtering or atomic layer deposition (ALD) to form the initial structure of the p-bit region.

[0017] S22, etching the MRAM area stack, coating the p-bit area with photoresist as a protective layer, performing directional etching in the MRAM area, and removing the thinned stack layer;

[0018] S23, MRAM area high Δ stack, additional high Δ stack is deposited in the exposed MRAM area to complete the stack differentiation of the two areas;

[0019] S24, MTJ patterning, full-chip photolithography and etching to form two types of MTJ columnar patterns, de-resist and clean.

[0020] As a further solution of the present invention: the “lightweight” stack in step S21 includes a spin reference layer, a free layer and a MgO tunnel layer.

[0021] As a further solution of the present invention: Step S3 is specifically as follows:

[0022] S31, high temperature annealing, coating the p-bit area with a SiO2 / SiN hard mask to isolate heat conduction and prevent the high temperature annealing of the MRAM area from affecting the p-bit area; using rapid thermal annealing (RTA) equipment to perform high temperature short time annealing, acting only on the MRAM area, to achieve CoFeB / MgO interface crystallization activation;

[0023] S32, low temperature annealing. After the mask is removed, the entire wafer is subjected to low temperature annealing to crystallize the p-bit region and eliminate stress to maintain a low Δ.

[0024] As a further solution of the present invention: the operating temperature of the RTA equipment for high temperature short time annealing in step S31 is 350-400°C.

[0025] As a further solution of the present invention: the temperature of the low-temperature annealing of the entire wafer in step S32 is 150-250°C.

[0026] As a further solution of the present invention: the middle and back-end interconnection processes in step S4 are Via opening, copper metal filling, CMP planarization and multi-layer metal interconnection wiring.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] Compared with traditional discrete solutions, the present invention has a higher device density, a greatly reduced energy efficiency ratio, and can independently optimize thermal stability and flipping speed. Synchronous patterning greatly reduces the number of process steps. Through the above innovations, the process of the present invention needs to be systematically optimized in terms of material deposition, mask partitioning, annealing process, etc., providing a solid process foundation for the deep integration of magnetic storage and magnetic computing. The present invention proposes a method of directional etching after full-chip lightweight stack deposition and then local supplementation of heavy stacking, which can form MTJ devices with two different film thicknesses and material combinations; a partitioned annealing scheme combining hard mask insulation with fast short-time thermal annealing is adopted to achieve the dual goals of high-temperature crystallization of the MRAM area and low-temperature maintenance of the p-bit area. Through the two core technologies of differentiated stacking and partitioned annealing, the present invention can integrate high-ΔMRAM storage units and low-Δp-bit probability calculation units on the same chip without the need for separate process lines or additional external modules, thereby significantly reducing chip area and system cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the steps of a process implementation method for parallel integration of magnetic storage and magnetic computing. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "provided with," "connected," and "connected" should be understood in a broad sense; for example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections via an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention in specific contexts.

[0032] To address the shortcomings of existing magnetic computing chip process solutions, the present invention provides an integrated semiconductor manufacturing process that takes into account both high-ΔMRAM and low-Δp-bit devices. This process requires systematic optimization in material deposition, mask partitioning, annealing process, etc., providing a solid process foundation for the deep integration of magnetic storage and magnetic computing.

[0033] See also Figure 1 A process for implementing parallel integration of magnetic storage and magnetic computing comprises the following steps:

[0034] S1. Bottom electrode construction and dielectric filling: After completing the CMOS front-end process on the silicon substrate, the bottom electrode metal is deposited, and the bottom electrode pattern is formed in the MTJ device area through lithography and etching. A layer of bottom buffer insulation film is deposited by plasma-enhanced chemical vapor deposition (PECVD) to fill the gap between the bottom electrodes and ensure electrical isolation of the device. The excess dielectric material is removed by chemical mechanical polishing (CMP) to expose the top surface of the bottom electrode.

[0035] S2. Differentiated MTJ stack construction: A stack is deposited across the entire wafer on the bottom electrode to form a p-bit region and an MRAM region. Directional etching and high-Δ stack deposition are performed in the MRAM region to differentiate the stacks between the two regions. Two types of MTJs are patterned across the entire wafer.

[0036] S21. In the low ΔMTJ stack, a “lightweight” stack is deposited over the entire wafer area using magnetron sputtering or atomic layer deposition (ALD), including a spin reference layer, a free layer, and an MgO tunnel layer to form the initial structure of the p-bit region.

[0037] S22, etching the MRAM area stack, coating the p-bit area with photoresist as a protective layer, performing directional etching in the MRAM area, and removing the thinned stack layer;

[0038] S23, MRAM area high Δ stack, additional high Δ stack is deposited in the exposed MRAM area to complete the stack differentiation of the two areas;

[0039] S24, MTJ patterning, full-chip photolithography and etching to form two types of MTJ columnar patterns, de-resist and clean;

[0040] S3, dual-stage partition annealing: the MRAM area in the whole wafer that has been differentiated in step S2 is first annealed at high temperature for a short time, and then the whole wafer is annealed at low temperature;

[0041] S31, high temperature annealing, coating the p-bit area with a SiO2 / SiN hard mask to isolate heat conduction and prevent the high temperature annealing of the MRAM area from affecting the p-bit area; using rapid thermal annealing (RTA) equipment to perform short-term annealing at 350-400°C, acting only on the MRAM area, to achieve crystallization activation of the CoFeB / MgO interface;

[0042] S32, low temperature annealing. After the mask is removed, the entire wafer is subjected to a low temperature annealing at 150–250°C to crystallize the p-bit region and eliminate stress, maintaining a low Δ.

[0043] S4, back-end interconnection and packaging: Complete via opening, copper metal filling, CMP planarization and multi-layer metal interconnection wiring in sequence, and finally form a complete magnetic computing chip and complete the packaging.

[0044] In step S21 , the low Δ stack includes a CoFeB free layer, an MgO tunnel layer, and a reference layer, and is 20-50% thinner than the high Δ stack.

[0045] In step S23 , the high Δ stack includes a [Co / Pt] multilayer reference layer and a thickened CoFeB free layer, and the Δ value is greater than 60.

[0046] In step S31 , a SiO 2 / SiN composite hard mask is used, and the thermal conductivity is less than 5 W / m·K.

[0047] The high temperature annealing is a pulsed RTA treatment with a duration of 10-30 seconds.

[0048] This invention proposes a manufacturing process for monolithic integration of magnetic storage MRAM and magnetic computing p-bit devices, achieving performance optimization through differentiated stack construction and zoned annealing. Key technologies include: 1) depositing low-Δp-bit and high-ΔMRAM MTJ stacks in separate regions within a unified process flow; 2) employing hard mask-assisted segmented annealing, with high-temperature treatment of the MRAM region to enhance thermal stability and low-temperature treatment of the p-bit region to maintain a low energy barrier; and 3) simultaneous patterning and interconnection of the two device types. This approach addresses the incompatibility of traditional processes with both storage and computing requirements, significantly reducing manufacturing costs.

[0049] This invention offers the advantage of process compatibility. Through differentiated MTJ stack construction and dual-stage zoned annealing, it simultaneously implements high-Δ MRAM storage and low-Δ p-bit computing devices on the same wafer, avoiding the complex interconnect issues of traditional discrete chip solutions and reducing system power consumption and area costs. Standard PECVD and CMP processes are used for bottom electrode construction and dielectric filling, and copper wiring technology is used for back-end interconnection, allowing seamless integration into existing semiconductor production lines without the need for additional equipment investment.

[0050] The precise design of the stack structure of the present invention has the advantages of performance differentiation regulation:

[0051] p-bit region: Lightweight stacking ensures low energy barriers, meeting the fast magnetic moment switching required for probabilistic calculations.

[0052] MRAM area: High Δ stack provides high thermal stability and ensures data storage reliability.

[0053] The present invention's zoned annealing technology uses high-temperature, short-term annealing at 350-400°C to optimize the crystallinity of the CoFeB / MgO interface and improve the tunnel magnetoresistance ratio. Low-temperature annealing at 150-250°C prevents an increase in the p-bit region's energy barrier while simultaneously eliminating stress, enabling independent optimization of the performance of the two zones.

[0054] This method completes etching of both types of MTJ pillars in one pass across the entire wafer, reducing photolithography and etching times, lowering process complexity and mask costs. The SiO2 / SiN hard mask effectively isolates the p-bit region from the effects of high-temperature annealing, preventing material degradation caused by repeated annealing and improving overall yield.

[0055] The present invention can also flexibly adapt to different application scenarios, such as in-memory computing and random number generation, by adjusting the thickness and material combination of the high-Δ / low-Δ stack. The planarization of the bottom electrode and dielectric fill lays the foundation for subsequent vertical integration of multi-layer MTJ stacks.

[0056] The main application scenarios of this invention are integrated storage and computing chips and high-reliability edge computing. The integrated storage and computing chip, namely MRAM, serves as non-volatile storage, and p-bit implements random sampling calculations, which is suitable for probabilistic computing architectures such as Bayesian neural networks. High-reliability edge computing, that is, a single chip that simultaneously meets the high Δ for data storage and the low Δ for real-time processing.

[0057] Compared to traditional discrete solutions, this invention offers higher device density, significantly lower energy efficiency, independent optimization of thermal stability and flipping speed, and simultaneous patterning, significantly reducing process steps. Through these innovations, this invention significantly outperforms traditional technologies in performance, cost, and integration, providing a scalable solution for the multifunctional integration of spintronic devices.

[0058] The present invention designs a process implementation method for the parallel integration of magnetic storage and magnetic computing. A method is proposed in which a full-chip lightweight stack is deposited, followed by directional etching, and then locally supplemented with a heavy stack. This method can form MTJ devices with two different film thicknesses and material combinations. A partitioned annealing scheme combining hard mask insulation with rapid, short-term thermal annealing is employed to achieve the dual goals of high-temperature crystallization in the MRAM region and low-temperature maintenance in the p-bit region. Through the two core technologies of differentiated stacking and partitioned annealing, the present invention can integrate high-ΔMRAM storage cells and low-Δp-bit probability computing cells on the same chip without the need for separate process lines or additional external modules, thereby significantly reducing chip area and system cost.

[0059] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. The embodiments should, therefore, be considered in all respects as illustrative and non-restrictive. The scope of the invention is defined by the appended claims rather than the foregoing description, and all changes coming within the meaning and range of equivalents of the claims are intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0060] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A process for realizing parallel integration of magnetic storage and magnetic computing, characterized in that: It has the following steps: S1. Bottom electrode construction and dielectric filling: forming a bottom electrode pattern on a silicon substrate; Deposit a buffer insulating film to fill the gaps between the bottom electrodes to ensure electrical isolation of the device; remove excess dielectric material to expose the top surface of the bottom electrode; S2. Differentiated MTJ stack construction: A stack is deposited across the entire wafer on the bottom electrode to form a p-bit region and an MRAM region. Directional etching and high-Δ stack deposition are performed in the MRAM region to differentiate the stacks between the two regions. Two types of MTJs are patterned across the entire wafer. S3, dual-stage partition annealing: the MRAM area in the whole wafer that has been differentiated in step S2 is first annealed at high temperature for a short time, and then the whole wafer is annealed at low temperature; S4. Back-end interconnection and packaging: Complete the back-end interconnection process in sequence to eventually form a complete magnetic computing chip and complete the packaging.

2. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 1, characterized in that: The process of forming the bottom electrode pattern in step S1 is as follows: after completing the CMOS front-end process on the silicon substrate, depositing the bottom electrode metal, and forming the bottom electrode pattern in the MTJ device area by photolithography and etching.

3. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 2, characterized in that: The process of forming the buffer insulating film in step S1 is as follows: depositing a bottom buffer insulating film by plasma enhanced chemical vapor deposition (PECVD).

4. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 3, characterized in that: The process of removing excess dielectric material in step S1 is a chemical mechanical polishing (CMP) process.

5. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 4, characterized in that: The step S2 is specifically as follows: S21. In the low ΔMTJ stack, a "lightweight" stack is deposited over the entire wafer area using magnetron sputtering or atomic layer deposition (ALD) to form the initial structure of the p-bit region. S22, etching the MRAM area stack, coating the p-bit area with photoresist as a protective layer, performing directional etching in the MRAM area, and removing the thinned stack layer; S23, MRAM area high Δ stack, additional high Δ stack is deposited in the exposed MRAM area to complete the stack differentiation of the two areas; S24, MTJ patterning, full-chip photolithography and etching to form two types of MTJ columnar patterns, de-resist and clean.

6. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 5, characterized in that: The “lightweight” stack in step S21 includes a spin reference layer, a free layer, and a MgO tunnel layer.

7. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 6, characterized in that: The step S3 is specifically as follows: S31, high temperature annealing, coating the p-bit area with a SiO2 / SiN hard mask to isolate heat conduction and prevent the high temperature annealing of the MRAM area from affecting the p-bit area; using rapid thermal annealing (RTA) equipment to perform high temperature short time annealing, acting only on the MRAM area, to achieve CoFeB / MgO interface crystallization activation; S32, low temperature annealing. After the mask is removed, the entire wafer is subjected to low temperature annealing to crystallize the p-bit region and eliminate stress to maintain a low Δ.

8. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 7, characterized in that: The operating temperature of the RTA equipment for high temperature short time annealing in step S31 is 350-400°C.

9. The method for realizing parallel integration of magnetic storage and magnetic computing according to claim 8, characterized in that: The temperature of the low-temperature annealing of the entire wafer in step S32 is 150-250°C.

10. The process for realizing parallel integration of magnetic storage and magnetic computing according to claim 9, characterized in that: The middle and back-end interconnection processes in step S4 are Via opening, copper metal filling, CMP planarization and multi-layer metal interconnection wiring.

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