Combined cavity for forming conductors in memory die

Abstract

Methods, systems, and apparatus for forming a merged cavity of a conductor in a memory die are described. An array of cavities may be formed through a stack of material layers of a memory die, and a conductor may be formed at least in part by incorporating some of the cavities in the array. Such cavities may be sized according to a relatively minimum feature that implements a subset of such cavities, and a minimum associated feature may be formed using a first subset of the array of cavities. A conductor may be formed at least in part by merging two or more cavities of a second subset of the array of cavities using a material removal operation to remove portions of the stack of material layers. This merging may support the conductor to be formed with a larger cross-section than other features formed using such cavities that are not merged.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 443,013, filed by Wells et al. on February 15, 2023, entitled “MERGED CAVITIES FOR CONDUCTOR FORMATION IN AMEMORY DIE,” and U.S. provisional patent application No. 63 / 486,175, filed by Wells et al. on February 21, 2023, entitled “MERGED CAVITIES FOR CONDUCTOR FORMATION IN A MEMORY DIE,” each of which is assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following relates to one or more systems for memory, including merged cavities for forming conductors in a memory die. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, and the like. Memory devices can be described in terms of either volatile or non-volatile configurations. Volatile memory cells (e.g., DRAM) can lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND) can maintain their programmed state for extended periods of time, even without an external power source. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1

[0014] Examples of systems supporting merged cavities for forming conductors in a memory die according to examples as disclosed herein are described.

[0007] Figure 2 Examples of memory architectures supporting merged cavities for forming conductors in a memory die are described according to examples as disclosed herein.

[0008] Figures 3 to 13 Examples of manufacturing operations that can support merged cavities for forming conductors in a memory die according to examples as disclosed herein are described.

[0009] Figure 14 The illustration shows a flow chart supporting one or several methods for forming merged cavities for conductors in a memory die according to examples as disclosed herein. DETAILED DESCRIPTION

[0010] In some memory manufacturing operations, one or more materials may be deposited over a substrate (e.g., a semiconductor substrate), and portions of the one or more materials may be removed according to various patterning operations. For example, a cavity pattern may be formed by removing one or more materials along a thickness direction according to an opening pattern having one or more different cross-sectional profiles. In some examples, memory cells may be formed at least in part by depositing one or more storage materials in some cavities, and conductors (e.g., to support access to the memory cells or for other operations or signaling) may be formed at least in part by depositing one or more conductive materials in some other cavities.

[0011] In some implementations, conductors may be associated with configured conductivity or resistance values, and the cavities used to form the conductors may have different sizes or patterns to support the conductivity or resistance values. However, forming cavities with different sizes or patterns may be associated with non-uniformities (e.g., structural non-uniformities, processing non-uniformities) within a memory array region or in transition regions between regions of the memory array using cavities of different sizes. Additionally or alternatively, forming patterns with cavities of different sizes (e.g., high aspect ratio cavities) may be associated with relatively complex or expensive processing. Thus, in some examples, it may be desirable to form an array of cavities of uniform size, and to form memory cells and conductors from respective subsets of the same cavity array. However, cavities may be formed with relatively small cross-sections (e.g., associated with the formation of the smallest features, such as memory pillar formation), and conductors formed in cavities of relatively small cross-sections may not support the desired conductivity or resistance values.

[0012] According to examples disclosed herein, an array of cavities can be formed through a stack of material layers of a memory die, and conductors (e.g., conductive pillars) can be formed, at least in part, by merging some of the cavities of the array. For example, such cavities can be sized according to the relative minimum features for implementing a subset of such cavities (e.g., forming memory pillars), and a first subset of the cavity array can be used to form the smallest associated features (e.g., memory pillars). Conductors can be formed, at least in part, by merging two or more cavities from a second subset of the cavity array. For example, selective material removal can be used to merge cavity patterns (e.g., to form a gap extending between two or more adjacent cavities (e.g., one or more nearest neighbor cavities), or to remove all material between adjacent cavities), and conductive material can be formed in the merged cavities to form conductive pillars. This merging can support the formation of conductors with a cross-section larger than that of a single cavity. Thus, a uniform pattern of cavities can be formed to maintain processing and structural consistency across the memory die, and some cavities can be merged to provide larger openings for conductors to achieve desired conductivity or resistivity values. Additionally, forming memory pillars and conductive pillars from the same cavity array can result in improved processing efficiency and reduced production costs.

[0013] refer to Figure 1 and 2 , features of the present disclosure are described and illustrated in the context of systems, devices, and circuits. Figures 3 to 14 , features of the disclosure are described and illustrated in the context of materials arrangements and methods.

[0014] Figure 1 An example of a memory device 100 supporting merged cavities for forming conductors in a memory die is illustrated according to examples as disclosed herein. Figure 1is an illustrative representation of various components and features of memory device 100. Thus, the components and features of memory device 100 are shown to illustrate functional interrelationships, not necessarily physical locations within memory device 100. Furthermore, although numerical indicators are used to label Figure 1 Some elements are included, but some other corresponding elements (even though they are identical or would be understood to be similar) are not labeled to increase visibility and clarity of the depicted features.

[0015] Memory device 100 may include one or more memory cells 105, such as memory cell 105-a and memory cell 105-b. In some examples, memory cell 105 may be a NAND memory cell, such as shown in the enlarged view of memory cell 105-a. Each memory cell 105 may be programmed to store a logic value representing one or more bits of information. In some examples, a single memory cell 105—such as a memory cell 105 configured as a single-level cell (SLC)—can be programmed into one of two supported states and, thus, can store one bit of information (e.g., a logic 0 or a logic 1) at a time. In some other examples, a single memory cell 105—such as a memory cell 105 configured as a multi-level cell (MLC), a three-level cell (TLC), a four-level cell (QLC), or other types of multi-level memory cells 105—can be programmed into one of more than two supported states and, thus, can store more than one bit of information at a time.

[0016] In some NAND memory arrays, each memory cell 105 may be described as a transistor that includes a charge-trapping structure (e.g., floating gate, replacement gate, dielectric material) for storing an amount of charge representing a logical value. Figure 1The enlarged view in FIG. 1 illustrates a NAND memory cell 105 - a including a transistor 110 (e.g., a metal oxide semiconductor (MOS) transistor) that can be used to store a logic value. Transistor 110 can include a control gate 115 and a charge-trapping structure 120 (e.g., a floating gate, a replacement gate), wherein in some examples, charge-trapping structure 120 can be between two portions of dielectric material 125. Transistor 110 can also include a first node 130 (e.g., a source or drain) and a second node 135 (e.g., a drain or source). A logic value can be stored in transistor 110 by storing (e.g., writing) a certain number of electrons (e.g., a certain amount of charge) on charge-trapping structure 120. The amount of charge to be stored on charge-trapping structure 120 can depend on the logic value to be stored. The charge stored on charge-trapping structure 120 may affect the threshold voltage of transistor 110, thereby affecting the amount of current that flows through transistor 110 when transistor 110 is activated (e.g., when a voltage is applied to control gate 115, when reading memory cell 105-a). In some examples, charge-trapping structure 120 may be an example of a floating gate or a replacement gate. For example, a NAND array may include multiple control gates 115 and charge-trapping structures 120 arranged around a single channel (e.g., a horizontal channel, a vertical channel, a pillar channel, a pillar channel).

[0017] The logic value stored in transistor 110 can be sensed (e.g., as part of a read operation) by applying a voltage to control gate 115 (e.g., applied to control node 140 via word line 165) to activate transistor 110 and measuring (e.g., detecting, sensing) the amount of current flowing through first node 130 or second node 135 (e.g., via bit line 155). For example, sensing component 170 can determine whether SLC memory cell 105 stores a logic 0 or a logic 1 in a binary manner (e.g., based on the presence or absence of current through memory cell 105 when a read voltage is applied to control gate 115, based on whether the current is above or below a threshold current). For multi-level memory cells 105, sensing component 170 can determine the logic value stored in memory cell 105 based on various intermediate threshold levels of current when a read voltage is applied to control gate 115, or by applying different read voltages to the control gate and evaluating different resulting current levels through transistor 110, or various combinations thereof.

[0018] SLC memory cell 105 can be written by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to memory cell 105 to store or not store charge on charge-trapping structure 120 and thereby cause memory cell 105 to store one of two possible logical values. For example, when a first voltage is applied to control node 140 (e.g., via word line 165) relative to body node 145 (e.g., a bulk node) of transistor 110 (e.g., when control node 140 is at a higher voltage than the body), electrons can tunnel into charge-trapping structure 120. Injecting electrons into charge-trapping structure 120 can be referred to as programming memory cell 105 and can occur as part of a write operation. In some cases, a programmed memory cell can be considered to store a logical 0. When a second voltage is applied to control node 140 (e.g., via word line 165) relative to body node 145 of transistor 110 (e.g., when control node 140 is at a lower voltage than body node 145), electrons may leave charge trapping structure 120. Removing electrons from charge trapping structure 120 may be referred to as erasing memory cell 105 and may occur as part of an erase operation. In some cases, an erased memory cell may be considered to store a logic 1. In some cases, memory cells 105 may be programmed at a page granularity due to a page sharing a common word line 165, and erased at a block granularity due to a block sharing a commonly biased body node 145.

[0019] In some examples, writing to a multi-level (e.g., MLC, TLC, or QLC) memory cell 105 may involve applying different voltages to the memory cell 105 (e.g., to its control node 140 or body node 145) at a finer granularity to more finely control the amount of charge stored on the charge-trapping structure 120, thereby enabling the representation of a larger set of logical values. Thus, relative to an SLC memory cell 105, a multi-level memory cell 105 may provide greater storage density, but in some cases, may involve narrower read or write margins or greater supporting circuitry complexity.

[0020] Charge trapping NAND memory cell 105 can operate similarly to floating gate NAND memory cell 105, but instead of or in addition to storing charge on charge trapping structure 120, charge trapping NAND memory cell 105 can also store charge representing a logic state in dielectric material between control gate 115 and a channel (e.g., the channel between first node 130 and second node 135). Thus, charge trapping NAND memory cell 105 can include charge trapping structure 120, or can implement charge trapping functionality in one or more portions of dielectric material 125, among other configurations.

[0021] In some examples, each page of memory cells 105 can be connected to a corresponding word line 165, and each column of memory cells 105 can be connected to a corresponding bit line 155 (e.g., a digit line). Thus, one memory cell 105 can be located at the intersection of a word line 165 and a bit line 155. This intersection can be referred to as the address of the memory cell 105. In some cases, the word lines 165 and the bit lines 155 can be substantially perpendicular to each other and can be collectively referred to as access lines or select lines. In some examples, the access lines (e.g., word lines 165 and bit lines 155) can be formed in a direction away from the substrate of the memory device 100 and can each be positioned between layers of dielectric material in the array region of the memory device 100. The direction away from the substrate can refer to the thickness (e.g., height) direction and can be subject to some degree of skew associated with the manufacturing process.

[0022] Access to memory cells 105 can be controlled by row decoder 160 and column decoder 150. For example, row decoder 160 can receive a row address from memory controller 180 and activate the appropriate word line 165 based on the received row address. Similarly, column decoder 150 can receive a column address from memory controller 180 and activate the appropriate bit line 155. Thus, by activating one word line 165 and one bit line 155, one memory cell 105 can be accessed. As part of this access, memory cell 105 can be read (e.g., sensed) by sensing component 170. For example, sensing component 170 can be configured to determine the stored logic value of memory cell 105 based on a signal generated by accessing memory cell 105. The signal can include a current, a voltage, or both a current and a voltage on bit line 155 of memory cell 105 and can depend on the logic value stored by memory cell 105. Sensing component 170 can include various circuitry (e.g., transistors, amplifiers) configured to detect and amplify the signal (e.g., current or voltage) on bit line 155. The logic value of memory cell 105 as detected by sense component 170 may be output via input / output component 190. In some cases, sense component 170 may be part of column decoder 150 or row decoder 160, or sense component 170 may be otherwise connected to or in electronic communication with column decoder 150 or row decoder 160.

[0023] Memory cell 105 may be programmed or written to by activating the associated word line 165 and bit line 155 to cause a logic value (e.g., representing one or more bits of information) to be stored in memory cell 105. Column decoder 150 or row decoder 160 may accept data (e.g., from input / output component 190) to be written to memory cell 105. In the case of NAND memory, memory cell 105 may be written to by storing electrons in a charge-trapping structure or insulating layer.

[0024] Memory controller 180 can control the operation (e.g., reading, writing, rewriting, refreshing) of memory cell 105 through various components (e.g., row decoder 160, column decoder 150, sensing component 170). In some cases, one or more of row decoder 160, column decoder 150, and sensing component 170 can be co-located with memory controller 180. Memory controller 180 can generate row and column address signals in order to activate the desired word lines 165 and bit lines 155. In some examples, memory controller 180 can generate and control various voltages or currents used during operation of memory device 100.

[0025] In some techniques for fabricating memory device 100 (e.g., for fabricating a memory die incorporating one or more aspects of memory device 100), one or more materials may be deposited over a substrate (e.g., a semiconductor substrate), and portions of the one or more materials may be removed according to various patterning operations. According to examples disclosed herein, an array of cavities may be formed through the stack of material layers of the memory die to support aspects of memory device 100, and conductors (e.g., conductive pillars, conductors associated with word lines 165 or bit lines 155) may be formed, at least in part, by merging some of the cavities of the array. For example, a subset of such cavities (e.g., pillars used to form memory cells 105) may be sized according to the relative minimum features for implementing such cavities, and the smallest associated features may be formed using a first subset of the cavity array. A conductor may be formed, at least in part, by merging two or more cavities from a second subset of the cavity array. For example, selective material removal may be used to merge the cavity patterns (e.g., to form a void extending between two or more adjacent cavities, or to remove all material between the cavities), and conductive material may be formed in the merged cavities to form the conductive pillars. This merging allows conductors to be formed with a larger cross-section than that of a single cavity. Consequently, a uniform pattern of cavities can be formed to maintain processing and structural consistency across the memory die, and some cavities can be merged to provide larger openings for the conductors to achieve a configured conductivity or resistivity value. Additionally, forming memory pillars and conductive pillars from the same cavity array can result in improved processing efficiency and reduced production costs.

[0026] Figure 2 An example of a memory architecture 200 that supports merged cavities for forming conductors in a memory die according to examples as disclosed herein is illustrated. The memory architecture 200 can be an example of a portion of a memory device, such as the memory device 100. Although Figure 2 Some elements in a group of elements (e.g., an array of elements) are included, but some elements may be omitted for the sake of visibility and clarity of the depicted elements. Figure 2 Some elements included in the memory architecture 200 are labeled, while some other corresponding elements are not labeled, even though they are identical or would be understood by one of ordinary skill in the art to be similar. Aspects of the memory architecture 200 may be described with reference to the x-, y-, and z-directions of an illustrated coordinate system.

[0027] The memory architecture 200 includes a three-dimensional array of memory cells 205, which may be reference Figure 1Examples of memory cells 105 are described (e.g., transistors 110, NAND memory cells). For example, memory cells 205 may be included in a block 210, which may be arranged as a 3D array of m memory cells along the x-direction, n memory cells along the y-direction, and o memory cells along the z-direction. Each memory cell 205 may be located (e.g., addressed) according to an index i along the x-direction, an index j along the y-direction, and an index k along the z-direction (e.g., for locating memory cells 205-a-ijk). The memory device 100 may include any number of one or more blocks 210 according to the examples disclosed herein, and different blocks 210 may be adjacent along the x-direction, along the y-direction, or along the z-direction, or any combination thereof.

[0028] In the example of memory architecture 200, block 210 can be divided into a set of pages 215 (e.g., a number o of pages 215) along the z-direction, including page 215-a-1 associated with memory cells 205-a-111 through 205-a-mn1. In some examples, each page 215 can be associated with the same word line 265 (e.g., reference Figure 1 1. The memory architecture 200 may be associated with a word line 265 (described above), which may be coupled to the control gate 115 of each of the memory cells 205 of the page 215. For example, page 215-a-1 may be associated with word line 265-a-1, and other pages 215-ai may be associated with different respective word lines 265-ai (not shown). In some examples, the word lines 265 according to the memory architecture 200 may be implemented as planar conductors (e.g., in the xy plane) coupled to each of the memory cells 205 of the page 215.

[0029] In the example of the memory architecture 200, the block 210 can also be divided into a set of strings 220 (e.g., a certain number (m×n) of strings 220) in the xy plane, including strings 220-a-mn associated with memory cells 205-a-mn1 through 205-a-mno. In some examples, each string 220 can include a set of memory cells 205 connected in series (e.g., along the z-direction, where the drain of one memory cell 205 in the string 220 can be coupled to the source of another memory cell 205 in the string 220). In some examples, the memory cells 205 of the string 220 can be implemented along a common channel, such as a pillar channel (e.g., a pillar channel, a doped semiconductor pillar) along the z-direction. Each memory cell 205 in the string 220 can be associated with a different word line 265, such that the number of word lines 265 in the memory architecture 200 can be equal to the number of memory cells 205 in the string 220. Thus, a string 220 may include memory cells 205 from multiple pages 215 , and a page 215 may include memory cells 205 from multiple strings 220 .

[0030] In some examples, memory cell 205 can be programmed (e.g., set to a logic-zero value) and read at a granularity (e.g., at the granularity of page 215), but cannot be erased (e.g., reset to a logic-one value) at that granularity (e.g., at the granularity of page 215). For example, NAND memory can instead be erased at a different (e.g., higher) level of granularity (e.g., at the granularity of block 210). In some cases, memory cell 205 can be erased before being reprogrammed. Different memory devices can have different read, write, or erase characteristics.

[0031] In some examples, each string 220 of block 210 can be coupled to a corresponding transistor 230 (e.g., a string select transistor, a drain select transistor) at one end of the string 220 (e.g., along the z-direction) and to a corresponding transistor 240 (e.g., a source select transistor, a ground select transistor) at the other end of the string 220. In some examples, the drain of each transistor 230 can be coupled to a bit line 250 of a set of bit lines 250 associated with block 210, where bit line 250 can be a reference Figure 1 1. An example of a bit line 155 is depicted. The gate of each transistor 230 can be coupled to a select line 235 (e.g., a string select line, a drain select line). Thus, transistors 230 can be used to couple strings 220 to bit lines 250 based on applying a voltage to select line 235 and, therefore, the gates of transistors 230. Although illustrated as separate lines along the x-direction, in some examples, select line 235 can be common to all transistors 230 associated with block 210 (e.g., a commonly biased string select node). For example, like word line 265 of block 210, in some examples, select line 235 associated with block 210 can be implemented as a planar conductor (e.g., in the xy plane) coupled to each of the transistors 230 associated with block 210. In some examples, access lines (e.g., bit line 250 and word line 265) can be formed in a direction away from the substrate of memory device 100 and can each be positioned between layers of dielectric material in the array region of memory device 100. The direction away from the substrate may be referred to as the z-direction (eg, thickness or height direction), and may be subject to some degree of bias associated with the manufacturing process.

[0032] In some examples, the source of each transistor 240 associated with a block 210 can be coupled to a source line 260 associated with the block 210 from a set of source lines 260. In some examples, the set of source lines 260 can be associated with a common source node (e.g., a ground node) corresponding to the block 210. The gate of each transistor 240 can be coupled to a select line 245 (e.g., a source select line, a ground select line). Thus, the transistors 240 can be used to couple the string 220 to the source line 260 based on applying a voltage to the select line 245 and, therefore, the gate of the transistor 240. Although illustrated as a single line along the x-direction, in some examples, the select line 245 can also be common to all transistors 240 associated with the block 210 (e.g., a commonly biased ground select node). For example, like word lines 265 of block 210 , select lines 245 associated with block 210 may in some examples be implemented as a planar conductor (eg, in the xy plane) coupled to each of transistors 240 associated with block 210 .

[0033] To operate the memory architecture 200 (e.g., to perform a program operation, a read operation, or an erase operation on one or more memory cells 205 of the block 210), various voltages may be applied to one or more select lines 235 (e.g., gates of transistors 230), one or more bit lines 250 (e.g., drains of one or more transistors 230), one or more word lines 265, one or more select lines 245 (e.g., gates of transistors 240), one or more source lines 260 (e.g., sources of transistors 240), or the bodies of the memory cells 205 (not shown) of the block 210. In some cases, each memory cell 205 of a block 210 may have a common body whose voltage may be controlled independently of the bodies of other blocks 210.

[0034] In some cases, as part of a read operation for a memory cell 205, a positive voltage may be applied to the corresponding bit line 250, while the corresponding source line 260 may be grounded or otherwise biased at a voltage lower than the voltage applied to the bit line 250. In some examples, for a memory cell 205, a voltage higher than the threshold voltage of transistors 230 and 240, respectively, may be concurrently applied to select lines 235 and 245, thereby activating transistors 230 and 240 so that a channel (e.g., a pillar channel) associated with the string 220 including the memory cell 205 may be electrically connected to (e.g., electrically connected between) the corresponding bit line 250 and source line 260. A channel may be an electrical path through the memory cells 205 in the string 220 (e.g., through the sources and drains of the transistors in the memory cells 205 of the string 220) that may conduct current under some operating conditions.

[0035] In some examples, multiple word lines 265 (e.g., in some cases, all word lines 265) of a block 210, except for word lines 265 associated with a page 215 of memory cells 205 to be read, can be concurrently set to a voltage (e.g., VREAD) that is higher than the threshold voltage (VT) of the memory cells 205. VREAD can cause all memory cells 205 in an unselected page 215 to be activated, so that each unselected memory cell 205 in a string 220 can maintain high conductivity within the channel. In some examples, the word line 265 associated with the memory cell 205 to be read can be set to a voltage VTarget. In the case where the memory cells 205 are operated as SLC memory cells, VTarget can be a voltage between (i) the VT of a memory cell 205 in an erased state and (ii) the VT of a memory cell 205 in a programmed state.

[0036] When the memory cell 205 to be read exhibits an erased VT (e.g., VTarget > VT of memory cell 205), the memory cell 205 can be turned “on” in response to applying VTarget to the word line 265 of the selected page 215, which can allow current to flow in the channel of the string 220, and therefore, from the bit line 250 to the source line 260. When the memory cell 205 to be read exhibits a programmed VT (e.g., VTarget < VT of the selected memory cell), the memory cell 205 can remain “off” despite applying VTarget to the word line 265 of the selected page 215, and therefore, current can be prevented from flowing in the channel of the string 220, and therefore, from the bit line 250 to the source line 260.

[0037] can (for example, by reference to Figure 1 The sensing component 170 described above senses a signal (e.g., an amount of current below or above a threshold) on the bit line 250 of the memory cell 205, and the signal can indicate whether the memory cell 205 becomes conductive or remains non-conductive in response to applying VTarget to the word line 265 of the selected page 215. Thus, the sensed signal can indicate whether the memory cell 205 is in an erased state (e.g., storing a logic 1) or a programmed state (e.g., storing a logic 0). Although aspects of the above example read operation have been explained in the context of an SLC memory cell 205 for clarity, such techniques can be expanded or modified and applied in the context of a multi-level memory cell 205 (e.g., by using multiple VTarget values ​​corresponding to different amounts of charge that can be stored in one multi-level memory cell 205).

[0038] In some cases, as part of a programming operation for memory cell 205, charge may be added to a portion of memory cell 205 so that when memory cell 205 is later read, current through memory cell 205 and, therefore, corresponding string 220 may be suppressed. For example, charge may be injected into charge trapping structure 120, as in Figure 1 2. Memory cell 105-a is shown in FIG. 2. In some cases, respective voltages may be applied to word line 265 of page 215 and the body of memory cell 205 to be programmed, such that control gate 115 of memory cell 205 is at a higher voltage than the body of memory cell 205 (e.g., a positive voltage may be applied to the word line). Voltages higher than the threshold voltages of transistors 230 and 240, respectively, may be concurrently applied to select lines 235 and 245, thereby activating transistors 230 and 240, and setting bit line 250 of memory cell 205 to be programmed to a relatively high voltage. This may induce an electric field that pulls electrons from the source to the drain of memory cell 205. The electric field may also cause some of these electrons to be pulled through dielectric material 125 and thereby injected into charge-trapping structure 120 of memory cell 205 through a process that may, in some cases, be referred to as tunnel injection.

[0039] In some cases, a single programming operation can program some or all of the memory cells 205 in a page 215 because the memory cells 205 of a page 215 can all share a common word line 265 and a common body. For memory cells 205 of a page 215 to which it is not desired to write a logic 0 (e.g., to a memory cell 205 to which programming is not desired), the corresponding bit line 250 can be set to a relatively low voltage (e.g., ground), which can inhibit electron injection into the charge trapping structure 120. Although aspects of the above example programming operations have been explained in the context of SLC memory cells 205 for clarity, such techniques can be extended and applied to the context of multi-level memory cells 205 (e.g., by using multiple programming voltages applied to the word line 265, or multiple passes or pulses of the programming voltage applied to the word line 265, corresponding to different amounts of charge that can be stored in one multi-level memory cell 205).

[0040] In some cases, as part of an erase operation for memory cell 205, charge may be removed from a portion of memory cell 205 so that when memory cell 205 is later read, current flow through memory cell 205 and, therefore, corresponding string 220 may not be inhibited (e.g., at least permitted to a greater extent). For example, charge may be removed from charge trapping structure 120, such as Figure 1205 - a. In some cases, respective voltages can be applied to the word line 265 of the page 215 and the body of the memory cell 205 to be erased such that the control gate 115 of the memory cell 205 is at a lower voltage than the body of the memory cell 205 (e.g., a positive voltage can be applied to the body), which can induce an electric field that pulls electrons out of the charge-trapping structure 120 and into the body of the memory cell 205. In some cases, a single programming operation can erase all of the memory cells 205 in the block 210 because the memory cells 205 of the block 210 can all share a common body.

[0041] In some techniques for fabricating memory architecture 200 (e.g., for fabricating a memory die incorporating one or more aspects of memory architecture 200), one or more materials may be deposited over a substrate (e.g., a semiconductor substrate), and portions of the one or more materials may be removed according to various patterning operations. According to examples disclosed herein, an array of cavities may be formed through the stack of material layers of the memory die to support aspects of memory architecture 200, and conductors (e.g., conductive pillars, conductors associated with word lines 265, bit lines 250, select lines 235, select lines 245, and source lines 260) may be formed, at least in part, by merging some of the cavities of the array. For example, a subset of such cavities (e.g., for forming strings 220) may be sized according to the relative minimum features for implementing such cavities, and the smallest associated features may be formed using a first subset of the cavity array. A conductor may be formed, at least in part, by merging two or more cavities from a second subset of the cavity array. For example, selective material removal may be used to merge the cavity pattern, and conductive material may be formed in the merged cavities to form the conductive pillars. This merging can allow the cavities for the conductors to be formed with a larger cross-section than that of a single cavity. Thus, a uniform pattern of cavities can be formed to maintain processing and structural consistency across the memory die, and some cavities can be merged to provide larger openings for the conductors to achieve a configured conductivity or resistivity value. Additionally, forming memory pillars and conductive pillars from the same cavity array can result in improved processing efficiency and reduced production costs.

[0042] Figures 3 to 13 Examples of fabrication operations that can support merged cavities for forming conductors in memory dies according to examples as disclosed herein are described. For example, Figures 3 to 13 Aspects of the operational sequence for manufacturing aspects of the material arrangement 300 may be described, which may be a reference for implementation. Figure 2 Examples of aspects of the described memory architecture 200 and other types of memory architectures. Figures 3 to 13Each of the figures may illustrate aspects of the material arrangement 300 after a different subset or alternative of fabrication operations used to form the material arrangement 300 (e.g., material arrangement 300-a illustrated as after a first set of one or more fabrication operations, material arrangement 300-b illustrated as after a second set of one or more fabrication operations, etc.). As illustrated, each view in the figures may be described with reference to an x-direction, a y-direction, and a z-direction, which directions may correspond to respective directions described with reference to the memory architecture 200.

[0043] Some of the provided figures include cross-sectional views illustrating example cross sections of the material arrangement 300. For example, in Figures 3 to 5 , view "Section AA" can be associated with a cross-section (e.g., according to section AA) in the xz plane through material arrangement 300 associated with a portion of a set of cavities (e.g., a cavity including at least one memory cell 205 for at least one memory cell 205 along the z-direction, such as string 220). Although material arrangement 300 illustrates some examples of relative sizes and quantities of various features, according to examples as disclosed herein, aspects of material arrangement 300 can be implemented utilizing other relative sizes or quantities of such features.

[0044] Figures 3 to 13 Described and referenced in Figures 3 to 13 The described operations can be performed by a manufacturing system, such as a semiconductor manufacturing system, configured to perform additive operations (e.g., deposition, epitaxy, bonding), subtractive operations (e.g., etching, trenching, planarization, polishing), modification operations (e.g., oxidation, doping, reaction, conversion), and support operations (e.g., masking, patterning, lithography, alignment), as well as other operations supporting the described techniques. In some examples, the operations performed by such a manufacturing system may be supported by a process controller or components thereof as described herein.

[0045] Figure 3 An example of a material arrangement 300 after a first set of one or more fabrication operations is illustrated (e.g., as material arrangement 300-a). As illustrated, material arrangement 300-a may be associated with region 301 (e.g., an array region associated with one or more blocks 210), including cavity 305 associated with an array of memory cells 205, and regions 302 and 306 (e.g., contact regions, wordline contact regions), including cavity 310 that may be associated with forming conductors to deliver signals associated with accessing memory cells 205. Each of cavities 305 and 310 may extend through at least a portion of material arrangement 300-a along the z-direction. In material arrangement 300-a, at least some features of regions 301 and 302 may be electrically isolated from one another, which may be supported by isolation regions 303 or isolation regions 304 (e.g., trench isolation regions), or various combinations thereof. In some examples, features associated with isolation regions 304 may be omitted from material arrangement 300-a.

[0046] The first set of operations may include forming a layer of material 325 (e.g., depositing material 325 over substrate 315), which may include a conductive material (e.g., a metal, a metal alloy, a conductive ceramic, such as tungsten silicide). In some examples, the layer of material 325 may support a ground node of the memory architecture 200, such as a source node (e.g., source line 260, a common source) of one or more blocks 210. Although material 325 is shown in regions 302, 303, and 304, in some examples, at least a portion of material 325 may be omitted from one or more of regions 302, 303, or 304. Although the layer of material 325 may be formed in contact with substrate 315, in some other examples, the material arrangement 300-a may include other materials or components between the layer of material 325 and substrate 315. The substrate 315 may include or otherwise be associated with circuitry 320, which may include interconnect or routing circuitry (e.g., access lines, power routing lines), control circuitry (e.g., transistors, logic, decoding circuitry, addressing circuitry, aspects of the memory controller 180, column decoder 150, row decoder 160, sensing components 170, input / output components 190), and other circuitry, which may include various conductor, semiconductor, or dielectric materials of the substrate 315, or between the layer of material 325 and the substrate 315, as well as other configurations. For example, the circuitry 320 may include an arrangement of complementary metal oxide semiconductor (CMOS) transistors or thin film transistors (TFTs), or any combination thereof, at least partially between the substrate 315 and the layer of material 325, and the like.

[0047] The first set of operations may also include forming a stack 330 (e.g., forming a material layer stack, depositing a material layer stack) over substrate 315 (e.g., over the layer of material 325), which may support the formation of various components that support access to memory cell 205 (e.g., in region 301). In some examples, stack 330 may include a layer of material 331, a layer of material 332, a layer of material 333, and a layer of material 334. In some examples, material 331 may be a semiconductor material (e.g., doped polysilicon, n+ doped polysilicon) that may support the formation of a channel portion of transistor 240. In some examples, each of material 332, material 333, and material 334 may be a sacrificial material, at least a portion of which may be patterned and removed in a later processing operation. In some examples, material 332, material 333, and material 334 may be selected to support various techniques for differential processing (e.g., differential etching, high selectivity). For example, material 332 may be a dielectric material (e.g., oxide, silicon oxide, liner oxide), material 333 may be a semiconductor material (e.g., polysilicon), and material 334 may be a dielectric material (e.g., oxide, silicon oxide, cap oxide) that may be the same as material 332.

[0048] In some examples, the first set of operations may include operations that support the formation of an etch stop in stack 330 (e.g., a vertical etch stop to prevent material removal beyond stack 330 in at least some areas of material arrangement 300-a). For example, the first set of operations may include operations for forming a cavity aligned with the position of cavity 305 (e.g., in the xy plane) and forming a trench aligned along the position of isolation region 303. In some examples, such trenches may be connected with other such trenches (e.g., along the x-direction) to provide trench isolation around each portion of material arrangement 300-a associated with block 210 (e.g., enclosing an area associated with block 210 in the xy plane, enclosing region 301, or a portion thereof). Such cavities and trenches may extend at least partially through the layer of material 321, thereby supporting the formation of material 335 (e.g., oxidation-doped polysilicon, which may include oxidizing material 331) along the bottom and sidewalls of the cavities and trenches. In some examples, after forming the etch stop feature in stack 330, a first set of operations may include forming (e.g., depositing, oxidizing) a layer of material 336 and a layer of material 337 over stack 330. Material 336 may be an oxide material (e.g., silicon oxide), and material 337 may be a semiconductor material (e.g., polysilicon). In some examples, material 336 may be a sacrificial material (e.g., a portion of which is removed in one or more subsequent operations), and material 337 may support the formation of one or more transistor structures (e.g., as part of a channel of transistor 240 of memory architecture 200).

[0049] The first set of operations may also include forming a stack 340 (e.g., forming a material layer stack, depositing a material layer stack), which may include various forming operations. For example, forming stack 340 may include forming alternating layers of material 341 and material 342 (e.g., according to alternating material deposition or other forming operations). In some examples, material 341 may include a dielectric material (e.g., an oxide, a layer oxide, an oxide of silicon) that may provide electrical isolation between features of material arrangement 300-a (e.g., between pages 215, between word lines 265, along the z-direction). Material 342 may include various materials different from material 341 (e.g., a nitride material, a nitride of silicon) and may be a sacrificial material (e.g., to support a subsequent differential etching process). Although stack 340 is illustrated as having twenty-five layers (e.g., thirteen layers of material 341 and twelve layers of material 342), according to examples disclosed herein, stack 340 may include any number of layers (e.g., tens of layers, hundreds of layers, etc.) of each of two or more materials, including as few as one layer of material 342.

[0050] The first set of operations may also include operations for forming cavities 310. For example, the first set of operations may include operations (e.g., dry etching operations, photolithography operations) for forming cavities 310 through stacks 340 and 330 in regions 302 and 306 (e.g., exposing electrical contacts associated with circuitry 320, such as conductive material portions). In some examples, one or more cavities 310 may be aligned with a group of corresponding cavities 305 along the y-direction or another direction (e.g., a row of cavities 305 along the x-direction or another direction). In some examples, cavities 305 and 310 may be formed in a continuous pattern (e.g., without discontinuities along one or more directions in the xy plane), which may include regions 306 directly adjacent to regions 301, among other examples.

[0051] Forming cavities 310 and cavities 305 can support forming contacts associated with one or more cavities 310 (e.g., of region 302) and coupled to bit lines 250 formed above the set of corresponding cavities 305 (e.g., along the z-direction). However, for other purposes, cavities 310 can be formed in region 302 or region 306 and can therefore be arranged in various other configurations. Cavities 310 can be formed via openings (e.g., cross-sectional openings, openings in the xy plane) that do not overlap with each other (e.g., in the xy plane). In some examples, the openings used to form cavities 310 can have the same or similar cross-section (e.g., size, shape) as the openings used to form cavities 305. Additionally or alternatively, the openings used to form cavities 310 can be formed in the same or similar pattern (e.g., a honeycomb pattern, which can include the same or similar spacing between openings) as the openings used to form cavities 305. Formation cavity 310 may be associated with sidewalls of the one or more materials that form (eg, expose) stacks 340 and 330 , and such sidewalls may have a shape that tapers along the z-direction.

[0052] While in some examples, cavities 310 can be formed through stack 340 and stack 330 in a single material removal operation, in some other examples, such cavities can be formed using a sequence of material removal operations. For example, for each cavity 310, a respective first cavity can be formed through at least stack 330 and, in some examples, through one or both of material 336 or material 337, and each first cavity can be filled with a sacrificial material (e.g., sacrificial carbon, with or without a lining material, or a stack of different materials). In some examples, such operations can be performed before forming stack 340. A respective second cavity can be formed through at least a subset of the material layers of stack 340 that is coincident with (e.g., aligned with) the respective first cavity (e.g., coaxially along the z-direction according to an alignment tolerance in the xy plane) (e.g., before forming another subset of the material layers of stack 340), and the second cavity can be filled with a sacrificial material (e.g., coincident with the previously formed sacrificial material over which another subset of the material layers of stack 340 can be formed). This sequence may be repeated for any number of iterations, and a single collective cavity 310 may be formed by removing sacrificial material from earlier cavity fill operations.

[0053] The first set of operations may also include operations for forming cavities 305. For example, the first set of operations may include operations (e.g., dry etching operations, photolithography operations) for forming cavities 305 in region 301 through stack 340 and through at least a portion of stack 330 (e.g., exposing a portion of material 325, using material 325 as a cavity etch stop). Cavities 305 may be formed in a pattern that may include staggered rows to improve the density of cavities 305 (e.g., in the xy plane). Cavities 305 may be formed through openings that do not overlap one another, and forming cavities 305 may be associated with forming sidewalls of one or more materials of stacks 340 and 330. In some examples, one or more operations associated with forming cavities 305 may be performed concurrently with corresponding operations (e.g., etching operations, sacrificial material deposition operations) associated with forming cavities 310 (e.g., one or more operations may occur during overlapping durations or during the same duration or process). For example, cavity 305 and cavity 310 may be formed using similar patterns (eg, etch patterns) and may have similar dimensions (eg, opening size, shape, depth).

[0054] While in some examples, cavities 305 can be formed through at least stack 340 in a single material removal operation, in some other examples, cavities 305 can be formed using a sequence of material removal operations. For example, for each cavity 305, a respective first cavity can be formed through a first subset of the material layers of stack 340, and the first cavity can be filled with a sacrificial material (e.g., before forming a second subset of the material layers of stack 340). A respective second cavity aligned with the respective first cavity can be formed through a second subset of the material layers of stack 340, and the second cavity can be filled with a sacrificial material. This sequence can be repeated for any number of iterations, and a single collective cavity 305 can be formed by removing sacrificial material from an earlier cavity-filling operation.

[0055] In some examples, each cavity 305 and cavity 310 can be filled with a sacrificial material 351 (e.g., sacrificial carbon or a different material). In some cases, each cavity 310 can be filled with sacrificial material 351 during one or more fill operations that also include forming the sacrificial material in each cavity 305 (e.g., concurrently). In some examples, after forming cavity 310, a first set of operations can include forming a layer of material 355 (e.g., a dielectric material, an oxide of silicon) over stack 340 that can provide a barrier to protect cavity 305 or cavity 310 during subsequent operations (e.g., which can involve removing sacrificial material 351 from a subset of cavities to perform subsequent operations).

[0056] Cavity 305 can participate in various operations that support the formation of memory cells associated with cavity 305 (e.g., memory cell 105, memory cell 205, or memory cells of string 220). For example, sacrificial material 351 can be removed from each cavity 305, and at least material 361 and material 362, and in some examples, material 363, can be formed (e.g., deposited, oxidized) in the formed cavity associated with cavity 305 to form pillars 307 (e.g., cell pillars, memory pillars, corresponding to string 220). Cavity 305 can extend along the z-direction, such that pillars 307 formed in cavity 305 can have an extent along the z-direction. Material 361 can support the charge-trapping function of memory cell 205 and, in various examples, can include one or more layers of material. In some examples, material 361 may include: a first layer (e.g., a dielectric layer, an oxide layer, or silicon oxide) in contact with the walls of the formed cavity, which may support the first dielectric material 125 of the string of memory cells 205; a second layer (e.g., a charge-trapping layer, a nitride layer, or silicon nitride) above the first layer, which may support the charge-trapping structure 120 of the string of memory cells 205; and a third layer (e.g., a dielectric layer, an oxide layer, or silicon oxide) above the second layer, which may support the second dielectric material 125 of the string of memory cells 205. Material 362 may be a semiconductor material (e.g., polysilicon in contact with material 361 or the third layer thereof) that may support a channel portion (e.g., between the respective first node 130 and second node 135) of the string of memory cells 205. Material 363 may be a dielectric material (e.g., silicon oxide in contact with material 362), which, in some examples, may fill the remainder of the cavity. In some examples, at least a portion of material 363 can be removed from the top of cavity 305 (e.g., recessed), and additional portions of material 362 can be formed (e.g., deposited, oxidized) to fill the top portion of cavity 305 (e.g., in a plug formation operation). In some examples, after forming pillar 307, a first set of operations can include forming a layer of material 365 (e.g., a dielectric, an oxide of silicon) over stack 340, which can provide a barrier to protect pillar 307 during subsequent operations.

[0057] The first set of operations may also include various operations (e.g., dry etching operations, photolithography operations) for forming trenches 370 along isolation regions 303 through stack 340 and through at least a portion of stack 330 (e.g., exposing a portion of material 325, using material 325 as a trench etch stop). In some examples, one or more operations associated with forming trenches 370 for isolation regions 303 may be performed concurrently with corresponding operations associated with forming cavities for pillars 307 (e.g., etching operations, sacrificial material deposition operations). While in some examples, trenches 370 may be formed through at least stack 340 in a single material removal operation, in some other examples, trenches 370 may be formed using a sequence of material removal operations. For example, for each isolation region 303, a respective first trench may be formed through a first subset of the material layers of stack 340, and the first trenches may be filled with sacrificial material (e.g., before forming a second subset of the material layers of stack 340). A corresponding second trench aligned with the corresponding first trench can be formed through a second subset of the material layers of stack 340, and the second trench can be filled with a sacrificial material. This sequence can be repeated for any number of iterations, and trench 370 can be formed by removing the sacrificial material from the earlier trench fill operation. In some examples, forming trench 370 can involve removing at least a portion of material 355 or material 365 from isolation region 303.

[0058] Opening trench 370 can support the formation of structures associated with pillar 307. For example, void 371 can be formed through trench 370, which can include removing (e.g., via a wet etching operation) exposed portions of material 332, material 333, material 334, material 336, and material 361. In some examples, such an operation can be performed by forming a liner material (not shown) on surfaces of stack 340 associated with trench 370, which can prevent the removal of material 341 and material 342 during such an operation. Material 375 can be formed in void 371, which can further support aspects of forming transistor 240. For example, material 375 can include a semiconductor material (e.g., a doped polysilicon material, n+ doped polysilicon material), which can be the same as material 331. In some examples, after forming material 375, the liner along trench 370 can be removed, and the exposed surfaces of material 331 and material 375 can be oxidized to form additional portions of material 335.

[0059] In some examples, forming word line 265 in material arrangement 300-a may involve forming a void by removing portions of material 342 from stack 340 in region 301, and forming one or more conductive materials in the formed void. However, with some techniques for forming such voids, the extent of removal of material 342 (e.g., along the x-direction, along the y-direction) may be uncertain or otherwise difficult to control due to variations in material removal rates and varying material removal sizes. As a result, in some examples, the void may extend into region 302 as well as other regions (e.g., between adjacent regions 301 that are intended to be electrically isolated), which may allow conductive material to undesirably form near cavity 310 or between cavity 310 and cavity 305, as well as other features of the material arrangement that are intended to be electrically isolated. Although in some instances, cavity 310 may be positioned relatively away from trench 370 to avoid adverse coupling with conductive material, in other techniques used to compensate for uncertain or otherwise variable degrees of voids and conductor deposition, such techniques may be associated with relatively inefficient utilization of the area of ​​material arrangement 300-a (e.g., in the xy plane).

[0060] In some examples, to form features of isolation region 304, a first set of operations may include operations (e.g., dry etching operations, photolithography operations) for forming trench 380 along isolation region 304 through at least stack 340, and in some examples, through stack 330 and the layer of material 325. In some examples, one or more operations associated with forming trench 380 for isolation region 304 may be performed concurrently with corresponding operations associated with forming cavity 310 (e.g., etching operations, sacrificial material deposition operations). While in some examples, trench 380 may be formed in a single material removal operation, in some other examples, trench 380 may be formed using a sequence of material removal operations, according to examples disclosed herein (e.g., as described with reference to forming cavity 310). After forming trench 380, material 381 may be formed (e.g., deposited, oxidized) in trench 380. Material 381 may include a dielectric material (e.g., an oxide, silicon oxide).

[0061] Figure 4The material arrangement 300 after a second set of one or more fabrication operations is illustrated in a cross-sectional side view (e.g., relative to section AA) (e.g., as material arrangement 300-b). The second set of operations may include operations (e.g., wet etching operations, excavation operations) that support the formation of word lines 265 in region 301. For example, the second set of operations may include forming voids 405 between layers of material 341 by removing material 342 from portions of stack 340 (e.g., in region 301). Forming voids 405 may expose portions of pillars 307 (e.g., exposing sidewalls of material 361 between layers of material 341), which may remain in contact with material 341 and support material 341 across voids 405 (e.g., along the z-direction) for forming word lines (e.g., word lines 265) in various structures of memory architecture 200. In some examples, voids 405 may extend as far as isolation regions 304, which may include exposing sidewalls of material 381 between layers of material 341. However, by including isolation region 304 , void 405 may not extend into region 302 (eg, such that a layer of material 342 of stack 340 may remain in region 302 ), which may prevent conductive material from forming in region 302 during formation of word line 265 .

[0062] Figure 5 The material arrangement 300 is illustrated in a cross-sectional side view (e.g., relative to section AA) after a third set of one or more fabrication operations (e.g., as material arrangement 300-c). The third set of operations may include further operations (e.g., one or more deposition operations, metal fill operations, etching operations) that support the formation of word line 265 between layers of material 341 (e.g., in portions of void 405). For example, the third set of operations may include forming (e.g., depositing) material 505 in void 405 (e.g., between layers of material 341), which may include forming material 505 in contact with pillar 307 or otherwise electrically coupled (e.g., in contact with material 361). Material 505 may include one or more conductive materials, such as tungsten, which may be the same as material 325. In some examples, forming material 505 can include forming (e.g., depositing, oxidizing) a dielectric material (e.g., aluminum oxide) in contact with pillar 307 (e.g., in contact with material 361 prior to depositing one or more conductive materials), which can support the dielectric function (e.g., dielectric material 125) of memory cell 205. Portions of material 505 can be removed from portions of void 405 (e.g., in a recess etch operation) to provide electrical isolation between word lines 265.

[0063] The third set of operations may also include operations (e.g., one or more deposition operations, one or more oxidation operations) that support forming electrical isolation in isolation region 303 based at least in part on forming (e.g., depositing, oxidizing) material 510 in region 303 (e.g., in at least some portion of trench 370 and void 405). Material 510 may be a dielectric material (e.g., an oxide, an oxide of silicon), which may be the same as material 355 or material 365 and other materials of material arrangement 300.

[0064] The third set of operations may be followed by other operations to support aspects of the memory architecture 200, such as forming a bit line 250 coupled to the string 220 (e.g., a conductive line above the material arrangement 300-c, which may be aligned along the x-direction and operable for coupling between the material 362 and the conductor), and forming a vertical direct contact (e.g., a vertical conductor) coupled to each of the word lines 265 (e.g., a contact electrically coupled to a corresponding layer of material 505), among other features.

[0065] Figures 6 to 9 A first alternative approach to implementing merged cavities (eg, implementing a complete merge of cavity 310 ) for forming conductors in a memory die is described according to examples as disclosed herein. Figures 6 to 9 Each of may illustrate aspects of the material arrangement 300 after a different subset of fabrication operations used to form the material arrangement 300 according to the first alternative (e.g., after a third set of operations). Figures 6 to 9 , view "Section BB" can be associated with a cross-section (e.g., according to Section BB) in the xz plane through material arrangement 300 associated with a set of cavities 310 (e.g., including a plurality of cavities 310 for forming and isolating conductors). Although aspects of the first alternative for implementing merged cavities for conductor formation are illustrated in region 306, similar techniques can be implemented using cavities 310 of region 302 and other regions of the memory die to form conductors using merged cavities 310.

[0066] Figure 6 The material arrangement 300 (e.g., material arrangement 300-d) after a fourth set of one or more fabrication operations is illustrated in top view and in cross-sectional side view (e.g., relative to section BB). The fourth set of operations can include operations (e.g., etching operations, wet etching operations, recessing operations) that support forming the merged cavity 605 at least in part by merging the plurality of cavities 310 (e.g., completely merging along the z-direction).

[0067] A fourth set of operations may include operations (e.g., masking operations, photolithography operations, patterning operations) that support the formation of a mask 610 (e.g., a masking material) over the pillars 307 and at least some of the cavities 310 (e.g., in regions 302 and 306). Mask 610 may protect the pillars 307 and at least some of the cavities 310, as well as other intervening features, from subsequent operations (e.g., etching operations, wet etching operations). Forming mask 610 may include patterning operations to expose regions (e.g., in the xy plane) corresponding to the groups of cavities 310 to be merged. For example, mask 610 may include a masking material (e.g., a hard mask) formed over stack 340 in a pattern such that the masking material does not cover the locations of the cavities 310 to be merged. In various examples, the boundaries of the mask 610 (e.g., the boundaries of the openings in the xy plane) may coincide with the boundaries of the cavities 310 (e.g., the openings), or the boundaries of the mask 610 may not coincide with the boundaries of the cavities 310. For example, the boundaries of the mask 610 may be wider than (e.g., and enclose) the cavities 310 to be merged, which may support a relatively larger merged cavity.

[0068] In some cases, different patterns for forming the mask 610 can be employed. For example, the number or pattern of cavities 310 exposed (e.g., grouped) to form the merged cavities 605 can vary from configuration to configuration. Additionally or alternatively, the number or pattern of cavities 310 that remain masked between the exposed locations of the merged cavities 605 can vary from configuration to configuration. Such techniques can result in different spacings between the merged cavities 605 (e.g., for different amounts of electrical isolation), or different amounts (e.g., cross-sections) of conductive material formed within the merged cavities 605. Thus, a uniform pattern of cavities 310 can be formed to maintain processing and structural consistency across the memory die, and different sizes of merged cavities 605 and different spacings between merged cavities 605 can be implemented to achieve desired conductivity or resistivity values.

[0069] A fourth set of operations may include merging (e.g., completely merging) multiple cavities 310 by removing sacrificial material 351 and at least material 341 and material 342 from portions of stack 340 (e.g., along the z-direction, between cavities 310), as well as other materials (e.g., materials 336 and 337, one or more materials of stack 330, or a combination thereof, as applicable). Merging cavities 310 to form merged cavity 605 may form a contiguous region without material between at least two cavities 310. In some examples, forming merged cavity 605 may include removing material to expose circuitry 320 (e.g., conductors of circuitry 320) or a portion of material 325 (e.g., where at least a portion of material 325 in region 306 or other regions is part of a distribution layer or other electrical node, which may not involve exposing conductors of circuitry 320).

[0070] In some examples, forming merged cavities 605 may involve operations (e.g., wet etching operations, recessing operations) that may recess material 342 and expose sidewalls 615 of material 342 between layers of material 341. Thus, the fourth set of operations may result in the formation of one or more protrusions 620 of material 341 toward an axis 625 of a respective merged cavity 605 extending along the z-direction (e.g., toward an axis 625 along the x-direction or along other directions in the xy plane).

[0071] Figure 7 Material arrangement 300 is illustrated in a cross-sectional side view (e.g., relative to section BB) after a fifth set of one or more manufacturing operations (e.g., as material arrangement 300-e). The fifth set of operations may include operations (e.g., one or more deposition operations, metal fill operations) that support the formation of conductor 705, at least in part, by forming material 710 in merged cavity 605. For example, the third set of operations may include forming (e.g., depositing) material 710 in merged cavity 605 (e.g., through at least stack 340 and, in some examples, through stack 340, as applicable). Material 710 may include one or more conductive materials (e.g., a metal, a metal alloy, a conductive ceramic (e.g., tungsten silicide), deposition of an electrode layer followed by bulk-fill deposition of a conductor), which may be the same as material 325 or material 505, or any combination thereof. Cavity 310 and merged cavity 605 may extend along the z-direction, such that conductor 705 may have an extent along the z-direction. The extent along the z-direction may at least partially overlap with the extent along the z-direction associated with the pillar 307 formed in the cavity 305 .

[0072] Forming material 710 may include depositing material 710 within the void formed by the recess in material 342. For example, the void may be formed by removing material (e.g., material 342) as a result of an omnidirectional etch (e.g., a wet etch). Conductor 705 may accordingly have one or more protrusions (e.g., in contact with sidewall 615) extending away from axis 625 (e.g., along the x-direction, or along other directions in the xy plane). In some examples, such techniques may include forming material 710 in contact with or otherwise electrically coupled to material 325 (e.g., where a portion of material 325 in region 306 or other regions is part of a distribution layer or other electrical node, this may not involve forming material 710 in contact with a conductor of circuitry 320). Additionally or alternatively, such techniques may include forming material 710 electrically isolated from material 325, or forming material 710 in contact with or otherwise electrically coupled to circuitry 320 (e.g., in regions where material 325 is omitted). Conductor 705 formed in contact with or otherwise electrically coupled to circuitry 320 may electrically couple the conductor with one or more transistor structures (eg, transistors of circuitry 320 , transistors formed at least in part from a doped portion of substrate 315 ).

[0073] Figure 8 The material arrangement 300 is illustrated in a cross-sectional side view (e.g., relative to section BB) after a sixth set of one or more fabrication operations (e.g., as material arrangement 300-f). The sixth set of operations may include operations (e.g., etching operations, wet etching operations, recessing operations) that support forming electrical isolation between conductors 705. For example, the sixth set of operations may include removing mask 610 and sacrificial material 351 from cavities 310 not associated with conductors 705. The sixth set of operations may also include removing portions of material 342 to form voids 805 (e.g., through regions 306 and between layers of material 341 in at least a portion of other regions). Voids 805 may expose portions of conductors 705 (e.g., sidewalls of material 710 between layers of material 341).

[0074] Figure 9Material arrangement 300 is illustrated in a cross-sectional side view (e.g., relative to section BB) after a seventh set of one or more fabrication operations (e.g., as material arrangement 300-g). The seventh set of operations may include operations that support forming electrical isolation between conductors 705 and other features (e.g., one or more deposition operations, one or more oxidation operations). For example, the seventh set of operations may include forming material 905 in cavities 310 and voids 805. For example, the seventh set of operations may include forming (e.g., depositing) material 905 in at least some of cavities 310 not used to form conductors 705, which may include forming material 905 in contact with exposed portions of material 710. Material 905 may be the same as material 341, material 336, material 355, material 365, material 381, material 510, or any combination thereof, as well as other materials of material arrangement 300, and may be a dielectric material (e.g., an oxide, an oxide of silicon). Material 905 (eg, including isolation pillars 910 associated with cavities 310 filled with material 905 ) may provide electrical isolation between conductor 705 and other features of material arrangement 300 .

[0075] Conductor 705 can support coupling between various features of memory architecture 200. For example, conductor 705 can be implemented as part of electrical coupling between circuitry 320 and any one or more of word line 265 (e.g., a portion of material 505), source line 260, select line 245, bit line 250, or select line 235, as well as other nodes of memory architecture 200, which can support implementation of circuitry 320 for operation of memory architecture 200. This electrical coupling can involve forming one or more conductive materials (not shown) between the respective components (e.g., above or otherwise through region 303, above or below stack 340, as applicable), as well as other examples. Additionally or alternatively, conductor 705 can be implemented to support electrical coupling of other elements of material arrangement 300.

[0076] Figures 10 to 13 A second alternative for implementing merged cavities for forming conductors in a memory die (eg, implementing partial merging of cavities 310 for forming conductors) is described according to examples as disclosed herein. Figures 10 to 13 Each of may illustrate aspects of the material arrangement 300 after a different subset of fabrication operations (eg, after a third set of operations) used to form the material arrangement 300 according to the second alternative. Figures 10 to 13, view "Section BB" can be associated with a cross-section (e.g., according to Section BB) in the xz plane through the material arrangement 300 associated with a set of cavities 310 (e.g., including a plurality of cavities 310 for forming and isolating conductors). Although aspects of the second alternative for implementing merged cavities for conductor formation are illustrated in region 306, similar techniques can be implemented using cavities 310 in region 302 and other regions of the memory die to form conductors using merged cavities 310 in region 302.

[0077] Figure 10 A material arrangement 300 is illustrated in top view and cross-sectional side view (e.g., relative to section BB) after an eighth set of one or more fabrication operations (e.g., as material arrangement 300-h). The eighth set of operations may include operations that support formation of isolation regions (e.g., etching operations, wet etching operations, recessing operations).

[0078] An eighth group of operations may include operations (e.g., masking operations, photolithography operations, patterning operations) that support forming mask 1005 (e.g., masking material). Forming mask 1005 may include patterning operations to mask regions corresponding to cavities 310 to be merged to form conductors and at least some of cavities 305 and 310 (e.g., in regions 301 and 302), while exposing regions corresponding to cavities 310 for forming electrical isolation regions. For example, mask 1005 may include masking material (e.g., a hard mask) formed in a pattern over stack 340 such that the masking material covers the locations of cavities 310 in region 306 to be merged to form conductors. In some cases, different patterns may be employed for forming mask 1005. For example, the number or pattern of cavities 310 exposed to form isolation regions may vary depending on the configuration. Additionally or alternatively, the number or pattern of cavities 310 that remain masked by mask 1005 may vary depending on the configuration. Such techniques can result in different spacings between masked cavities 310 (e.g., for different amounts of electrical isolation) and different amounts of conductive material formed within the cavities 310, which are subsequently merged to form a conductor. Thus, a uniform pattern of cavities 310 can be formed to maintain processing and structural consistency across the memory die, and different sizes of cavities 310 to be merged and different spacings between cavities 310 can be formed to achieve a configured conductivity or resistivity value.

[0079] The eighth set of operations may include operations (e.g., etching operations, wet etching operations, recessing operations) that support the formation of electrically isolated regions between cavities 310 to be merged. For example, the eighth set of operations may include removing sacrificial material 351 from cavities 310 that are not merged to form conductors. The eighth set of operations may also include removing portions of material 342 to form voids 1015 (e.g., through regions 306 and between layers of material 341 in at least a portion of other regions). Voids 1015 may expose portions of sacrificial material 351 corresponding to cavities 310 that are masked by mask 1005 (e.g., sidewalls of sacrificial material 351 between layers of material 341).

[0080] Figure 11 A material arrangement 300 (e.g., as material arrangement 300-i) is illustrated in a cross-sectional side view (e.g., relative to cut plane BB) after a ninth set of one or more fabrication operations. The ninth set of operations may include further operations (e.g., one or more deposition operations, one or more oxidation operations) that support forming electrical isolation between cavities 310 to be merged for conductor formation (e.g., including isolation pillars 1110). For example, the ninth set of operations may include forming material 1105 in cavities 310 and voids 1015. For example, the ninth set of operations may include forming (e.g., depositing) material 1105 in at least some of the cavities 310 that are not merged, which may include forming material 1105 in contact with exposed portions of sacrificial material 351. Material 1105 may be the same as material 341, material 336, material 355, material 365, material 381, material 510, or any combination thereof, as well as other materials of material arrangement 300, and may be a dielectric material (e.g., an oxide, silicon oxide). Isolation posts 1110 may provide electrical isolation between conductors to be formed in merged cavity 310 and other features of material arrangement 300 .

[0081] Figure 12 The material arrangement 300 is illustrated in a cross-sectional side view (e.g., relative to cutting plane BB) after a tenth set of one or more fabrication operations (e.g., as material arrangement 300-j). The tenth set of operations can include operations (e.g., etching operations, wet etching operations, recessing operations) that support forming the merged cavity 1210 at least in part by merging multiple cavities 310 (e.g., partially merging the cavities along the z-direction).

[0082] The tenth set of operations may include merging multiple cavities 310 by removing mask 1005 and removing sacrificial material 351 from cavities 310 to be merged for conductor formation. The tenth set of operations may also include removing at least material 342 from portions of stack 340 (e.g., between layers of material 341 within region 306) to form voids 1215 between layers of material 341 (e.g., to form partial merges between cavities 310). However, in some other examples (not shown), the tenth set of operations may also include removing material 341 as well as other materials to form fully merged cavities (e.g., without intervening portions of material 341 or other materials). Merging cavities 310 to form merged cavity 1210 may form a contiguous region without material between at least two cavities 310. In some examples, forming merged cavity 1210 may include removing material to expose circuitry 320 (e.g., a conductor of circuitry 320) or a portion of material 325 (e.g., which may not involve exposing a conductor of circuitry 320 where at least a portion of material 325 in region 306 or other regions is part of a distribution layer or other electrical node).

[0083] Figure 13 Material arrangement 300 is illustrated in a cross-sectional side view (e.g., relative to cut plane BB) after an eleventh set of one or more fabrication operations (e.g., as material arrangement 300-k). The eleventh set of operations may include operations (e.g., one or more deposition operations, metal fill operations) that support forming conductor 1305, at least in part, by forming material 1310 in merged cavity 1210. For example, the third set of operations may include forming (e.g., depositing) material 1310 in merged cavity 1210 (e.g., through at least stack 340 and, in some examples, through stack 330, as applicable) and void 1215. Material 1310 may include one or more conductive materials (e.g., a metal, a metal alloy, a conductive ceramic (e.g., tungsten silicide), deposition of an electrode layer followed by bulk-fill deposition of a conductor), which may be the same as material 325 or material 505, or any combination thereof. Cavity 310 and merged cavity 1210 may extend along the z-direction, such that conductor 1305 may have an extent along the z-direction. The extent along the z-direction may at least partially overlap with the extent in the z-direction associated with pillars 307 formed in cavities 305. Forming material 1310 may include depositing material 1310 within voids 1215 where applicable (e.g., in partially merged cavities 1210).

[0084] In some examples, such techniques may include forming material 1310 in contact with or otherwise electrically coupled to material 325 (e.g., where a portion of material 325 in region 306 or other regions is part of a distribution layer or other electrical node, this may not involve forming material 1310 in contact with a conductor of circuitry 320). Additionally or alternatively, such techniques may include forming material 1310 electrically isolated from material 325, or forming material 1310 in contact with or otherwise electrically coupled to circuitry 320 (e.g., in regions where material 325 is omitted). Forming conductor 1305 in contact with or otherwise electrically coupled to circuitry 320 may electrically couple the conductor with one or more transistor structures (e.g., a transistor formed at least in part from a doped portion of substrate 315).

[0085] Conductor 1305 can support coupling between various features of memory architecture 200. For example, conductor 1305 can be implemented as part of electrical coupling between circuitry 320 and any one or more of word line 265 (e.g., a portion of material 505), source line 260, select line 245, bit line 250, or select line 235, as well as other nodes of memory architecture 200, which can support implementation of circuitry 320 for operation of memory architecture 200. This electrical coupling can involve forming one or more conductive materials (not shown) between the respective components (e.g., above or otherwise through region 303, above or below stack 340, as applicable), as well as other examples. Additionally or alternatively, conductor 1305 can be implemented to support electrical coupling of other elements of material arrangement 300.

[0086] Figure 14 The illustration shows a flow chart of a method 1400 for supporting the formation of a merged cavity for a conductor in a memory die according to examples disclosed herein. The operations of method 1400 can be performed by a manufacturing system or one or more controllers associated with the manufacturing system. In some examples, the one or more controllers can execute a set of instructions to control one or more functional elements of the manufacturing system to perform desired functions. Additionally or alternatively, the manufacturing system can use dedicated hardware to perform aspects of the described functions.

[0087] At 1405, the method may include forming a stack of material layers over a substrate of a memory die.

[0088] At 1410 , the method may include forming a plurality of cavities through the stack of material layers.

[0089] At 1415 , the method may include forming a merged cavity through the stack of material layers at least in part by merging at least two cavities of the plurality of cavities.

[0090] At 1420 , the method may include forming a conductor through the stack of material layers based at least in part on forming one or more conductive materials in the merged cavity.

[0091] In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform one or several methods, such as method 1400. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of a manufacturing system) for performing the following aspects of the present disclosure, or any combination thereof:

[0092] Aspect 1: A method or apparatus comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: forming a material layer stack above a substrate of a memory die; forming a plurality of cavities through the material layer stack; forming a merged cavity through the material layer stack at least in part by merging at least two of the plurality of cavities; and forming a conductor through the material layer stack based at least in part on forming one or more conductive materials in the merged cavity.

[0093] Aspect 2: The method or apparatus of aspect 1, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: forming a plurality of second cavities through the stack of material layers; forming a plurality of memory cells based at least in part on forming semiconductor material in the plurality of second cavities, wherein the conductor is operable to electrically couple with at least a subset of the plurality of memory cells.

[0094] Aspect 3: The method or apparatus of aspect 2, wherein the plurality of second cavities are formed concurrently with forming the plurality of cavities.

[0095] Aspect 4: The method or apparatus of any one of Aspects 2 to 3, further comprising operations, features, circuit systems, logic, components or instructions, or any combination thereof, for: forming a plurality of voids based at least in part on removing corresponding portions of a second material of the material layer stack from between a first material layer of the material layer stack; and forming a plurality of word lines electrically coupled to the plurality of memory cells based at least in part on forming one or more second conductive materials in the plurality of voids; and wherein the conductor is electrically coupled to at least one of the plurality of word lines.

[0096] Aspect 5: The method or apparatus of any one of Aspects 1 to 4, wherein forming the at least two cavities exposes a third conductive material between the material layer stack and the substrate, and forming the conductor comprises forming a conductive material of the one or more conductive materials in contact with the third conductive material.

[0097] Aspect 6: The method or apparatus of any one of aspects 1 to 5, wherein the conductor is electrically coupled to one or more transistors formed at least in part from a doped portion of the substrate.

[0098] Aspect 7: A method or apparatus according to any one of Aspects 1 to 6, wherein merging the at least two cavities includes operations, features, circuit systems, logic, components or instructions, or any combination thereof, for forming a plurality of gaps between adjacent cavities in the at least two cavities based at least in part on removing corresponding portions of the second material of the material layer stack between the first material layer of the material layer stack.

[0099] Aspect 8: A method or apparatus according to any one of Aspects 1 to 7, wherein merging the at least two cavities includes operations, features, circuit systems, logic, components or instructions, or any combination thereof, for removing corresponding portions of the first material of the material layer stack and the second material of the material layer stack between adjacent cavities in the at least two cavities.

[0100] Aspect 9: The method or apparatus of any one of aspects 1 to 8, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for forming a dielectric material in one or more of the plurality of cavities adjacent to the at least two cavities.

[0101] Aspect 10: The method or apparatus according to any one of Aspects 1 to 9, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: forming a sacrificial material in the multiple cavities; removing the sacrificial material from at least two second cavities of the multiple cavities; recessing the second material of the material layer stack through the at least two second cavities to expose the sidewalls of the second material between the first material layers of the material layer stack; forming a portion of the first material above the exposed sidewalls of the second material; removing the sacrificial material from the at least two cavities of the multiple cavities; removing the portion of the second material through the at least two cavities to expose the sidewalls of the portion of the first material; and forming a conductive material of the one or more conductive materials in contact with the exposed sidewalls of the portion of the first material.

[0102] Aspect 11: The method or apparatus of any one of Aspects 1 to 10, further comprising operations, features, circuit systems, logic, components or instructions, or any combination thereof, for: forming a sacrificial material in the plurality of cavities; removing the sacrificial material from the at least two cavities of the plurality of cavities; recessing the second material of the material layer stack through the at least two cavities to expose the sidewalls of the second material between the first material layers of the material layer stack; forming a portion of the first material above the exposed sidewalls of the second material; and forming a conductive material of the one or more conductive materials in contact with the portion of the first material.

[0103] Aspect 12: The method or apparatus of aspect 11, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: removing the sacrificial material from one or more of the plurality of cavities that are different from the at least two cavities; and forming portions of the first material in the one or more cavities.

[0104] Aspect 13: A method or apparatus according to any one of Aspects 1 to 12, wherein forming the plurality of cavities comprises operations, features, circuit systems, logic, components or instructions, or any combination thereof, for: forming a first plurality of cavities through a first subset of the stack of material layers; and forming a second plurality of cavities through a second subset of the stack of material layers, each of the second plurality of cavities coinciding with a corresponding one of the first plurality of cavities.

[0105] Aspect 14: The method or apparatus of any of aspects 1 to 13, wherein the material layer stack comprises alternating layers of oxide material and nitride material.

[0106] It should be noted that the described methods include possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more methods may be combined.

[0107] A device is described. The following provides an overview of aspects of the device as described herein:

[0108] Aspect 15: An apparatus comprising: an array region above a substrate, comprising a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being arranged in a direction away from the substrate and each positioned between a first layer of dielectric material in the array region; and a conductor operable to couple to at least one of the plurality of memory cells, the conductor being located outside the array region and comprising: a plurality of first conductor portions, each aligned in the direction away from the substrate; and at least one second conductor portion coupled to an adjacent first conductor portion of the plurality of first conductor portions, each second conductor portion being located between a second layer of dielectric material outside the array region.

[0109] Aspect 16: The apparatus of Aspect 15, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells with one or more transistors formed at least in part from a doped portion of the substrate.

[0110] Aspect 17: The apparatus of any one of aspects 15 to 16, wherein the conductor contacts a portion of at least one of the plurality of access lines outside of the array region.

[0111] Aspect 18: The apparatus of any one of aspects 15 to 17, wherein: the plurality of memory cells are associated with a first range along the direction; and the conductor is associated with a second range along the direction, the second range at least partially overlapping the first range.

[0112] Aspect 19: The apparatus of any one of aspects 15 to 18, wherein a subset of the plurality of memory cells are each arranged along a respective cell pillar extending in the direction, each cell pillar being associated with a cross-sectional area smaller than a cross-sectional area of ​​the conductor.

[0113] Aspect 20: The apparatus of any one of aspects 15 to 19, wherein the conductor comprises a first conductive material in contact with at least a portion of the dielectric material and a second conductive material in contact with the first conductive material.

[0114] A device is described. The following provides an overview of aspects of the device as described herein:

[0115] Aspect 21: An apparatus comprising: an array region above a substrate, comprising a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being arranged along a direction away from the substrate and each positioned between layers of dielectric material in the array region; a conductor operable to couple to at least one of the plurality of memory cells, the conductor being located outside the array region and associated with an axis aligned along the direction; and one or more dielectric portions surrounding at least a portion of the conductor, each of the one or more dielectric portions comprising at least one protrusion of the dielectric material toward the axis.

[0116] Aspect 22: The apparatus of aspect 21, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells with one or more transistors formed at least in part from a doped portion of the substrate.

[0117] Aspect 23: The apparatus of any of aspects 21-22, wherein the conductor contacts a portion of at least one of the plurality of access lines outside of the array region.

[0118] Aspect 24: The apparatus of any one of aspects 21 to 23, wherein: the memory cell is associated with a first range along the direction; and the conductor is associated with a second range along the direction, the second range at least partially overlapping the first range.

[0119] Aspect 25: The apparatus of any one of aspects 21 to 24, wherein a subset of the plurality of memory cells are each arranged along a respective cell pillar extending in the direction, each cell pillar being associated with a cross-sectional area smaller than a cross-sectional area of ​​the conductor.

[0120] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if any conductive path exists between the components that can readily support signal flow between the components. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or an indirect conductive path between the connected components may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0121] The term "coupled" (e.g., "electrically coupled") may refer to a condition whereby components move from an open-circuit relationship (where signals are currently unable to communicate between the components via a conductive path) to a closed-circuit relationship (where signals are able to communicate between the components via a conductive path). If a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0122] The term "isolation" refers to a relationship between components where signals are no longer able to flow between them. If an open circuit exists between the components, the components are isolated from each other. For example, if a switch located between the components is open, the two components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0123] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" may be interchangeable if they are used to describe a connection between conditional actions, conditional processes, or portions of a process.

[0124] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or any other doping means.

[0125] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices, including a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "turned on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "turned off" or "deactivated."

[0126] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not preferred or superior to other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0127] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the second reference label.

[0128] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0129] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: forming a stack of material layers over a substrate of the memory die; forming a plurality of cavities through the stack of material layers; forming a merged cavity through the stack of material layers at least in part by merging at least two cavities of the plurality of cavities; and A conductor is formed through the stack of material layers based at least in part on forming one or more conductive materials in the merged cavity.

2. The method according to claim 1, further comprising: forming a plurality of second cavities through the stack of material layers; and A plurality of memory cells are formed based at least in part on forming a semiconductor material in the plurality of second cavities, wherein the conductor is operable to electrically couple with at least a subset of the plurality of memory cells. The method of claim 2 , wherein the second plurality of cavities are formed concurrently with forming the plurality of cavities.

4. The method according to claim 2, further comprising: forming a plurality of voids based at least in part on removing respective portions of a second material of the material layer stack from between first material layers of the material layer stack; and forming a plurality of word lines electrically coupled to the plurality of memory cells based at least in part on forming one or more second conductive materials in the plurality of voids, The conductor is electrically coupled to at least one word line of the plurality of word lines.

5. The method according to claim 1, wherein: forming the at least two cavities to expose the third conductive material between the material layer stack and the substrate; and Forming the conductor includes forming a conductive material of the one or more conductive materials in contact with the third conductive material.

6. The method of claim 1, wherein the conductor is electrically coupled to one or more transistors formed at least in part from a doped portion of the substrate.

7. The method of claim 1 , wherein merging the at least two cavities comprises: A plurality of voids are formed between adjacent ones of the at least two cavities based at least in part on removing respective portions of a second material of the material layer stack between first material layers of the material layer stack.

8. The method of claim 1 , wherein merging the at least two cavities comprises: Respective portions of the first material of the material layer stack and the second material of the material layer stack between adjacent ones of the at least two cavities are removed.

9. The method according to claim 1, further comprising: forming a sacrificial material in the plurality of cavities; removing the sacrificial material from at least two second cavities of the plurality of cavities; recessing the second material of the material layer stack via the at least two second cavities to expose sidewalls of the second material between the first material layers of the material layer stack; forming a portion of the first material over the exposed sidewalls of the second material; removing the sacrificial material from the at least two cavities of the plurality of cavities; removing portions of the second material through the at least two cavities to expose sidewalls of the portions of the first material; and A conductive material of the one or more conductive materials is formed in contact with the exposed sidewalls of the portion of the first material.

10. The method of claim 1, further comprising: forming a sacrificial material in the plurality of cavities; removing the sacrificial material from the at least two cavities of the plurality of cavities; recessing a second material of the material stack via the at least two cavities to expose sidewalls of the second material between first material layers of the material layer stack; forming a portion of the first material over the exposed sidewalls of the second material; and A conductive material of the one or more conductive materials is formed in contact with the portion of the first material. The method of claim 1 , wherein the material layer stack comprises alternating layers of oxide material and nitride material.

12. A device comprising: an array region above a substrate, comprising a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being arranged in a direction away from the substrate and each positioned between a first layer of dielectric material in the array region; and a conductor operable to couple with at least one memory cell of the plurality of memory cells, the conductor being located outside the array region and comprising: a plurality of first conductor portions, each of which is aligned along the direction away from the substrate; and At least one second conductor portion is coupled to an adjacent first conductor portion of the plurality of first conductor portions, each second conductor portion being located between the second layers of dielectric material outside the array region.

13. The apparatus of claim 12, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells with one or more transistors formed at least in part from a doped portion of the substrate.

14. The apparatus of claim 12, wherein the conductor contacts a portion of at least one of the plurality of access lines outside of the array region.

15. The apparatus of claim 12, wherein: The plurality of memory cells are associated with a first range along the direction; and The conductor is associated with a second extent that at least partially overlaps the first extent along the direction.

16. The apparatus of claim 12, wherein a subset of the plurality of memory cells are each arranged along a respective cell pillar extending in the direction, each cell pillar being associated with a cross-sectional area smaller than a cross-sectional area of ​​the conductor.

17. An apparatus comprising: an array region above a substrate, comprising a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being arranged in a direction away from the substrate and each being positioned between dielectric material layers in the array region; a conductor operable to couple with at least one memory cell of the plurality of memory cells, the conductor being located outside the array region and associated with an axis aligned along the direction; and One or more dielectric portions surround at least a portion of the conductor, each of the one or more dielectric portions including at least one protrusion of the dielectric material toward the axis.

18. The apparatus of claim 17, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells with one or more transistors formed at least in part from a doped portion of the substrate.

19. The apparatus of claim 17, wherein the conductor contacts a portion of at least one of the plurality of access lines outside of the array region.

20. The apparatus of claim 17, wherein a subset of the plurality of memory cells are each arranged along a respective cell pillar extending in the direction, each cell pillar being associated with a cross-sectional area smaller than a cross-sectional area of ​​the conductor.

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