Signal monitoring apparatus, signal monitoring method, electronic device, and storage medium

Abstract

A signal monitoring apparatus, a signal monitoring method, an electronic device, and a storage medium. The signal monitoring apparatus comprises a monitoring module configured to obtain a pulse width threshold and receive a monitored signal, and perform glitch monitoring on the monitored signal based on the pulse width threshold. The monitoring module comprises an edge monitoring submodule and a glitch determination submodule. The edge monitoring submodule is configured to record a time of occurrence of each level inversion of the monitored signal, and send the time of occurrence of each level inversion to the glitch determination submodule. The glitch determination submodule is configured to determine whether a glitch is generated in the monitored signal based on a relationship between a difference between times of occurrence of two adjacent level inversions of the monitored signal and the pulse width threshold. The signal monitoring apparatus can improve the flexibility of glitch monitoring on the monitored signal, does not require an additional sampling clock, and can effectively reduce circuit cost and power consumption.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a signal monitoring device, a signal monitoring method, an electronic device, and a storage medium. Background Technology

[0002] In logic circuits, a signal glitch refers to a brief, unwanted spike or oscillation that occurs during signal changes. Glitches may be incorrectly identified as valid signals, leading to errors in the logic circuit's output. For example, in a counter circuit, a glitch on the clock signal may cause the counter to count incorrectly, disrupting the operation of the entire system. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a signal monitoring device, including: a monitoring module configured to acquire a pulse width threshold and receive a monitored signal, and to perform glitch monitoring on the monitored signal based on the pulse width threshold, wherein the monitoring module includes an edge monitoring submodule and a glitch determination submodule, the edge monitoring submodule being configured to record the occurrence time of each level reversal of the monitored signal and send the occurrence time of each level reversal to the glitch determination submodule; the glitch determination submodule being configured to determine whether the monitored signal has generated a glitch based on the relationship between the difference between the occurrence times of two adjacent level reversals of the monitored signal and the pulse width threshold.

[0004] For example, in a signal monitoring device provided in at least one embodiment of this disclosure, the glitch determination submodule performs a determination based on the relationship between the difference between the occurrence times of two adjacent level reversals of the monitored signal and the pulse width threshold to determine whether the monitored signal has generated a glitch, including: determining that the monitored signal has generated a glitch in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being less than the pulse width threshold; and determining that the monitored signal has not generated a glitch in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being greater than or equal to the pulse width threshold.

[0005] For example, in a signal monitoring device provided in at least one embodiment of this disclosure, the monitored signal includes a fault alarm signal used to report a fault or abnormality in the monitored circuit. The signal monitoring device further includes an identification module coupled to the monitoring module. The monitoring module is further configured to, in response to determining that a glitch has been generated in the fault alarm signal, send a signal segment of the fault alarm signal from the nearest edge before the glitch to the nearest edge after the glitch to the identification module. The identification module is configured to acquire configuration information of the error type and identify the error type of the signal segment based on the configuration information of the error type.

[0006] For example, in a signal monitoring device provided in at least one embodiment of this disclosure, the identification module includes a mapping submodule, a generation submodule, and a matching submodule. The mapping submodule is configured to map the signal segment to a first style in units of clock cycles, wherein the glitch in the signal segment is mapped to a first value in the first style, and multiple data in the signal segment corresponding to multiple clock cycles other than the glitch are mapped to multiple second values ​​in the first style. The generation submodule is configured to generate multiple second styles based on the configuration information of the error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value. The matching submodule is configured to determine a target style that matches the first style from the multiple second styles, and determine and output the error type of the signal segment based on the target style.

[0007] For example, in a signal monitoring device provided in at least one embodiment of this disclosure, the matching submodule performs the task of determining a target style that matches the first style from the plurality of second styles, including: determining that the first style matches the target style in response to a first number of second values ​​preceding the first value in the first style falling within a first range of the target style, and a second number of second values ​​following the first value in the first style falling within a second range of the target style.

[0008] For example, in a signal monitoring device provided in at least one embodiment of this disclosure, the number of the second pattern is equal to the square of the number of the error types.

[0009] For example, in the signal monitoring device provided in at least one embodiment of this disclosure, the error type includes at least one of cyclic redundancy check error and parity check error.

[0010] For example, at least one embodiment of the signal monitoring device provided in this disclosure further includes an alarm module coupled to the monitoring module, the alarm module being configured to alarm for spikes generated by the monitored signal.

[0011] For example, in the signal monitoring device provided in at least one embodiment of this disclosure, the monitoring module is further configured to send glitch information of the glitch to the alarm module in response to determining that the monitored signal has generated a glitch. The alarm module includes an acquisition submodule, an alarm submodule, and a feedback submodule. The acquisition submodule is configured to acquire alarm configuration information and, in response to determining that an alarm is needed based on the alarm configuration information, send the glitch information to the alarm submodule. The alarm configuration information includes at least one of whether an alarm needs to be triggered after a glitch is detected and how to trigger the alarm. The alarm submodule is configured to generate alarm information based on the glitch information and send the alarm information to the feedback submodule. The feedback submodule is configured to output the alarm information based on the alarm configuration information.

[0012] For example, at least one embodiment of the signal monitoring device provided in this disclosure further includes a glitch widening module coupled to the monitoring module. The glitch widening module is configured to widen the pulse of the glitch in response to the generation of a glitch in the monitored signal, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

[0013] For example, in the signal monitoring device provided in at least one embodiment of this disclosure, the monitoring module is further configured to, in response to determining that the monitored signal has generated a glitch, send the glitch information to the glitch widening module. The glitch widening module includes an information storage submodule and a glitch widening submodule. The information storage submodule is configured to acquire glitch widening configuration information and, in response to receiving the glitch information, send the glitch widening configuration information to the glitch widening submodule. The glitch widening submodule is configured to widen the pulse width of the glitch according to the glitch widening configuration information, so that the pulse width of the widened glitch reaches the target pulse width set in the glitch widening configuration information.

[0014] For example, in the signal monitoring device provided in at least one embodiment of this disclosure, the glitch widening submodule includes an AND gate, an OR gate, a first D flip-flop, and a second D flip-flop. The first terminal of the AND gate receives a first signal, the second terminal of the AND gate is connected to the third terminal of the OR gate, the first output terminal of the AND gate is connected to the first input terminal of the first D flip-flop, the third terminal of the OR gate receives the monitored signal, the fourth terminal of the OR gate receives a clock signal, the second output terminal of the OR gate is connected to the first clock terminal of the first D flip-flop, the third output terminal of the first D flip-flop is connected to the second input terminal of the second D flip-flop, the second clock terminal of the second D flip-flop is connected to the fourth terminal of the OR gate to receive the clock signal, and the fourth output terminal of the second D flip-flop outputs the glitch-widened monitored signal.

[0015] For example, at least one embodiment of the signal monitoring device provided in this disclosure further includes a configuration module coupled to the monitoring module, wherein the configuration module includes a configuration entry and a first configuration submodule, the configuration entry is configured to send user-provided setting information to the first configuration submodule; the first configuration submodule is configured to parse the setting information to obtain a pulse width threshold, and send the pulse width threshold to the monitoring module.

[0016] For example, in the signal monitoring device provided in at least one embodiment of this disclosure, the setting information further includes at least one of error type configuration information, alarm configuration information, and glitch widening configuration information.

[0017] At least one embodiment of this disclosure also provides a signal monitoring method, including: acquiring a pulse width threshold and receiving a monitored signal; recording the occurrence time of each level reversal of the monitored signal; and determining whether the monitored signal has generated glitches based on the relationship between the difference between the occurrence times of two adjacent level reversals of the monitored signal and the pulse width threshold.

[0018] For example, in a signal monitoring method provided in at least one embodiment of this disclosure, determining whether the monitored signal has generated glitches based on the relationship between the difference between the occurrence times of two adjacent level reversals of the monitored signal and the pulse width threshold includes: determining that the monitored signal has generated glitches in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being less than the pulse width threshold; and determining that the monitored signal has not generated glitches in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being greater than or equal to the pulse width threshold.

[0019] For example, in a signal monitoring method provided in at least one embodiment of this disclosure, the monitored signal includes a fault alarm signal, which is used to report a fault or abnormal condition in the monitored circuit. The signal monitoring method further includes: in response to determining that the fault alarm signal has generated a glitch, acquiring a signal segment in the fault alarm signal from the nearest edge before the glitch to the nearest edge after the glitch; acquiring configuration information of the error type; and identifying the error type of the signal segment based on the configuration information of the error type.

[0020] For example, in a signal monitoring method provided in at least one embodiment of this disclosure, identifying the error type of the signal segment based on the configuration information of the error type includes: mapping the signal segment to a first style in units of clock cycles, wherein the glitches in the signal segment are mapped to a first value in the first style, and multiple data points in the signal segment corresponding to multiple clock cycles other than the glitches are mapped to multiple second values ​​in the first style; generating multiple second styles based on the configuration information of the error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value; and determining a target style from the multiple second styles that matches the first style, and determining and outputting the error type of the signal segment based on the target style.

[0021] For example, in a signal monitoring method provided in at least one embodiment of this disclosure, determining a target style that matches the first style from the plurality of second styles includes: determining that the first style matches the target style in response to a first number of second values ​​preceding the first value in the first style falling within a first range of the target style, and a second number of second values ​​following the first value in the first style falling within a second range of the target style.

[0022] For example, at least one embodiment of the signal monitoring method provided in this disclosure further includes: acquiring alarm configuration information; in response to determining that the monitored signal has generated a glitch and determining that an alarm needs to be triggered according to the alarm configuration information, generating alarm information according to the glitch information, wherein the alarm configuration information includes at least one of whether an alarm needs to be triggered after a glitch is detected and how to trigger the alarm; and outputting the alarm information according to the alarm configuration information.

[0023] For example, at least one embodiment of the signal monitoring method provided in this disclosure further includes: acquiring configuration information for glitch widening; in response to determining that the monitored signal has generated a glitch, performing the widening process on the pulse width of the glitch according to the configuration information for glitch widening, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

[0024] For example, the signal monitoring method provided in at least one embodiment of this disclosure further includes: acquiring setting information provided by a user; and parsing the setting information to obtain at least one of pulse width threshold, error type configuration information, alarm configuration information, and glitch widening configuration information.

[0025] At least one embodiment of this disclosure also provides an electronic device, including: at least one memory storing computer-executable instructions non-transitory; and at least one processor configured to run the computer-executable instructions, wherein the computer-executable instructions, when run by the processor, implement the signal monitoring method described in any of the above embodiments.

[0026] At least one embodiment of this disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by at least one processor, implement the signal monitoring method described in any of the above embodiments. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1 This is a schematic diagram of a burr detection circuit.

[0029] Figure 2 A schematic diagram of a signal monitoring device provided in at least one embodiment of this disclosure;

[0030] Figure 3 A schematic diagram of another signal monitoring device provided in at least one embodiment of this disclosure;

[0031] Figure 4A A schematic diagram of yet another signal monitoring device provided for at least one embodiment of the present disclosure;

[0032] Figure 4B A schematic diagram illustrating a mapping operation provided for at least one embodiment of this disclosure;

[0033] Figure 4C This is a schematic diagram illustrating the generation of multiple second styles based on configuration information of error type, provided in at least one embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of yet another signal monitoring device provided for at least one embodiment of the present disclosure;

[0035] Figure 6A A schematic diagram of yet another signal monitoring device provided for at least one embodiment of the present disclosure;

[0036] Figure 6B This is a schematic diagram of the structure of a burr widening submodule provided in at least one embodiment of the present disclosure;

[0037] Figure 6CA schematic diagram of an enlarged burr provided for at least one embodiment of this disclosure;

[0038] Figure 7 A schematic diagram of yet another signal monitoring device provided for at least one embodiment of the present disclosure;

[0039] Figure 8 A flowchart illustrating a signal monitoring method provided in at least one embodiment of this disclosure;

[0040] Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of this disclosure; and

[0041] Figure 10 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described objects changes. It should be understood that the various steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0044] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0045] Chip circuits contain numerous combinational logic circuits. In these circuits, the input of multiple signals makes it easy for race conditions to arise when these signals change simultaneously. A race condition occurs when there is a time difference in the transmission of input signal changes from different paths to the same gate level, resulting in unwanted spikes or interference pulses in the circuit output. A hazard is a momentary error in the circuit output caused by a race condition, manifesting as a narrow pulse not present in the original design at the output, often referred to as a glitch.

[0046] When designing a complex digital circuit system, anticipating race conditions and hazards is extremely difficult, posing a threat to the circuit's proper function. As chip circuits become increasingly larger, monitoring, identifying, and handling these glitches caused by race conditions and hazards becomes increasingly important.

[0047] Figure 1 This is a schematic diagram of a burr detection circuit. Figure 1 As shown, the glitch detection circuit includes a frequency-locked loop circuit and a glitch detector. The frequency-locked loop circuit includes a counting module, an internal oscillator, and a frequency-locked loop filter. The glitch detector includes detection logic.

[0048] In the system clock signal CK SYS When detecting glitches, the internal oscillator of the frequency-locked loop circuit first generates multiple high-frequency clock signals CK with different phases. FAST The high-frequency clock signal CK generated by the internal oscillator FAST The clock period is greater than that of the system clock signal CK. SYS The clock period is shorter, so the high-frequency clock signal CK FAST It can be used for the system clock signal CK SYS Sampling is performed, therefore the high-frequency clock signal CK FAST It can also be called a sampling clock.

[0049] For example, when the system clock signal CK SYS Upon arrival, the counting module begins operation, utilizing the high-frequency clock signal CK. FAST The sampling clock, used for counting, is recorded by a counter within the counting module. The high-frequency clock signal CK is used for recording. FAST Each rising edge (or falling edge) until the system clock signal CK SYSAt the end of one pulse cycle, the counter stops counting. The value recorded in the counter is the system clock signal CK. SYS High-frequency clock signal CK within one pulse cycle FAST The number of pulses, due to the high-frequency clock signal CK FAST The frequency is known, so it can be determined based on the value recorded in the counter and the high-frequency clock signal CK. FAST The system clock signal CK is obtained by frequency calculation. SYS The system clock pulse width value is then output to the glitch detector. The detection logic in the glitch detector uses this value to monitor changes in the system clock pulse width. When the system clock pulse width is less than a set threshold, it is identified as a glitch.

[0050] The frequency-locked loop filter in the frequency-locked loop circuit can feed back the frequency information of the monitored system clock to the internal oscillator, thereby enabling the internal oscillator to adjust the output sampling clock (high-frequency clock signal CK) in a timely manner. FAST (The frequency of ).

[0051] The inventors of this disclosure discovered that, through Figure 1 The glitch detection circuit shown has the following drawbacks when detecting glitches in a signal:

[0052] (1) Glitches detected based on sampling clock are difficult to detect with very narrow pulse widths. For example, when a glitch with a very narrow pulse width is not at the sampling edge of the sampling clock, it cannot be detected.

[0053] (2) Using multiple sampling clocks to detect the monitored signal means that the sampling clocks also need to be changed when the monitored signal changes, resulting in poor compatibility.

[0054] (3) When the threshold of the glitch changes, the sampling clock also needs to be changed, which is not flexible enough;

[0055] (4) The hardware requires an oscillator, resulting in high circuit cost;

[0056] (5) Detection methods based on sampling clocks will lead to increased power consumption.

[0057] In this regard, at least one embodiment of the present disclosure provides a signal monitoring device. Figure 2 This is a schematic diagram of a signal monitoring device provided for at least one embodiment of the present disclosure.

[0058] like Figure 2 As shown, the signal monitoring device 200 includes a monitoring module 10. The monitoring module 10 is configured to acquire a pulse width threshold (not shown) and receive the monitored signal, and perform glitch monitoring on the monitored signal based on the pulse width threshold.

[0059] For example, the monitoring module 10 includes a coupled edge monitoring submodule 11 and a glitch detection submodule 12. The edge monitoring submodule 11 is configured to record the occurrence time of each level transition of the monitored signal and send the occurrence time of each level transition to the glitch detection submodule 12. The glitch detection submodule 12 is configured to determine whether a glitch has occurred in the monitored signal based on the relationship between the difference between the occurrence times of two adjacent level transitions of the monitored signal and a pulse width threshold.

[0060] For example, in embodiments of this disclosure, the monitored signal refers to the signal used to monitor whether glitches are generated. For example, the monitored signal can be a system clock signal, data signal, address signal, fault alarm signal, or other digital signals that need to be monitored. The monitored signal includes pulses, which have rising and falling edges. The rising edge corresponds to the pulse changing from a low level to a high level, and the falling edge corresponds to the pulse changing from a high level to a low level. The pulses in the monitored signal can appear periodically or randomly and non-periodically; embodiments of this disclosure do not impose such limitations.

[0061] For example, in embodiments of this disclosure, the pulse width threshold can be understood as a threshold for distinguishing the pulse width of a glitch from a normal signal, wherein the pulse width of a glitch is typically smaller than the normal pulse width of the monitored signal.

[0062] For example, in embodiments of this disclosure, the monitoring module 10 can obtain the pulse width threshold of the system's default configuration, or it can obtain the pulse width threshold from the user-provided setting information, thereby improving the flexibility of the configuration.

[0063] For example, Figure 3 Another signal monitoring device 300 provided in at least one embodiment of the present disclosure is shown. Compared with the signal monitoring device 200, the signal monitoring device 300 further includes a configuration module 20 coupled to the monitoring module 10. The configuration module 20 is used to provide a configuration entry (not shown in the figure) to the user so that the user can flexibly change the setting information according to his or her own needs.

[0064] For example, a configuration entry point is used to obtain user-provided setting information, which may include user-defined parameter values ​​and other configuration information. The configuration entry point can be implemented in hardware or software (e.g., an interactive interface for parameter setting). For instance, configuration entry points include, but are not limited to, the Joint Test Action Group (JTAG) interface or In-System Programming (ISP) interface in Field Programmable Gate Array (FPGA) development software.

[0065] like Figure 3 As shown, the configuration module 20 may include a first configuration submodule 21. The configuration entry point can send user-provided setting information to the first configuration submodule 21. The first configuration submodule 21 is configured to parse the user-provided setting information to obtain the pulse width threshold and send the pulse width threshold to the monitoring module 10. Through the configuration entry point and the first configuration submodule 21, flexible configuration of the pulse width threshold can be achieved.

[0066] For example, in embodiments of this disclosure, in addition to setting the pulse width threshold, other parameters such as the pulse amplitude of the glitch and whether the glitch is a high pulse or a low pulse can also be set. The first configuration submodule 21 can be configured to save some glitch-related parameters that are either configured by default in the system or freely set by the user, such as the pulse width threshold, the glitch pulse amplitude, and the pulse height of the glitch.

[0067] For example, the monitoring module 10 can obtain parameters related to glitches from the first configuration submodule 21 of the configuration module 20. For example, when the user does not set a pulse width threshold, the monitoring module 10 can use the pulse width threshold configured by the system default; when the user sets a pulse width threshold, the monitoring module 10 will preferentially use the pulse width threshold set by the user.

[0068] For example, the number of monitoring modules 10 can be configured to be one or multiple, and multiple monitoring modules 10 can each receive multiple different monitored signals. Correspondingly, the number of first configuration submodules 21 in the configuration module 20 can also be configured to be multiple, or the first configuration submodules 21 can store multiple pulse width thresholds corresponding to the multiple monitored signals, thereby enabling the monitoring module 10 to simultaneously detect multiple monitored signals, improving detection efficiency and compatibility with the monitored signals. For example, it can simultaneously detect glitches in both the address signal and the fault alarm signal used to monitor whether an address signal error has occurred.

[0069] For example, in embodiments of this disclosure, the edge monitoring submodule 11 can record the occurrence time of a level toggle by detecting the rising or falling edge of the monitored signal. Here, a level toggle can be understood as a pulse switching between a first level and a second level, where one of the first level and the second level is low and the other is high. For example, the edge monitoring submodule 11 can be configured to continuously detect the occurrence time of each level toggle in the monitored signal from the moment the monitored signal is received, and send the occurrence time of each level toggle to the glitch detection submodule 12. The edge monitoring submodule 11 can be implemented in hardware or software. For example, when the edge monitoring submodule 11 is implemented in hardware, it can include logic gates and flip-flops, etc. The embodiments of this disclosure do not limit the specific implementation method of the edge monitoring submodule 11.

[0070] For example, in an embodiment of this disclosure, the glitch detection submodule 12 can calculate the difference between the occurrence times of two adjacent level transitions of the monitored signal and compare it with a pulse width threshold to determine whether a glitch has occurred in the monitored signal. Here, the difference between the occurrence times of two adjacent level transitions refers to the difference between the occurrence time of the first level transition from the first level to the second level and the occurrence time of the second level transition from the second level to the first level, wherein the first level transition and the second level transition are adjacent.

[0071] For example, in one example, the occurrence times sent by the edge monitoring submodule 11 to the glitch determination submodule 12 include: the occurrence time t1 of level transition A, the occurrence time t2 of level transition B, the occurrence time t3 of level transition C, and the occurrence time t4 of level transition D, where t4 > t3 > t2 > t1. The glitch determination submodule 12 calculates the difference d1 between t2 and t1 and compares the difference d1 with the pulse width threshold to determine whether the pulse from t1 to t2 is a glitch; then it calculates the difference d2 between t4 and t3 and compares the difference d2 with the pulse width threshold to determine whether the pulse from t3 to t4 is a glitch.

[0072] For example, in an embodiment of this disclosure, the glitch determination submodule 12 can be configured to determine that the monitored signal has generated a glitch in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being less than a pulse width threshold, that is, to determine that the pulse between the two adjacent level reversals is a glitch; and to determine that the monitored signal has not generated a glitch in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being greater than or equal to a pulse width threshold, that is, to determine that the pulse between the two adjacent level reversals is a normal signal and not a glitch.

[0073] For example, if a pulse width threshold is set by the user, the glitch detection submodule 12 can compare the difference between the occurrence times of two consecutive level reversals of the monitored signal with the user-set pulse width threshold. If the user does not set a pulse width threshold, the glitch detection submodule 12 can compare the difference between the occurrence times of two consecutive level reversals of the monitored signal with the system's default pulse width threshold. The glitch detection submodule 12 can be implemented in hardware or software. For example, when the glitch detection submodule 12 is implemented in hardware, it can include a subtractor and a comparator, etc. The embodiments of this disclosure do not limit the specific implementation method of the glitch detection submodule 12.

[0074] The signal monitoring device provided in at least one embodiment of this disclosure monitors whether glitches have occurred by calculating the difference between the occurrence times of two adjacent level reversals of the monitored signal and comparing it with a pulse width threshold. It can monitor glitches of arbitrary pulse widths, flexibly switch the monitored signal, and the pulse width threshold for glitches of the monitored signal is adjustable. It does not require an additional sampling clock, which can effectively reduce circuit cost and power consumption.

[0075] For example, in embodiments of this disclosure, the monitored signal may be a fault alarm signal. A fault alarm signal is a signal used to report faults or abnormal conditions in the monitored circuit, including but not limited to the alert_n signal and the uvm_error signal. For ease of description, embodiments of this disclosure are described in detail below using the alert_n signal as an example; however, this is not intended to limit the embodiments of this disclosure.

[0076] For example, in the DDR protocol of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), two types of error checks are defined for signal transmission: Cyclic Redundancy Check (CRC) error and Parity Check (PAR) error. When either of these two error checks occurs, the alert_n signal will be pulled low, thus issuing an alarm.

[0077] For example, Cyclic Redundancy Check (CRC) is an error-correcting code. During data transmission, the sender calculates a CRC checksum based on the data to be transmitted and an agreed-upon generator polynomial, and appends it to the original data before sending it. The receiver checks the received data using the same generator polynomial. If the calculated CRC checksum does not match the received checksum, a CRC error occurs, and the alert_n signal is pulled low, indicating that an error may have occurred during data transmission.

[0078] For example, parity checking involves adding a parity bit to the data to ensure that the number of 1s in the data is either odd (odd parity) or even (even parity). Upon receiving the data, the receiver checks whether the number of 1s in the data meets the requirements according to the agreed-upon parity check method. If it does not, a parity error is generated, and the alert_n signal is pulled low, indicating that an error may have occurred during data transmission.

[0079] In the DDR protocol, the pulse width of alert_n corresponding to cyclic redundancy check errors and parity check errors can fluctuate within a certain range, but the pulse width of alert_n corresponding to the two is different.

[0080] The inventors of this disclosure have discovered that, for the alert_n signal (or other fault alarm signals with different pulse widths for different error types), the control module handling the alert_n signal can only determine whether the error is a cyclic redundancy check (CRC) error or a parity check (PCA) error based on the pulse width of alert_n. Although the control module may detect extreme system instability and trigger a reset process when a large number of errors occur consecutively (low probability), in cases such as two consecutive errors of the same type or two consecutive errors of different types, the pulse width of alert_n may merge into a single long pulse, exceeding the standard pulse width for a single error. In such cases, the control module can usually only identify it as an unknown error. When the control module identifies it as an unknown error, it will choose to ignore it or report the error.

[0081] To address this, at least one embodiment of this disclosure adds an identification module to the signal monitoring device. This module can identify whether a combination of a few consecutive errors has occurred while detecting glitches in the low-level alert_n signal, thereby improving the accuracy of error identification. For example, the alert_n signal can be sent to both the control module and the signal monitoring device. The configuration module 20 in the signal monitoring device can pre-set the allowable pulse width ranges for the alert_n signals corresponding to the two types of errors. The identification module in the signal monitoring device can then determine the combination of error types based on these allowable pulse width ranges. For example, the control module can be external to the signal monitoring device and may or may not be connected to it. Once the identification module identifies the combination of error types, it can directly report the error, or it can feed back the identified error type to the control module and report it along with the control module's information, thus facilitating the system to execute the corresponding processing strategy based on the error type.

[0082] Figure 4A This is a schematic diagram of yet another signal monitoring device provided in at least one embodiment of the present disclosure. (See diagram below.) Figure 4A As shown, the signal monitoring device 400 is relative to Figure 3 The signal monitoring device 300 shown also includes an identification module 30 coupled to the monitoring module 10, used to detect the error type of the monitored signal (e.g., a fault alarm signal). Here, the monitored signal that the identification module 30 can identify is a signal with a different pulse width corresponding to different types of errors. For example, the monitored signal can be alert_n. When a cyclic redundancy check error occurs, the pulse width of alert_n is a dozen or so cycles, and when a parity check error occurs, the pulse width of alert_n is tens or hundreds of cycles.

[0083] For example, in one embodiment of this disclosure, after determining that a glitch has occurred in the monitored signal, the monitoring module 10 can send the monitored signal to the identification module 30, which then identifies the error type of the monitored signal. For example, in another embodiment of this disclosure, the monitoring module 10 can continuously send the monitored signal to the identification module 30, thereby enabling the identification module 30 to more comprehensively and accurately identify the monitored signal. For example, in yet another embodiment of this disclosure, the monitoring module 10 can send only the signal segment containing the glitch to the identification module 30, thereby reducing the computational load on the identification module 30. This signal segment may, for example, include the signal from the nearest edge before the glitch to the nearest edge after the glitch.

[0084] For example, the identification module 30 is configured to acquire configuration information of error types and identify the error type of the signal segment based on the configuration information. Here, the error type may include at least one of cyclic redundancy check (CRC) error and parity check (PCM) error. The configuration information of the error type may include, for example, the minimum and maximum pulse widths of the alert_n signal corresponding to a CRC error, and the minimum and maximum pulse widths of the alert_n signal corresponding to a PCM error. For example, if the identified error does not belong to any of the errors set in the configuration information, it can be considered an unknown error (e.g., unknown errors can be ignored or reported).

[0085] For example, in embodiments of this disclosure, the identification module 30 can obtain configuration information of error types in the system's default configuration, or it can obtain configuration information of error types in the settings provided by the user, thereby improving the flexibility of identification.

[0086] For example, in one example of an embodiment of this disclosure, such as Figure 4AAs shown, the configuration module 20 in the signal monitoring device 400 may further include a second configuration submodule 22, which is configured to store configuration information such as the system default configuration or user-defined error types. For example, the identification module 30 is coupled to the second configuration submodule 22 of the configuration module 20, and the identification module 30 can obtain the error type configuration information from the second configuration submodule 22 of the configuration module 20.

[0087] like Figure 4A As shown, the identification module 30 may include a coupled mapping submodule 31, a generation submodule 32, and a matching submodule 33.

[0088] For example, the mapping submodule 31 is configured to map the monitored signal or signal segments within the monitored signal sequentially in clock cycles to a first pattern composed of a first value and a plurality of second values. Glitches are mapped to the first value in the first pattern, and multiple data points corresponding to multiple clock cycles, excluding glitches, are mapped to the plurality of second values ​​in the first pattern. For example, one of the first and second values ​​can be 1, and the other can be 0. For example, in a specific example of an embodiment of this disclosure, the first value is 1, and the second value is 0. The first and second values ​​can also take other values, and the embodiments of this disclosure do not limit this.

[0089] Figure 4B This is a schematic diagram illustrating a mapping operation provided for at least one embodiment of this disclosure. For example... Figure 4B As shown in (a), if the glitch in signal segment 1 of the monitored signal Sig is within the clock cycle (not falling on the clock edge) and has a high level, it is mapped to 1. Data in other clock cycles corresponding to this glitch are all at a low level within the clock cycle and are mapped to 0. Thus, the mapped form of signal segment 1 is: 00010. Alternatively, as... Figure 4B As shown in (b), the spike in signal segment 2 of the monitored signal Sig is at a high level on the rising edge of the clock, and is mapped to 1. The data level corresponding to the rising edge of other clock cycles is low, and is mapped to 0. Thus, the mapped pattern of signal segment 2 is: 010000.

[0090] For example, the generation submodule 32 is configured to generate multiple second styles based on configuration information of error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value.

[0091] Figure 4C This is a schematic diagram illustrating the generation of multiple second styles based on configuration information of error type, provided in at least one embodiment of this disclosure. For example... Figure 4C As shown, the error types include error A and error B. The configuration information for the error types includes the minimum pulse width A_min and the maximum pulse width A_max for error A, and the minimum pulse width B_min and the maximum pulse width B_max for error B. The generation submodule 32 can generate multiple second styles based on A_min, A_max, B_min and B_max, namely style 1, style 2, style 3 and style 4.

[0092] For example, the first range of style 1 is the number of second values ​​0 before the first value 1 that is greater than or equal to A_min and less than or equal to A_max, and the second range of style 1 is the number of second values ​​0 after the first value 1 that is greater than or equal to B_min and less than or equal to B_max.

[0093] For example, the first range of style 2 is the number of second values ​​0 before the first value 1 that is greater than or equal to A_min and less than or equal to A_max, and the second range of style 2 is the number of second values ​​0 after the first value 1 that is greater than or equal to A_min and less than or equal to A_max.

[0094] For example, the first range of style 3 is the number of second values ​​0 before the first value 1 that is greater than or equal to B_min and less than or equal to B_max, and the second range of style 3 is the number of second values ​​0 after the first value 1 that is greater than or equal to B_min and less than or equal to B_max.

[0095] For example, the first range of style 4 is the number of second values ​​0 before the first value 1 that is greater than or equal to B_min and less than or equal to B_max, and the second range of style 4 is the number of second values ​​0 after the first value 1 that is greater than or equal to A_min and less than or equal to A_max.

[0096] For example, error A in the above embodiments can be a cyclic redundancy check (CRC) error, with a minimum pulse width A_min of, for example, 12 cycles and a maximum pulse width A_max of, for example, 20 cycles; error B can be a parity check (PCA) error, with a minimum pulse width B_min of, for example, 96 cycles and a maximum pulse width B_max of, for example, 192 cycles. Errors A and B in the above embodiments are not limited to CRC and PCA errors. Specific error types and pulse width ranges can be configured according to the actual circuit and related protocol specifications, and the embodiments of this disclosure do not impose such limitations. For example, in at least one embodiment of this disclosure, three, four, or more error types can be set according to actual needs. The number of generated second styles can be equal to the square of the number of error types. Therefore, the generation submodule 32 can generate and store as many second styles as possible using the set error types and their configuration information.

[0097] For example, the matching submodule 33 is configured to determine a target style that matches the first style from a plurality of second styles, and to determine and output the error type of the signal segment based on the target style. For example, if a first number of second values ​​preceding a first value in the first style falls within a first range of the target style, and a second number of second values ​​following a first value in the first style falls within a second range of the target style, then the first style is determined to match the target style.

[0098] For example, in a specific example of an embodiment of this disclosure, if the signal segment of the monitored signal is mapped to a first pattern of "0000000000001000000000000000", then since the number of second values ​​of 0 before the first value 1 in the first pattern is 12 (first quantity), and the number of second values ​​of 0 after the first value 1 is 15 (second quantity), that is, the first and second quantities of 0 in the first pattern are both greater than or equal to A_min (e.g., 12 cycles) and less than A_max (e.g., 20 cycles), falling within the first and second ranges of pattern 2, it can be determined that the first pattern matches pattern 2, and the error type of the signal segment can be determined as A and A based on the error type corresponding to pattern 2. Similarly, if the target pattern of the first pattern is pattern 1, the error type of the signal segment can be determined as A and B based on the error type corresponding to pattern 1.

[0099] The technical solution provided in the above embodiments of this disclosure for generating multiple second styles and matching the first style with the target style is a specific implementation method with strong operability. In addition, the monitored signal can be counted by bits (e.g., the number of clock cycles of low level duration) and compared and matched with the error type configuration information to determine the error type of the monitored signal.

[0100] It should be noted that if the first quantity of the second value before the first value in the first style (or the second quantity of the second value after the first value) is not in the first range (or second range) of any second style, then the error type corresponding to that part of the signal segment can be determined to be an unknown error.

[0101] For example, in a specific example of an embodiment of this disclosure, if the signal segment of the monitored signal is mapped to a first pattern of "00000000001000000000000000", then since the number of second values ​​0 before the first value 1 in the first pattern is 10 (first quantity) and the number of second values ​​0 after the first value 1 is 15 (second quantity), that is, the first quantity of 0 in the first pattern is not within the first range of any second pattern, but the second quantity of 0 in the first pattern is greater than A_min (e.g., 12 cycles) and less than A_max (e.g., 20 cycles), falling within the pulse width allowable range of error type A, it can be determined that the error type of the part before 1 corresponding to the glitch in the signal segment is an unknown error, and the error type of the part after 1 corresponding to the glitch in the signal segment is A.

[0102] The signal monitoring device including the identification module 30 provided in at least one embodiment of this disclosure can infer the error type of the fault alarm signal based on the level form before and after the spike in the fault alarm signal, thereby facilitating targeted correction of the error in the future.

[0103] Figure 5 This is a schematic diagram of yet another signal monitoring device provided in at least one embodiment of the present disclosure. (See diagram below.) Figure 5 As shown, the signal monitoring device 500 is relative to Figure 3 The signal monitoring device 300 shown also includes an alarm module 40 coupled to the monitoring module 10, configured to alarm for glitches generated in the monitored signal. Through this alarm module 40, relevant information about the glitches can be promptly fed back after a glitch is generated in the monitored signal.

[0104] For example, in embodiments of this disclosure, the monitoring module 10 is further configured to send glitch information to the alarm module 40 in response to determining that a glitch has occurred in the monitored signal. For example, the glitch information may include the time of occurrence of the glitch, the pulse amplitude, the pulse width, etc.

[0105] like Figure 5 As shown, the alarm module 40 may include a coupled acquisition submodule 41, an alarm submodule 42, and a feedback submodule 43.

[0106] For example, the acquisition submodule 41 is configured to acquire alarm configuration information, and in response to determining that an alarm is needed based on the alarm configuration information, to send glitch information to the alarm submodule 42. The alarm submodule 42 is configured to generate alarm information based on the glitch information and send the alarm information to the feedback submodule 43, which is configured to output alarm information based on the alarm configuration information.

[0107] For example, alarm configuration information can include at least one of whether an alarm should be triggered upon detecting a glitch and how the alarm should be triggered. For instance, it can be configured to trigger an alarm for glitches whose pulse amplitude exceeds a threshold; or it can be configured to use which pin to provide alarm feedback, for example, it can be set to use alert_n or uvm_error to provide alarm feedback; it can also be configured to include what information in the output alarm message, such as the time of occurrence of the glitch, its duration, the pulse amplitude, and on which signal the glitch occurs.

[0108] For example, the alarm module 40 can obtain the configuration information of the alarm in the system's default configuration, or it can obtain the configuration information of the alarm in the settings provided by the user, thereby improving the flexibility of the alarm.

[0109] For example, in one example of an embodiment of this disclosure, such as Figure 5 As shown, in addition to the first configuration submodule 21, the configuration module 20 in the signal monitoring device 500 may also include a third configuration submodule 23. The third configuration submodule 23 is configured to store the system default configuration or user-defined alarm configuration information. For example, the alarm module 40 is coupled to the third configuration submodule 23 of the configuration module 20, and the alarm module 40 can obtain the alarm configuration information from the third configuration submodule 23 of the configuration module 20.

[0110] For example, the alarm module 40 can be implemented in hardware or software. For example, it can output alarm information through an alarm signal or provide feedback through an operation register. The embodiments disclosed herein do not limit this.

[0111] Figure 6A This is a schematic diagram of yet another signal monitoring device provided in at least one embodiment of the present disclosure. (See diagram below.) Figure 6A As shown, Figure 6A As shown, the signal monitoring device 600 is relative to Figure 3 The signal monitoring device 300 shown also includes a glitch widening module 50 coupled to the monitoring module 10. This module is configured to widen the pulse of a glitch generated by the monitored signal, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device. Through the widening process of the glitch widening module 50, the pulse of a narrow or otherwise undetectable glitch can be widened, making it easier for the system to detect the glitch.

[0112] For example, in embodiments of this disclosure, the monitoring module 10 is further configured to send glitch information to the glitch widening module 50 in response to determining that a glitch has occurred in the monitored signal. For example, the glitch information may include the glitch occurrence time, pulse amplitude, pulse width, etc.

[0113] like Figure 6AAs shown, the burr widening module 50 may include a coupled information storage submodule 51 and a burr widening submodule 52.

[0114] For example, the information storage submodule 51 is configured to acquire glitch widening configuration information and, in response to receiving glitch information, send the glitch widening configuration information to the glitch widening submodule 52. The glitch widening submodule 52 is configured to widen the pulse width of the glitch according to the glitch widening configuration information, so that the pulse width of the widened glitch reaches the target pulse width set in the glitch widening configuration information.

[0115] For example, the configuration information for glitch widening can include the pulse width after glitch widening (target pulse width), which can be equal to the clock period or other values ​​set according to actual needs (e.g., values ​​greater than the clock period). The configuration information can also include whether to widen the glitch. For instance, if the glitch pulse width is already wide enough to be detected by the sampling edge of the clock signal, then widening the glitch is not necessary; otherwise, widening is required.

[0116] For example, the burr widening module 50 can obtain the burr widening configuration information of the system's default configuration, or it can obtain the burr widening configuration information of the user-provided settings, thereby improving the flexibility of burr widening.

[0117] For example, in one example of an embodiment of this disclosure, such as Figure 6A As shown, in addition to the first configuration submodule 21, the configuration module 20 in the signal monitoring device 600 may also include a fourth configuration submodule 24. The fourth configuration submodule 24 is configured to store configuration information such as the system default configuration or user-defined glitch widening. For example, the glitch widening module 50 is coupled to the fourth configuration submodule 24 of the configuration module 20, and the glitch widening module 50 can obtain the glitch widening configuration information from the fourth configuration submodule 24 of the configuration module 20.

[0118] Figure 6B This is a schematic diagram of the structure of a burr widening submodule 52 provided for at least one embodiment of the present disclosure. Figure 6B As shown, the glitch widening submodule 52 includes an AND gate 521, an OR gate 522, a first D flip-flop 523, and a second D flip-flop 524.

[0119] For example, the first terminal of AND gate 521 receives a first signal, the second terminal of AND gate 521 is connected to the third terminal of OR gate 522 and receives the monitored signal sig, the first output terminal of AND gate 521 is connected to the first input terminal (D terminal) of the first D flip-flop 523, the third terminal of OR gate 522 receives the monitored signal sig, the fourth terminal of OR gate 522 receives the clock signal clk (e.g., the system clock), the second output terminal of OR gate 522 is connected to the first clock terminal of the first D flip-flop 523, the third output terminal (Q terminal) of the first D flip-flop 523 is connected to the second input terminal (D terminal) of the second D flip-flop 524, the second clock terminal of the second D flip-flop 524 is connected to the fourth terminal of OR gate 522 to receive the clock signal clk, and the fourth output terminal (Q terminal) of the second D flip-flop 524 outputs the glitch-widened monitored signal sig_out. Since glitch monitoring is based on edge detection, the glitch widening submodule 52 can widen glitch signals of arbitrary pulse widths.

[0120] Figure 6C This is a schematic diagram of an enlarged burr provided for at least one embodiment of this disclosure. For example... Figure 6B and Figure 6C As shown, the first signal is a continuous high-level signal (e.g., logic state 1). If there is a glitch in the monitored signal sig (e.g., manifested as a high-level pulse), the first D flip-flop 523 (on the rising edge of the clock) feeds it back to the intermediate signal m_sig, where m_sig equals 1. If there is no glitch, m_sig equals 0. Then, if the rising edge of the clock of the second D flip-flop 524 arrives, the value of m_sig is assigned to the Q input of the second D flip-flop 524, thereby widening the pulse width of the glitch. The output signal sig_out after widening the glitch is as follows: Figure 6C As shown. The pulse width of the glitches in the widened signal sig_out is wide enough to be detected by the sampling edge (e.g., rising or falling edge) of the clock signal of other circuits, facilitating subsequent glitches processing, such as filtering. For example, Figure 6B and Figure 6C The clock signal clk in the system is the same as the clock signals of other circuits, for example, they are all the system clock.

[0121] Figure 7 This is a schematic diagram of yet another signal monitoring device provided in at least one embodiment of the present disclosure. (See diagram below.) Figure 7 As shown, the signal monitoring device 700 includes a monitoring module 10, a configuration module 20, an identification module 30, an alarm module 40, and a burr widening module 50.

[0122] The structure and detailed description of the monitoring module 10, the identification module 30, the alarm module 40 and the burr widening module 50 can be found in the relevant descriptions in the above embodiments, and will not be repeated here.

[0123] For example, configuration module 20 includes a first configuration submodule 21, a second configuration submodule 22, a third configuration submodule 23, and a fourth configuration submodule 24. The first configuration submodule 21 is connected to the monitoring module 10, the second configuration submodule 22 is connected to the identification module 30, the third configuration submodule 23 is connected to the alarm module 40, and the fourth configuration submodule 24 is connected to the burr widening module 50. Detailed descriptions of the first configuration submodule 21, the second configuration submodule 22, the third configuration submodule 23, and the fourth configuration submodule 24 can be found in the relevant descriptions in the above embodiments, and will not be repeated here.

[0124] Users can set the pulse width threshold, error type configuration information, alarm configuration information, and spur widening configuration information according to their needs, and save them in the first configuration submodule 21, the second configuration submodule 22, the third configuration submodule 23, and the fourth configuration submodule 24 respectively. When the monitoring module 10, the identification module 30, the alarm module 40, and the spur widening module 50 need to use this information, they can directly obtain it from the configuration module 20, thereby improving the working efficiency of each module.

[0125] It should be noted that, in the embodiments of this disclosure, the signal monitoring device may include more or fewer circuits or modules, and the connection relationship between the various circuits or modules is not limited and can be determined according to actual needs. The specific configuration of each circuit or module is not limited; it can be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0126] Figure 8 A flowchart illustrating a signal monitoring method provided in at least one embodiment of this disclosure, such as... Figure 8 As shown, the signal monitoring method includes the following steps S810~S830.

[0127] S810: Acquires pulse width threshold and receives monitored signal.

[0128] S820: Records the time of each level transition of the monitored signal.

[0129] S830: Based on the relationship between the difference between the occurrence times of two consecutive level reversals of the monitored signal and the pulse width threshold, determine whether the monitored signal has generated glitches.

[0130] For example, in the signal monitoring method provided in at least one embodiment of this disclosure, step S830, which determines whether the monitored signal has generated glitches based on the relationship between the difference between the occurrence times of two adjacent level reversals of the monitored signal and the pulse width threshold, may include: determining that the monitored signal has generated glitches in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being less than the pulse width threshold; and determining that the monitored signal has not generated glitches in response to the difference between the occurrence times of two adjacent level reversals of the monitored signal being greater than or equal to the pulse width threshold.

[0131] For example, in the signal monitoring method provided in at least one embodiment of this disclosure, the monitored signal includes a fault alarm signal, which is used to report faults or abnormalities in the monitored circuit.

[0132] For example, at least one embodiment of the signal monitoring method provided in this disclosure further includes: in response to determining that a glitch has been generated in the fault alarm signal, acquiring a signal segment in the fault alarm signal from the nearest edge before the glitch to the nearest edge after the glitch; acquiring configuration information of the error type; and identifying the error type of the signal segment based on the configuration information of the error type.

[0133] For example, in the signal monitoring method provided in at least one embodiment of this disclosure, identifying the error type of a signal segment based on configuration information of the error type may include: mapping the signal segment to a first style in units of clock cycles, wherein glitches in the signal segment are mapped to a first value in the first style, and multiple data in the signal segment other than glitches corresponding to multiple clock cycles are mapped to multiple second values ​​in the first style; generating multiple second styles based on the configuration information of the error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value; and determining a target style that matches the first style from the multiple second styles, and determining and outputting the error type of the signal segment based on the target style.

[0134] For example, in the signal monitoring method provided in at least one embodiment of this disclosure, a target pattern that matches the first pattern is determined from a plurality of second patterns. A specific example may include: in response to a first number of second values ​​preceding a first value in the first pattern falling within a first range of the target pattern, and a second number of second values ​​following a first value in the first pattern falling within a second range of the target pattern, the first pattern is determined to match the target pattern.

[0135] For example, the signal monitoring method provided in at least one embodiment of this disclosure further includes: acquiring alarm configuration information; in response to determining that a glitch has been generated in the monitored signal and determining that an alarm needs to be triggered according to the alarm configuration information, generating alarm information according to the glitch information, wherein the alarm configuration information includes at least one of whether an alarm needs to be triggered after a glitch is detected and how to trigger the alarm; and outputting alarm information according to the alarm configuration information.

[0136] For example, the signal monitoring method provided in at least one embodiment of this disclosure further includes: acquiring configuration information for glitch widening; in response to determining that a glitch has been generated in the monitored signal, widening the pulse width of the glitch according to the configuration information for glitch widening, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

[0137] For example, the signal monitoring method provided in at least one embodiment of this disclosure further includes: acquiring setting information provided by the user; parsing the setting information to obtain at least one of pulse width threshold, error type configuration information, alarm configuration information, and glitch widening configuration information.

[0138] The signal monitoring method provided in at least one embodiment of this disclosure monitors whether glitches have occurred by calculating the difference between the occurrence times of two adjacent level reversals of the monitored signal and comparing it with a pulse width threshold. It can monitor glitches of arbitrary pulse widths and can switch or monitor multiple monitored signals. It also increases the flexibility of glitch monitoring and post-processing, and makes parameters such as the pulse width threshold of the monitored signal, error type configuration information, alarm configuration information, and glitch widening configuration information adjustable.

[0139] At least one embodiment of this disclosure also provides an electronic device, including a memory and a processor. The memory stores computer-executable instructions non-transitoryly, and the processor is configured to execute the computer-executable instructions. The computer-executable instructions, when executed by the processor, implement the signal monitoring method as described in any of the above embodiments. The technical effects of this electronic device are the same as those of the above-described signal monitoring method, and will not be repeated here.

[0140] At least one embodiment of this disclosure also provides a non-transitory computer-readable storage medium. Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of this disclosure. For example, such as Figure 9 As shown, one or more computer-executable instructions 901 can be stored non-transitorily on the storage medium 900. For example, when the computer-executable instructions 901 are executed by the processor, one or more steps in the signal monitoring method described above can be performed. The technical effects of this non-transitory storage medium are the same as those of the signal monitoring method described above, and will not be repeated here.

[0141] For example, the aforementioned non-transiently readable storage medium is implemented as a memory, such as volatile memory and / or non-volatile memory. In the above embodiments, the memory can be volatile memory, such as random access memory (RAM) and / or cache. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. The memory can also store various applications (code, instructions) and data, as well as various data used and / or generated by the applications.

[0142] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods disclosed herein.

[0143] Computer program code for performing the methods of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0144] Some embodiments of this disclosure also provide an electronic device that includes the signal monitoring device of any of the above embodiments or can perform the signal monitoring method of any of the above embodiments.

[0145] Figure 10 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 10 The illustrated electronic device 1000 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0146] For example, such as Figure 10 As shown, in some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which may include the signal monitoring device of any of the above embodiments, capable of performing various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. RAM 1003 also stores various programs and data required for the operation of the computer system. Processing device 1001, ROM 1002, and RAM 1003 are connected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0147] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable storage media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 10 An electronic device 1000 including various devices is shown, but it should be understood that it is not required to implement or include all of the devices shown, and more or fewer devices may be implemented or included alternatively.

[0148] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0149] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, or navigator, or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0150] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0151] In addition to the exemplary content described above, the following points should be noted regarding this disclosure:

[0152] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0153] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0154] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0155] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A signal monitoring device, comprising: The monitoring module is configured to acquire a pulse width threshold and receive a monitored signal, and to perform glitches on the monitored signal based on the pulse width threshold. The monitoring module includes an edge monitoring submodule and a burr detection submodule. The edge monitoring submodule is configured to record the occurrence time of each level reversal of the monitored signal and send the occurrence time of each level reversal to the glitch determination submodule. The glitch detection submodule is configured to determine whether the monitored signal has generated a glitch based on the relationship between the difference between the occurrence times of two consecutive level reversals of the monitored signal and the pulse width threshold. The monitored signal includes a fault alarm signal, which is used to report faults or abnormalities in the monitored circuit. The signal monitoring device further includes an identification module coupled to the monitoring module. The monitoring module is also configured to, in response to determining that a glitch has been generated in the fault alarm signal, send a signal segment of the fault alarm signal from the nearest edge before the glitch to the nearest edge after the glitch to the identification module. The identification module is configured to acquire configuration information of error types and identify the error type of the signal segment based on the configuration information of error types. The identification module includes a mapping submodule, a generation submodule, and a matching submodule. The mapping submodule is configured to map the signal segment to a first pattern in clock cycle units, wherein the glitch in the signal segment is mapped to a first value in the first pattern, and multiple data points in the signal segment corresponding to multiple clock cycles, excluding the glitch, are mapped to multiple second values ​​in the first pattern. The generation submodule is configured to generate multiple second styles based on the configuration information of the error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value. The matching submodule is configured to determine a target pattern from the plurality of second patterns that matches the first pattern, and to determine and output the error type of the signal segment based on the target pattern. The matching submodule performs the task of determining a target style that matches the first style from the plurality of second styles, including: In response to a first number of second values ​​preceding the first value in the first style falling within a first range of the target style, and a second number of second values ​​following the first value in the first style falling within a second range of the target style, it is determined that the first style matches the target style.

2. The signal monitoring device according to claim 1, wherein, The glitch detection submodule determines whether the monitored signal has generated a glitch based on the relationship between the difference between the occurrence times of two consecutive level reversals of the monitored signal and the pulse width threshold, including: If the difference between the occurrence times of two consecutive level reversals of the monitored signal is less than the pulse width threshold, it is determined that the monitored signal has generated a glitch. If the difference between the occurrence times of two consecutive level reversals of the monitored signal is greater than or equal to the pulse width threshold, it is determined that the monitored signal has not generated glitches.

3. The signal monitoring device according to claim 1, wherein, The number of the second style is equal to the square of the number of the error types.

4. The signal monitoring device according to claim 1, wherein, The error types include at least one of cyclic redundancy check error and parity check error.

5. The signal monitoring device according to any one of claims 1-4 further includes an alarm module coupled to the monitoring module, the alarm module being configured to alarm for spikes generated by the monitored signal.

6. The signal monitoring device according to claim 5, wherein, The monitoring module is also configured to send glitch information to the alarm module in response to determining that a glitch has occurred in the monitored signal. The alarm module includes an acquisition submodule, an alarm submodule, and a feedback submodule. The acquisition submodule is configured to acquire alarm configuration information, and in response to determining that an alarm is needed based on the alarm configuration information, send the glitch information to the alarm submodule. The alarm configuration information includes at least one of whether an alarm needs to be triggered after a glitch is detected and how to trigger the alarm. The alarm submodule is configured to generate alarm information based on the glitch information and send the alarm information to the feedback submodule. The feedback submodule is configured to output the alarm information based on the alarm configuration information.

7. The signal monitoring device according to any one of claims 1-4 further includes a glitch widening module coupled to the monitoring module, the glitch widening module being configured to widen the pulse of the glitch in response to the generation of a glitch in the monitored signal, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

8. The signal monitoring device according to claim 7, wherein, The monitoring module is also configured to send glitch information to the glitch widening module in response to determining that a glitch has been generated in the monitored signal. The burr widening module includes an information storage submodule and a burr widening submodule. The information storage submodule is configured to acquire configuration information for glitch widening, and in response to receiving the glitch information, send the configuration information for glitch widening to the glitch widening submodule. The burr widening submodule is configured to perform the widening process on the pulse width of the burr according to the burr widening configuration information, so that the pulse width of the widened burr reaches the target pulse width set in the burr widening configuration information.

9. The signal monitoring device according to claim 8, wherein, The glitch widening submodule includes AND gates, OR gates, a first D flip-flop, and a second D flip-flop. The first terminal of the AND gate receives a first signal, the second terminal of the AND gate is connected to the third terminal of the OR gate, and the first output terminal of the AND gate is connected to the first input terminal of the first D flip-flop. The third terminal of the OR gate receives the monitored signal, the fourth terminal of the OR gate receives a clock signal, and the second output terminal of the OR gate is connected to the first clock terminal of the first D flip-flop. The third output terminal of the first D flip-flop is connected to the second input terminal of the second D flip-flop, the second clock terminal of the second D flip-flop is connected to the fourth terminal of the OR gate to receive the clock signal, and the fourth output terminal of the second D flip-flop outputs the monitored signal after glitches are widened.

10. The signal monitoring device according to any one of claims 1-4, further comprising a configuration module coupled to the monitoring module, wherein, The configuration module includes a configuration entry point and a first configuration sub-module. The configuration entry is configured to send user-provided settings information to the first configuration submodule; The first configuration submodule is configured to parse the setting information to obtain a pulse width threshold and send the pulse width threshold to the monitoring module.

11. The signal monitoring device according to claim 10, wherein, The configuration information also includes at least one of the following: error type configuration information, alarm configuration information, and glitch widening configuration information.

12. A signal monitoring method, comprising: Obtain the pulse width threshold and receive the monitored signal; Record the time of each level reversal of the monitored signal; as well as Based on the relationship between the difference in the occurrence time of two consecutive level reversals of the monitored signal and the pulse width threshold, it is determined whether the monitored signal has generated glitches. The monitored signal includes a fault alarm signal, which is used to report faults or abnormalities in the monitored circuit. The signal monitoring method further includes: In response to determining that a glitch has been generated in the fault alarm signal, a signal segment in the fault alarm signal from the nearest edge before the glitch to the nearest edge after the glitch is acquired. Retrieve configuration information for error types; and The error type of the signal segment is identified based on the configuration information of the error type. The step of identifying the error type of the signal segment based on the configuration information of the error type includes: The signal segment is mapped to a first pattern in units of clock cycles, wherein the glitch in the signal segment is mapped to a first value in the first pattern, and multiple data in the signal segment other than the glitch corresponding to multiple clock cycles are mapped to multiple second values ​​in the first pattern. Multiple second styles are generated based on the configuration information of the error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value; and From the plurality of second styles, a target style that matches the first style is determined, and based on the target style, the error type of the signal segment is determined and output. The step of determining the target style that matches the first style from the plurality of second styles includes: In response to a first number of second values ​​preceding the first value in the first style falling within a first range of the target style, and a second number of second values ​​following the first value in the first style falling within a second range of the target style, it is determined that the first style matches the target style.

13. The signal monitoring method according to claim 12, wherein, The method of determining whether the monitored signal has generated glitches based on the relationship between the difference in the occurrence times of two adjacent level reversals of the monitored signal and the pulse width threshold includes: If the difference between the occurrence times of two consecutive level reversals of the monitored signal is less than the pulse width threshold, it is determined that the monitored signal has generated a glitch. If the difference between the occurrence times of two consecutive level reversals of the monitored signal is greater than or equal to the pulse width threshold, it is determined that the monitored signal has not generated glitches.

14. The signal monitoring method according to claim 12 or 13, further comprising: Obtain alarm configuration information; In response to determining that a glitch has occurred in the monitored signal and determining that an alarm is needed based on the alarm configuration information, an alarm message is generated based on the glitch information. The alarm configuration information includes at least one of whether an alarm needs to be triggered upon detecting a glitch and how the alarm should be triggered; and The alarm information is output according to the alarm configuration information.

15. The signal monitoring method according to claim 12 or 13, further comprising: Obtain the configuration information for burr widening; In response to determining that a glitch has been generated in the monitored signal, the pulse width of the glitch is widened according to the glitch widening configuration information so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

16. The signal monitoring method according to claim 12 or 13, further comprising: Obtain user-provided settings information; The configuration information is parsed to obtain at least one of the following: pulse width threshold, error type configuration information, alarm configuration information, and glitch widening configuration information.

17. An electronic device comprising: At least one memory stores computer-executable instructions non-transiently; At least one processor, configured to run the computer-executable instructions, The computer-executable instructions are executed by the processor to implement the signal monitoring method according to any one of claims 12-16.

18. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by at least one processor, they implement the signal monitoring method according to any one of claims 12-16.

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