Layout processing method, lithography method, apparatus, and storage medium

Abstract

Embodiments of this disclosure relate to layout processing methods, photolithography methods, apparatus, and storage media. The layout processing method proposed herein includes: acquiring a target layout; and dividing the target layout to obtain corresponding mask layouts for multiple masks, wherein the mask layout of a first mask among the multiple masks includes a first pattern in the target layout corresponding to the first mask and adjacent patterns of the first pattern in the target layout.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein generally relate to the field of semiconductor technology, and more specifically, to a layout processing method, a photolithography method, an apparatus, and a storage medium. Background Technology

[0002] Photolithography is a crucial process in semiconductor manufacturing used to transfer circuit patterns onto a target object (such as a chip). In some applications, the chip size may exceed the maximum area that a photolithography machine can expose in a single exposure. In such cases, multiple masks can be used for multiple exposures, stitching the entire pattern together piece by piece. This photolithography process is also known as stitching lithography. However, in stitching lithography, exposure defects are prone to occur at the joints between adjacent masks, thus affecting device performance and overall yield. Summary of the Invention

[0003] In a first aspect of this disclosure, a layout processing method is provided. The method includes: acquiring a target layout; and dividing the target layout to obtain corresponding mask layouts for multiple masks, wherein the mask layout of a first mask among the multiple masks includes a first pattern in the target layout corresponding to the first mask and adjacent patterns of the first pattern in the target layout.

[0004] In a second aspect of this disclosure, a photolithography method is provided. The method includes: transferring a target pattern to a designated object using photolithography based on a plurality of masks; and wherein the plurality of masks are fabricated based on corresponding mask patterns of the plurality of masks, the corresponding mask patterns of the plurality of masks being determined by dividing the target pattern to obtain corresponding mask patterns of the plurality of masks, wherein the mask pattern of a second mask among the plurality of masks includes a third pattern in the target pattern corresponding to the second mask and adjacent patterns of the third pattern in the target pattern.

[0005] In a third aspect of this disclosure, an electronic device is provided. The device includes at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor. When executed by the at least one processor, the instructions cause the device to perform the methods of the first or second aspect.

[0006] In a fourth aspect of this disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores computer-executable instructions that can be executed by a processor to implement the methods of the first or second aspect.

[0007] In a fifth aspect of this disclosure, a computer program product is provided. The computer program product includes computer-executable instructions that, when executed by a processor, implement the method according to a first or second aspect of this disclosure.

[0008] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0009] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0010] Figure 1 A schematic diagram illustrating an example of exposure defects at the junction of adjacent masks is shown;

[0011] Figure 2 A schematic diagram of an example environment in which embodiments of the present disclosure can be implemented is shown;

[0012] Figure 3 A flowchart illustrating an example process of layout processing according to some embodiments of the present disclosure is shown;

[0013] Figure 4 A schematic diagram illustrating an example of a target layout according to some embodiments of the present disclosure;

[0014] Figure 5A A schematic diagram illustrating an example of determining a mask layout according to some embodiments of the present disclosure is shown;

[0015] Figure 5B A schematic diagram illustrating another example of determining a mask layout according to some embodiments of the present disclosure is shown;

[0016] Figure 6A A schematic diagram illustrating an example of a predetermined extraction range according to some embodiments of the present disclosure is shown;

[0017] Figure 6B A schematic diagram illustrating an example of a reference pattern according to some embodiments of the present disclosure;

[0018] Figure 7 A flowchart of a photolithography process according to some embodiments of the present disclosure is shown;

[0019] Figure 8 A schematic diagram illustrating examples of multiple masks according to some embodiments of the present disclosure is shown;

[0020] Figure 9 A schematic diagram illustrating an example of a photolithography process according to some embodiments of the present disclosure; and

[0021] Figure 10A block diagram of an electronic device in which one or more embodiments of the present disclosure may be implemented is shown. Detailed Implementation

[0022] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0023] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0024] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0025] As briefly described above, pattern transfer for large-size chips can currently be achieved using splicing photolithography. However, exposure defects are prone to occur at the splicing points of adjacent masks, thus affecting device performance and overall yield.

[0026] For example, Figure 1 A schematic diagram of an example 100 of an exposure defect at the junction of adjacent masks is shown. (Refer to...) Figure 1 During the photolithography process, the chip can be divided into multiple regions, such as a first region and a second region. A first mask 101 (corresponding to the first region) has a first pattern 1011, and a second mask 102 (corresponding to the second region, which is adjacent to the first region) has a second pattern 1021. Based on the first mask 101 and the second mask 102, the first pattern 1011 can be transferred to a corresponding position in the first region, and the second pattern 1021 can be transferred to a corresponding position in the second region, using photolithography processes such as multiple exposures. In the first and second regions, the first pattern 1011 and the second pattern 1021 will be stitched together to form a single, integrated pattern.

[0027] However, in practical applications, since the first splicing portion 1012 in the first pattern 1011 and the second splicing portion 1022 in the second pattern 1021 are located on the edges of the first mask 101 and the second mask 102, respectively, these two splicing portions may be distorted after being transferred to the first and second regions. For example, the first splicing portion 1012 and the second splicing portion 1022, which were originally right-angled rectangles, may appear as rounded rectangles after being transferred to the first and second regions. This geometric deformation will reduce the effective contact area of ​​the corresponding devices (such as transistors or wires formed based on the pattern), thereby affecting the electrical performance.

[0028] It should be noted that image distortion is only one example among many exposure defects at mask stitching. In practical applications, other anomalies may exist at mask stitching. For example, if image 1013 is too close to the edge of the first mask 101, it may cause problems such as unclear image edges after transfer.

[0029] In view of this, embodiments of the present disclosure provide a layout processing scheme to improve the above-mentioned problems. According to the scheme, a target layout is obtained. The target layout is divided to obtain corresponding mask layouts for multiple masks. The mask layout of the first mask among the multiple masks includes: a first pattern in the target layout corresponding to the first mask and adjacent patterns of the first pattern in the target layout.

[0030] As will be more clearly understood from the following description, according to the embodiments of this disclosure, when generating a mask layout for each mask (e.g., a first mask) from a target layout, in addition to giving the mask layout a main pattern (e.g., a first pattern), adjacent patterns of the main pattern are also introduced into the mask layout. These adjacent patterns can be added as auxiliary structures to the positions where the main pattern is stitched with other patterns. This process is equivalent to adding an auxiliary pattern at the stitching position. When performing photolithography using a mask fabricated based on this mask layout, the auxiliary pattern can regulate the light intensity distribution at the corresponding stitching position, thereby inducing the required optical proximity effect to compensate for exposure defects at that stitching position. In this way, the solutions of the embodiments of this disclosure can optimize the photolithography quality of stitched photolithography. This helps improve the electrical performance of the corresponding device, thereby improving the overall manufacturing yield.

[0031] Below, we will first describe various example implementations of the present disclosure for processing the target layout with reference to the accompanying drawings. Figure 2 A schematic diagram of an example environment 200 in which embodiments of the present disclosure can be implemented is shown. (Refer to...) Figure 2Example environment 200 includes electronic device 210, target chip 220, target layout 230, and mask layout 240. It should be understood that the structure and function of the various elements in environment 200 are described herein for illustrative purposes only and do not imply any limitation on the scope of this disclosure.

[0032] Electronic device 210 can obtain the target layout 230 of target chip 220 through a specific interface or protocol. The target layout 230 is a detailed graphical representation describing the internal layout and interconnections of target chip 220. It contains numerous components (such as transistors, resistors, capacitors, etc.) and circuits, presented in complex geometries and connections. Electronic device 210 establishes a communication mechanism with a client device (not shown in the figure). The client can be a computer, server, or any other device capable of sending and receiving data. Interaction between electronic device 210 and the client can be conducted via a network, ensuring accurate data transmission through standard communication protocols. The client can send various instructions and requests to electronic device 210. These instructions and requests can be sent in the form of data packets, containing necessary parameters and information so that electronic device 210 can accurately understand and execute them.

[0033] Upon receiving a layout processing request from a client, electronic device 210 can divide the target layout 230 to generate corresponding mask layouts for multiple masks. For example, electronic device 210 can divide the overall pattern in the target layout 230 based on the mask size and a predetermined pattern segmentation strategy to obtain a mask layout 240 for each mask. During the segmentation process, for each mask, electronic device 210 can incorporate the pattern corresponding to that mask in the target layout and its adjacent patterns into the mask layout of that mask. Next, based on the mask layout 240 of each mask, electronic device 210 or other suitable device can transfer the pattern in the mask layout 240 to the corresponding mask using any pattern transfer method suitable for masks (e.g., laser direct writing), thereby obtaining a mask with a main pattern and auxiliary patterns as mentioned above.

[0034] In example environment 200, electronic device 210 can be any type of computing device, such as a terminal device or a server device. In some embodiments, the terminal device can be any type of mobile terminal, fixed terminal, or portable terminal, including mobile phones, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, media computers, multimedia tablets, personal communication system (PCS) devices, personal navigation devices, personal digital assistants (PDAs), audio / video players, digital cameras / camcorders, positioning devices, television receivers, radio receivers, e-book devices, gaming devices, or any combination thereof, including accessories and peripherals of these devices or any combination thereof.

[0035] In some embodiments, the server-side device may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks, and big data and artificial intelligence platforms. The server-side device may include, for example, computing systems / servers, such as mainframes, edge computing nodes, computing devices in a cloud environment, and so on.

[0036] Figure 3 A flowchart of an example process 300 for layout processing according to some embodiments of the present disclosure is shown. Process 300 may be implemented at electronic device 210. It should be noted that the embodiments of the present disclosure can be applied to the processing of layouts for chips of a specific size, and in particular to the processing of layouts for large-size chips (e.g., chips larger than 33mm × 36mm).

[0037] Reference Figure 3 In block 310, electronic device 210 acquires target layout 230. Target layout 230 can refer to the design layout of target chip 220 or an optimized design layout. Target layout 230 can include patterns that conform to specific process requirements and design rules and are expected to be formed on target chip 220. In some embodiments, the boundary of target layout 230 can be determined based on a seal ring. A seal ring can refer to a sealing structure disposed at the edge of target chip 220 and surrounding the effective circuitry in target chip 220. Figure 4 A schematic diagram of an example 400 of a target layout 230 according to some embodiments of the present disclosure is shown. (Refer to...) Figure 4 In some embodiments, the four boundaries of the target layout 230 (top, bottom, left, right) may coincide with the sealing ring 401.

[0038] In some embodiments, the target layout 230 may be obtained based on optical proximity correction (OPC) of an initial layout of multiple masks. In this way, the deviation between the actual image after photolithography and the expected design can be compensated, thereby ensuring that the final pattern (e.g., the pattern formed on the target chip 220) accurately reflects the original design.

[0039] In some embodiments, the electronic device 210 can correct for optical proximity effects on the initial layout in the following manner. First, the electronic device 210 can simulate the imaging effect of the initial layout under specific lithography conditions (e.g., light source type, numerical aperture, etc.) to identify which areas are susceptible to optical proximity effects. Next, based on the simulation results, the electronic device 210 can make targeted modifications to the affected pattern portions. These modifications include, but are not limited to, linewidth adjustment, adding auxiliary exposure patterns, edge smoothing, and correction of sharp angles, etc. After completing the initial correction, the electronic device 210 can run the simulation again to verify whether the corrected layout can produce the expected results on the target chip 220. If the expected results are produced, the target layout 230 is generated. If the expected results are not produced, the above process is repeated until the relevant requirements are met.

[0040] In the embodiments of this disclosure, in order to achieve pattern transfer for large-size chips, a splicing lithography technique will be used in the subsequent photolithography process. For the multiple masks involved in the splicing lithography technique (here, multiple masks can refer to initial masks that have not yet formed patterns), in frame 320, the electronic device 210 divides the target layout 230 to obtain the corresponding mask layouts of the multiple masks.

[0041] Multiple masks can be independent masks for different process layers (such as gate layers, metal interconnect layers, contact layers, etc.) or different exposure areas within the same process layer. The corresponding mask layouts of the multiple masks can refer to layouts output separately by the electronic device 210 for each mask, used to achieve the regional pattern transfer of the target layout 230 on the target object. The mask layout 240 of at least one of the multiple masks (e.g., the first mask) includes: a first pattern in the target layout 230 corresponding to the first mask and adjacent patterns of the first pattern in the target layout.

[0042] For each mask (e.g., the first mask), the pattern in the target layout 230 corresponding to that mask (e.g., the first pattern) can refer to the main pattern of that mask. In subsequent photolithography processes, the main patterns of each mask will be transferred to a designated area of ​​the target chip 220. The main patterns of each mask will be stitched together on the surface of the target chip 220 according to predetermined rules, thereby reconstructing the overall pattern in the target layout 230.

[0043] In some embodiments, the electronic device 210 may extract adjacent patterns of the first pattern from other areas on the side closest to the first pattern in the target layout 230 based on a predetermined extraction range.

[0044] The predetermined extraction range can be a spatial region pre-defined based on photolithography process characteristics (e.g., the influence range of optical proximity effect and / or mask manufacturing errors, etc.). Electronic device 210 can divide the target layout 230 into multiple regions that facilitate pattern processing based on any suitable method. Other regions near the side of the first pattern can be, in addition to the region where the first pattern is located, regions adjacent to a side of the first pattern (e.g., a side of the first pattern used for splicing with other patterns, such as...). Figure 4 The region immediately adjacent to the right side of the first pattern 501. The adjacent patterns extracted in the above manner have good correlation and continuity with the first pattern 501. This is beneficial for achieving better optical correction effects in subsequent photolithography processes.

[0045] In some embodiments, the electronic device 210 can determine a pattern corresponding to each mask in the target layout 230 based on the corresponding positions of each mask on the target layout 230. Specifically, the electronic device 210 can divide the target layout 230 into multiple regions corresponding to multiple masks (e.g., one-to-one correspondence). As an example, the electronic device 210 can divide the overall pattern in the target layout 230 based on the size of these masks, thereby determining multiple regions corresponding to multiple masks (e.g., one-to-one correspondence). For example, assuming the mask size is 33mm × 36mm, the size of each region segmented by the electronic device 210 from the target layout 230 can be 33mm × 36mm. The electronic device 210 can determine the pattern located in a first region in the target layout 230 as a first pattern. The first region can be a region in multiple regions corresponding to the first mask. The electronic device 210 can determine the pattern located in a second region in the target layout 230 as a second pattern. The second region can be a region in multiple regions adjacent to the first region, and the second pattern is the pattern used to stitch with the first pattern in subsequent photolithography processes. Based on this, the electronic device 210 can use a portion of the second pattern that is closer to the first pattern as an adjacent pattern. In this way, the electronic device 210 can use the portion of the second pattern used to join with the first pattern as an auxiliary pattern for the first pattern. Such an auxiliary pattern can be regarded as an extension of the first pattern, thus achieving a better optical proximity correction effect.

[0046] Reference Figure 4Assuming that multiple mask bodies are two masks of the same size (or more masks, but for ease of discussion, this disclosure uses two masks as an example), one mask A and the other mask B. In this case, the electronic device 210 can divide the target layout 230 into two regions corresponding one-to-one with the two masks. For example, the electronic device 210 can divide the target layout 230 into left and right regions based on the center line of the target layout 230. Further, the electronic device 210 can determine the pattern located in the left region of the target layout 230 as the pattern corresponding to mask A (e.g., the first pattern 501). The electronic device 210 can determine the pattern located in the right region of the target layout 230 as the pattern corresponding to mask B (e.g., the second pattern 502). And so on.

[0047] The adjacent patterns of the first pattern 501 can be extracted from the second pattern 502. Figure 5A A schematic diagram of an example 500A for determining a mask layout 240 according to some embodiments of the present disclosure is shown. (Refer to...) Figure 5A The electronic device 210 can use a portion of pattern 503 of the second pattern 502 that is closer to the first pattern 501 as an adjacent pattern of the first pattern 501. It should be noted that the adjacent patterns of the first pattern 501 are not limited to a portion of pattern 503 in the second pattern 502. Depending on actual needs, other patterns corresponding to other masks may exist around the first pattern 501, and so on. In this case, the adjacent patterns of the first pattern 501 may also include portions of these other patterns that are closer to the first pattern 501, and so on.

[0048] In some embodiments, based on the corresponding mask layout of each mask, electronic device 210 or other suitable device can transfer the pattern in mask layout 240 to the corresponding mask using any pattern transfer method suitable for masks. This results in a mask with a specific pattern. The specific pattern here may refer to an auxiliary pattern (e.g., partial pattern 503) formed at the splicing portion (e.g., the right side of the first pattern) where the main pattern (e.g., the first pattern 501) of the mask (e.g., the first mask) is used to splice with other patterns. When performing photolithography using this mask, the auxiliary pattern can modulate the light intensity distribution at the corresponding splicing portion, thereby inducing the required optical proximity effect to compensate for exposure defects at the splicing portion. In this way, embodiments of the present disclosure can improve problems such as pattern distortion at the splicing points of multiple masks during splicing photolithography, thereby optimizing the photolithography imaging quality.

[0049] It should be noted that the above explanation uses the mask layout 240-1 of the first mask as an example. Depending on actual needs, the corresponding mask layouts for multiple masks can be determined using the same method. For example, Figure 5BA schematic diagram of an example 500B of determining a mask layout 240 according to some embodiments of the present disclosure is shown. (Refer to...) Figure 5B For at least one of a plurality of masks (e.g., the third mask), the electronic device 210 can determine the pattern in the target layout 230 corresponding to the third mask (e.g., the second pattern 502, also referred to as the main pattern of the third mask) and the adjacent pattern of the second pattern 502 (e.g., a portion of the first pattern 501 near the second pattern 502). The electronic device can determine the second pattern 502 and the portion of the pattern 504 as the corresponding mask layout 240-2 of the third mask, and so on. For ease of discussion, the following description continues to use the corresponding mask layout 240-1 of the first mask as an example to illustrate various example implementations of the embodiments of this disclosure.

[0050] In some embodiments, the electronic device 210 may extract a portion of the pattern 503 based on a predetermined extraction range. Figure 6A A schematic diagram of example 600A, showing a predetermined extraction range 601 according to some embodiments of the present disclosure, is shown. Figure 6B A schematic diagram of example 600B of reference pattern 602 according to some embodiments of the present disclosure is shown. (See reference...) Figure 6A and Figure 6B The electronic device 210 can extract a reference pattern 602 on the side of the second pattern 502 closest to the first pattern 501 based on a predetermined extraction range 601. In some embodiments, the electronic device 210 can use the extracted reference pattern 602 as a portion of the second pattern 502 on the side closest to the first pattern 501. Alternatively, in some embodiments, the electronic device 210 can perform pattern optimization on at least one edge of the reference pattern 602. Subsequently, the electronic device 210 can use the pattern-optimized reference pattern 602 as a portion of the second pattern 502 on the side closest to the first pattern 501.

[0051] By optimizing the reference pattern 602 extracted from the second pattern 502, aberrations (such as incomplete patterns) at the edges of the reference pattern 602 can be eliminated. This optimization ensures that these aberrations are not transferred into the mask, thereby preventing subsequent photolithography processes from being affected by these aberrations.

[0052] As mentioned above, the predetermined extraction range 601 can be a spatial region pre-defined based on the characteristics of the photolithography process (such as the influence range of optical proximity effect and / or mask manufacturing error). As an example, the predetermined extraction range 601 can refer to a section extending from one edge of the second pattern 502 close to the first pattern 501 (e.g., the left edge of the second pattern 502) towards the second pattern 502 away from the first pattern 501.

[0053] In addition to the predetermined extraction range 601, in some embodiments, the electronic device 210 may use other methods to extract a portion of the pattern 503. For example, the electronic device 210 may extract a portion of the pattern 503 from the second pattern 502 based on a predetermined ratio, and so on.

[0054] In some embodiments, adjacent patterns (e.g., partial patterns 503) of the first pattern 501 in the target layout 230 may be extracted from the second pattern 502 based on a predetermined extraction range 601. The predetermined extraction range 601 may be determined at least based on the extent to which the edges of the first pattern 501 are affected by optical proximity effects.

[0055] The influence range of the optical proximity effect refers to the effective area in which the imaging of the target pattern on the photoresist changes due to optical diffraction and interference between patterns on the mask during photolithography. This influence range can be determined through OPC simulation. For example, during OPC simulation, it is possible to assess how much influence (e.g., 1.5 μm to 2 μm) might affect the imaging of the edge of the first pattern 501 on the photoresist under specific photolithography conditions (such as light source wavelength, numerical aperture, etc.). Based on these analysis results, the size of the predetermined extraction range 601 can be defined. For example, if the OPC simulation results indicate that the edge of the first pattern 501 is affected within a 1.5 μm radius, then the predetermined extraction range 601 can be a distance extending outward from at least 1.5 μm from the edge of the first pattern 501. In this way, a portion of the pattern 503 can be reasonably extracted from the second pattern 502. On the one hand, the portion of the pattern 503 can have a sufficient size to ensure that the light intensity distribution at the junction of the first pattern 501 is effectively improved. On the other hand, some patterns 503 are not too large, thus preventing them from having an adverse effect on photolithography.

[0056] In some embodiments, in addition to the extent to which the edge of the first pattern 501 is affected by the optical proximity effect, the electronic device 210 can further combine other factors such as mask manufacturing errors to comprehensively determine the size of the predetermined extraction range 601. For example, if the results of OPC simulation indicate that the edge of the first pattern 501 is affected within a range of 1.5 μm around it, then the predetermined extraction range 601 can be a distance that covers at least 10 μm outward from the edge of the first pattern 501. In this way, a certain margin can be provided for part of the pattern 503 to offset the effects of errors or other factors. Moreover, this margin is negligible compared to the size of the mask pattern 240 itself (e.g., 33 mm × 36 mm). Furthermore, this margin also helps to provide sufficient space for the pattern optimization mentioned above, thereby ensuring the effective implementation of pattern optimization.

[0057] In some embodiments, the pattern optimization mentioned above may include a size reduction operation on a first object to be optimized located at at least one side edge of the reference pattern 602. Alternatively or additionally, in some embodiments, pattern optimization may include a size enlargement operation on a second object to be optimized located at at least one side edge of the reference pattern 602.

[0058] The first and second objects to be optimized can be determined according to actual optimization needs, and the embodiments of this disclosure do not limit this. For example, the first and / or second objects to be optimized may refer to incomplete graphics present at the edge of the reference pattern 602. By performing size reduction and / or size enlargement operations, the influence of these incomplete graphics on the photolithography process can be eliminated. In some embodiments, the scope 603 of pattern optimization can be determined at least based on the design size requirements of the second pattern 502. The design size requirements (Design Rules) of the second pattern 502 may refer to the specific requirements specified for the pattern in terms of key dimensions, line width, spacing, edge-to-edge spacing, graphic density, shape ratio, etc. In this way, the scope 603 of pattern optimization can be dynamically defined, so that the pattern optimization is more in line with the actual situation of the second pattern 502 and the optimization effect is improved.

[0059] In some embodiments, the first pattern 501 and the second pattern 502 are arranged along a first direction X. The first direction X may be, for example, a... Figure 6B In the horizontal direction, in this case, the first pattern 501 and the second pattern 502 are adjacent to each other on the left and right. Correspondingly, Figure 6B The vertical direction in this context can also be referred to as the second direction Y. Based on this, the electronic device 210 can perform pattern optimization on the edge of the reference pattern 602 that is away from the first pattern 501. For example, in... Figure 6BIn this design, the edge of the reference pattern 602 furthest from the first pattern 501 can be the right edge of the reference pattern 602. Since this edge corresponds to the cut edge of the reference pattern 602, it is most likely to produce anomalous graphics. By optimizing the pattern at least on this edge, high-quality graphics output can be obtained with less graphics processing overhead. The size of the pattern optimization range 603 in the first direction X can be larger than the minimum design size indicated by the design size requirements. This helps eliminate "small graphics" smaller than the minimum design size that may occur when extracting the reference pattern 602. The minimum design size can refer to the minimum size specified for the second pattern in terms of key dimensions, line width, spacing, edge-to-edge spacing, graphic density, shape ratio, etc. In some embodiments, the pattern optimization range can be greater than or equal to N times the minimum design size. For example, assuming the minimum design size is 1.8 μm, then the pattern optimization range can be 5 μm or other appropriate values, and so on.

[0060] It should be noted that, Figure 6B The arrangement of the first pattern 501 and the second pattern 502 is merely an example. Depending on actual needs, the first pattern 501 and the second pattern 502 may also be arranged vertically adjacently, which will not be elaborated further in the embodiments of this disclosure.

[0061] In some embodiments of this disclosure, a photolithography method is also provided. Figure 7 A flowchart of a photolithography process 700 according to some embodiments of the present disclosure is shown. The following is in conjunction with… Figure 1 and Figure 5A The process 700 is described in detail below. In block 710, multiple masks are provided to electronic device 210 or other suitable device. The multiple masks are fabricated based on corresponding mask patterns. The corresponding mask patterns of the multiple masks can be based on, for example... Figure 5A The method shown is used to determine this. For example, electronic device 210 divides the target layout to obtain corresponding mask layouts for multiple masks. The mask layout of the second mask among the multiple masks includes the third pattern in the target layout corresponding to the second mask and the adjacent patterns of the third pattern in the target layout. The incomplete description of the corresponding mask layouts here can be determined by referring to the description of the mask layout 240-1 of the first mask above, and will not be repeated here.

[0062] In some embodiments, after obtaining the mask layout 240, the electronic device 210 or other suitable device may use any pattern transfer method applicable to the mask to transfer the pattern in the mask layout 240 to the corresponding mask. In this case, at least one of the multiple masks (e.g., the second mask) will have a main pattern (e.g., the third pattern), and there are also auxiliary patterns (e.g., a portion of the pattern extracted from the fourth pattern) at the splicing points of the main pattern.

[0063] After acquiring multiple masks, in frame 720, electronic device 210 uses photolithography to transfer target pattern 230 to a designated object based on the multiple masks. For example, electronic device 210 can use stitching photolithography to sequentially transfer the patterns on each mask onto target chip 220, thereby stitching together and reconstructing the overall pattern in target pattern 230 on target chip 200. As mentioned above, auxiliary patterns can regulate the light intensity distribution at the corresponding stitching portion, thereby triggering the required optical proximity effect to compensate for exposure defects at the stitching portion. In this way, embodiments of this disclosure can improve problems such as pattern distortion at the stitching points of multiple masks during stitching photolithography, thereby optimizing photolithography quality.

[0064] In some embodiments, during the photolithography process, electronic device 210 or other suitable device can designate a region in the second mask having the third pattern as an effective photolithography region. Furthermore, electronic device 210 can designate a region in the second mask having an adjacent pattern of the third pattern as an ineffective photolithography region.

[0065] As mentioned earlier, the third pattern is the main pattern of the second mask, used to indicate the graphic content that should actually be transferred onto the target chip 220 during exposure. The effective lithography area can refer to the area on the mask that allows light to shine on it during the lithography process. In practical applications, electronic equipment 210 or other suitable equipment can control the exposure system (such as a scanner) to align with the effective lithography area for exposure, thereby forming a latent image on the photoresist consistent with the third pattern. The ineffective lithography area refers to the area on the mask that, although it contains a graphic structure (i.e., the portion of the pattern extracted from the fourth pattern mentioned earlier), is not actually exposed during the lithography process or is shielded by the optical system. The pattern in this area can produce the desired optical proximity effect on the third pattern, thereby improving exposure defects at the junctions of the third pattern.

[0066] Figure 8 A schematic diagram of an example 800 of multiple masks according to some embodiments of the present disclosure is shown. (Refer to...) Figure 8 Mask 810 can be fabricated, for example, based on mask pattern 240-1 mentioned above, and mask 820 can be fabricated, for example, based on mask pattern 240-2 mentioned above. Mask 810 has a main pattern 811 and an auxiliary pattern 812 (e.g., which can be extracted from the main pattern 821 of mask 820), and mask 820 has a main pattern 821 and an auxiliary pattern 822 (e.g., which can be extracted from the main pattern 811 of mask 810). For clarity, in Figure 8 The image also shows the area 830 where the sealing ring is located.

[0067] During the photolithography process, the area containing the main pattern 811 in mask 810 can be set as an effective photolithography area (e.g., indicated by the crosshair arrow inside mask 810), while the area containing the auxiliary pattern 812 in mask 810 is set as an ineffective photolithography area. Similarly, the area containing the main pattern 821 in mask 820 is set as an effective photolithography area (e.g., indicated by the crosshair arrow inside mask 820), while the area containing the auxiliary pattern 822 in mask 820 is set as an ineffective photolithography area.

[0068] Electronic device 210 or other suitable device can divide the effective and ineffective lithography regions during the photolithography process in any suitable manner. For example, Figure 9 A schematic diagram of an example 900 of a photolithography process according to some embodiments of the present disclosure is shown. (Refer to...) Figure 9 In some embodiments, during the photolithography process, the electronic device 210 can block invalid photolithography areas on the mask (e.g., mask 810) by adjusting the light-blocking plate 901 in the exposure system, so that the exposure system exposes only the valid photolithography areas.

[0069] In some embodiments, the mask (e.g., mask 810) may include a substrate 902, a light-shielding layer (e.g., which may have a main pattern 811 and an auxiliary pattern 812), a support structure 903, and a protective layer 904, etc. The thickness d1 of the substrate 902 (e.g., 5 mm or other values) and the spacing d2 between the substrate 902 and the protective layer 904 (e.g., 5 mm or other values) are much greater than the thickness d3 of the light-shielding layer (e.g., 50 nm or other values). In this way, during exposure, light from the edge of the light-shielding plate 901 (e.g., diffracted light) can still reach the auxiliary pattern 812 below its shielded area. The auxiliary pattern 812 can therefore modulate the incident light field, thereby achieving the desired optical proximity effect compensation or optimization. In this way, embodiments of the present disclosure can improve the process performance of large-size chips (exceeding the maximum mask area) at mask seams, thereby solving the exposure defects faced by such designs at mask seams. In addition to the two-mask-based lithography schemes listed above, the embodiments of this disclosure can also be applied to schemes that use more masks (e.g., three masks, four masks, or even nine masks, etc.) for lithography, thus having better scalability and flexibility.

[0070] Figure 10 A block diagram is shown of an electronic device 1000 in which one or more embodiments of the present disclosure may be implemented. The electronic device 1000 may, for example, be used to implement... Figure 2 The electronic device 210 shown. It should be understood that, Figure 10The electronic device 1000 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.

[0071] Reference Figure 10 The electronic device 1000 is in the form of a general-purpose electronic device. Components of the electronic device 1000 may include, but are not limited to, one or more processors 1010, memory 1020, storage device 1030, one or more communication units 1040, one or more input devices 1050, and one or more output devices 1060. The processor 1010 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 1020. In a multiprocessor system, multiple processors execute computer-executable instructions in parallel to improve the parallel processing capability of the electronic device 1000.

[0072] Electronic device 1000 typically includes multiple computer storage media. Such media can be any available media accessible to electronic device 1000, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 1020 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 1030 can be removable or non-removable media and may include machine-readable media, such as flash drives, disks, or any other media capable of storing information and / or data and accessible within electronic device 1000.

[0073] Electronic device 1000 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 10 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 1020 may include computer program product 1025 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0074] The communication unit 1040 enables communication with other electronic devices via a communication medium. Additionally, the functionality of the components of the electronic device 1000 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, the electronic device 1000 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0075] Input device 1050 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 1060 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 1000 can also communicate with one or more external devices (not shown) via communication unit 1040 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 1000, or with any device that enables electronic device 1000 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0076] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, wherein the computer-executable instructions are executed by a processor to implement the methods described above. According to an exemplary implementation of this disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, which are executed by a processor to implement the methods described above.

[0077] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0078] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0079] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0080] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0081] Various implementations of this disclosure have been described above. The foregoing description is exemplary and not exhaustive, nor is it limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is determined to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A layout processing method, characterized in that, The method includes: Obtain the target map; and The target layout is divided to obtain corresponding mask layouts for multiple masks, wherein the mask layout of the first mask in the multiple masks includes a first pattern in the target layout corresponding to the first mask and adjacent patterns of the first pattern in the target layout.

2. The method according to claim 1, characterized in that, The adjacent patterns of the first pattern are extracted in the following way: Based on a predetermined extraction range, the adjacent patterns are extracted from other areas on the side closest to the first pattern in the target layout.

3. The method according to claim 1 or 2, characterized in that, Dividing the target map includes: The target layout is divided into multiple regions corresponding to the multiple masks; The pattern located in the first region of the target layout is determined as the first pattern, wherein the first region is the region in the plurality of regions that corresponds to the first mask; The pattern located in the second region of the target map is defined as the second pattern, wherein the second region is a region adjacent to the first region among the plurality of regions; and The portion of the second pattern that is closer to the first pattern is designated as the adjacent pattern.

4. The method according to claim 3, characterized in that, The portion of the second pattern closest to the first pattern is determined in the following manner: Based on a predetermined extraction range, a reference pattern is extracted from the side of the second pattern that is close to the first pattern; Pattern optimization is performed on at least one edge of the reference pattern; as well as The reference pattern, after pattern optimization, is used as the partial pattern.

5. The method according to claim 4, characterized in that, The pattern optimization includes at least one of the following: The size reduction operation for the first object to be optimized located at at least one edge of the reference pattern, or Size enlargement operation for a second object to be optimized located at at least one edge of the reference pattern.

6. The method according to claim 4, characterized in that, The scope of the pattern optimization is determined at least based on the design size requirements of the second pattern.

7. The method according to claim 6, characterized in that, The first pattern and the second pattern are arranged along a first direction, and pattern optimization is performed on at least one edge of the reference pattern, including: The pattern optimization is performed on the edge of the reference pattern away from the first pattern, and the extent of the pattern optimization in the first direction is greater than the minimum design size indicated by the design size requirement.

8. The method according to claim 1, characterized in that, The adjacent patterns are extracted from the target layout based on a predetermined extraction range, which is determined at least based on the extent to which the edges of the first pattern are affected by the optical proximity effect.

9. The method according to claim 1, characterized in that, The target layout is obtained by correcting the initial layout of the plurality of masks for optical proximity effect.

10. A photolithography method, characterized in that, The method includes: Based on multiple masks, photolithography is used to transfer a target layout to a specified object; and The plurality of masks are fabricated based on corresponding mask layouts, which are determined in the following manner: The target layout is divided to obtain corresponding mask layouts for the plurality of masks, wherein the mask layout of the second mask in the plurality of masks includes the third pattern in the target layout corresponding to the second mask and the adjacent patterns of the third pattern in the target layout.

11. The method according to claim 10, characterized in that, Transferring a target layout to a specified object using photolithography includes: During the photolithography process, the region in the second mask containing the third pattern is designated as the effective photolithography region; and The region in the second mask that has the adjacent pattern is set as an invalid lithography region.

12. An electronic device, characterized in that, include: At least one processor; as well as At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, causing the electronic device to perform the method according to any one of claims 1 to 9, or to perform the method according to claim 10 or 11.

13. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that, The computer-executable instructions can be executed by a processor to implement the method according to any one of claims 1 to 9, or to perform the method according to claim 10 or 11.

14. A computer program product comprising computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a processor, implement the method according to any one of claims 1 to 9, or perform the method according to claim 10 or 11.

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