A polynomial multiplication accelerator

Abstract

The application provides a polynomial multiplication accelerator, and relates to the technical field of multiplication accelerator, and comprises a calculation module, wherein the calculation module comprises a number theory transform unit, an iterative convolution unit and an inverse number theory transform unit; the number theory transform unit is configured to perform a number theory transform operation on a to-be-calculated polynomial in a global ring by using a first butterfly subunit with a number of execution layers to obtain a first intermediate result; the iterative convolution unit is configured to perform an iterative convolution operation on the first intermediate result in a quotient ring to obtain a second intermediate result; and the inverse number theory transform unit is configured to perform an inverse number theory transform operation on the second intermediate result in the global ring by using a second butterfly subunit with a number of execution layers to obtain a target result, so as to solve the problem that the current polynomial multiplication accelerator forces to perform butterfly operations of all levels completely, resulting in that part of the calculation resources are used to process low significant bit operations with low contribution to the result, and causing significant redundant computing power.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of multiplication accelerator, and in particular to a polynomial multiplication accelerator. BACKGROUND

[0002] In high-throughput application scenarios such as big data processing, cryptography operation and artificial intelligence acceleration, the calculation efficiency of polynomial multiplication as a core operator directly affects the overall performance of the system.

[0003] At present, the fast number theory transform (NTT) and its inverse transform (INTT) in the complete number field are generally used to realize polynomial multiplication. This scheme converts time domain convolution into frequency domain point multiplication, reducing the complexity from O(n2) to quasi-linear O(nlog2n). The specific process includes: performing forward NTT on the input polynomial to convert the coefficient representation into frequency domain point value representation; completing point multiplication operation in the frequency domain; and finally restoring the result through inverse INTT. Among them, NTT adopts a hierarchical butterfly calculation structure, each layer of butterfly operation includes modulus multiplication and modulus addition operations, and data order correctness needs to be ensured through bit reversal rearrangement between layers. For example, for a polynomial with a length of n=2 k , k layers of butterfly operation are required, and each layer includes butterfly units.

[0004] However, in the hierarchical calculation of NTT, the last few layers of butterfly operation have a low contribution to the final result. However, the current scheme still forces to completely perform butterfly operation of all levels, resulting in that part of the computing resources is used to process low significant bit operation with low contribution to the result, causing significant computing power redundancy. SUMMARY

[0005] The present application provides a polynomial multiplication accelerator to solve the technical problem that the existing polynomial multiplication accelerator forces to completely perform butterfly operation of all levels, resulting in that part of the computing resources is used to process low significant bit operation with low contribution to the result, causing significant computing power redundancy.

[0006] The present application provides a polynomial multiplication accelerator, comprising:

[0007] A calculation module, the calculation module comprising:

[0008] A number theory transform unit, an iterative convolution unit and an inverse number theory transform unit; the number theory transform unit is provided with a plurality of layers of first butterfly sub-units; the inverse number theory transform unit is provided with a plurality of layers of second butterfly sub-units;

[0009] The number theory transform unit is configured to:

[0010] The first butterfly subunit with an execution layer number is used to perform a number theory transform operation on the to-be-calculated polynomial in a global ring to obtain a first intermediate result; the execution layer number is k-m;

[0011] In the formula, k=log2n; n is the point number of the polynomial multiplication accelerator; and m is a set value.

[0012] The iterative convolution unit is configured to:

[0013] An iterative convolution operation is performed on the first intermediate result in a quotient ring to obtain a second intermediate result.

[0014] The inverse number theory transform unit is configured to:

[0015] The second butterfly subunit with an execution layer number is used to perform an inverse number theory transform operation on the second intermediate result in the global ring to obtain a target result.

[0016] In some embodiments, the global ring is: ;

[0017] In the formula, is an integer set representing the value range of the coefficients of the to-be-calculated polynomial; is a variable in the to-be-calculated polynomial;

[0018] The quotient ring is: ;

[0019] In the formula, = ; = ; is a twist factor; () represents an integer bit inversion operation; represents the ring number of the quotient ring.

[0020] In some embodiments, the first butterfly subunit and the second butterfly subunit include:

[0021] A multiplier configured to perform a modulo multiplication operation;

[0022] A first adder configured to perform a modulo addition operation;

[0023] A first subtractor configured to perform a modulo subtraction operation.

[0024] In some embodiments, the iterative convolution unit is provided with a plurality of second adders and second subtractors;

[0025] The second adder is configured to perform a modulo addition operation;

[0026] The second subtracter is configured to perform a modulo subtraction operation.

[0027] In some embodiments, the number theoretic transform unit is configured with a rotation factor table, the rotation factor table is configured with original rotation factors, the original rotation factors are used to perform a modulo multiplication operation in the number theoretic transform operation;

[0028] The polynomial multiplication accelerator further comprises:

[0029] The first memory is configured to:

[0030] Obtain the original rotation factors and twist factors;

[0031] Based on the original rotation factors and the twist factors, calculate target rotation factors and store.

[0032] In some embodiments, the inverse number theoretic transform unit is configured with an inverse rotation factor table, the inverse rotation factor table is configured with original inverse rotation factors, the original inverse rotation factors are used to perform a modulo multiplication operation in the inverse number theoretic transform operation;

[0033] The polynomial multiplication accelerator further comprises:

[0034] The second memory is configured to:

[0035] Obtain the original inverse rotation factors and twist factors;

[0036] Based on the original inverse rotation factors and the twist factors, calculate target inverse rotation factors and store.

[0037] In some embodiments, the polynomial multiplication accelerator further comprises:

[0038] The third memory is configured to:

[0039] Store the to-be-calculated polynomial coefficients.

[0040] In some embodiments, the third memory is configured with 16 memory banks, the memory banks are provided with 4096 addresses;

[0041] The polynomial multiplication accelerator accesses 16 different to-be-calculated polynomial coefficients in parallel through the memory banks in one clock cycle.

[0042] In some embodiments, the third memory adopts an in-place storage structure;

[0043] The third memory is further configured to:

[0044] updating the intermediate coefficients generated in the process of performing the number theoretic transform operation, the iterative convolution operation, and the inverse number theoretic transform operation on the to-be-calculated polynomial to the positions in the third memory where the coefficients of the to-be-calculated polynomial are located.

[0045] In some embodiments, the polynomial multiplication accelerator further comprises:

[0046] a control module configured to:

[0047] controlling the data flow inside the polynomial multiplication accelerator in the form of a finite state machine.

[0048] The present application provides a polynomial multiplication accelerator, comprising: a calculation module, the calculation module comprising: a number theoretic transform unit, an iterative convolution unit, and an inverse number theoretic transform unit; the number theoretic transform unit is provided with a plurality of layers of first butterfly sub-units; the inverse number theoretic transform unit is provided with a plurality of layers of second butterfly sub-units; the number theoretic transform unit is configured to perform a number theoretic transform operation on a to-be-calculated polynomial in a global ring by using the first butterfly sub-units with a number of execution layers to obtain a first intermediate result; the number of execution layers is: k-m; where k=log2n; n is the number of points of the polynomial multiplication accelerator; m is a set value; the iterative convolution unit is configured to perform an iterative convolution operation on the first intermediate result in a quotient ring to obtain a second intermediate result; and the inverse number theoretic transform unit is configured to perform an inverse number theoretic transform operation on the second intermediate result in the global ring by using the second butterfly sub-units with a number of execution layers to obtain a target result, so as to solve the problem that the current polynomial multiplication accelerator forces to perform butterfly operations of all levels completely, resulting in that part of the computing resources are used to process low significant bit operations with low contribution to the result, causing significant computing redundancy. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0050] Figure 1 It is a structural schematic diagram of the polynomial multiplication accelerator in the present application.

[0051] Figure 2 It is a structural schematic diagram of the calculation module in the present application.

[0052] Figure 3 It is a calculation cost curve diagram of the number theoretic transform unit switching to the iterative convolution unit under different switching layers.

[0053] Figure 4Timeline analysis diagram of the polynomial multiplication accelerator in the present application under the condition of n = 65536;

[0054] Figure 5 Performance comparison analysis diagram between the original multiplication accelerator and the multiplication accelerator in the present application under different scales.

[0055] Explanation of reference signs:

[0056] 1 - calculation module; 11 - number theory transformation unit; 111 - first butterfly subunit; 12 - iterative convolution unit; 121 - second adder; 122 - second subtractor; 13 - inverse number theory transformation unit; 131 - second butterfly subunit; 1311 - multiplier; 1312 - first adder; 1313 - first subtractor; 2 - first memory; 3 - second memory; 4 - third memory; 5 - control module. DETAILED DESCRIPTION

[0057] In order to enable persons skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should be within the scope of protection of the present application.

[0058] In some technologies, the polynomial multiplication accelerator forces complete execution of all levels of butterfly operation, resulting in some computing resources being used to process low significant bit operations with low contribution to the result, causing significant computing power redundancy. In order to solve this technical problem, the present application provides a polynomial multiplication accelerator. The structures of the parts of the polynomial multiplication accelerator will be described below:

[0059] For example, the polynomial multiplication accelerator provided by the present application is used to process the polynomial: A(X) = a_0 + a_1×X + a_2×X 2 +... + a_(n-1)×X n-1 .

[0060] For example, the polynomial multiplication accelerator provided by the present application is used to process the polynomial: A(X) = a_0 + a_1×X + a_2×X 2 +... + a_(n-1)×X n-1 . Figure 1As shown, the polynomial multiplication accelerator architecture provided by the present application is mainly divided into three core units: a storage unit, a calculation module 1 and a control module 5. Among them, the storage unit includes a simple double-port third memory 4 for polynomial coefficients, and a first memory 2 and a second memory 3 for storing target rotation factors and target inverse rotation factors; the calculation module 1 includes two number theory transformation units 11, one inverse number theory transformation unit 13 and one iterative convolution unit 12; and the control module 5 controls the data flow inside the accelerator in the form of a finite state machine (FSM).

[0061] The present application provides a polynomial multiplication accelerator, comprising:

[0062] a calculation module 1, wherein the calculation module 1 comprises:

[0063] a number theory transformation unit 11, an iterative convolution unit 12 and an inverse number theory transformation unit 13; the number theory transformation unit 11 is provided with a plurality of layers of first butterfly sub-units 111; and the inverse number theory transformation unit 13 is provided with a plurality of layers of second butterfly sub-units 131.

[0064] The number theory transformation unit 11 is configured to:

[0065] perform a number theory transformation operation on a to-be-calculated polynomial in a global ring by using the first butterfly sub-units 111 of the execution layers to obtain a first intermediate result; the execution layers are: k-m; and the global ring is: ;

[0066] wherein, is an integer set representing the value range of the coefficients of the to-be-calculated polynomial; all integers from 0, 1, 2,..., to q-1 are included, and the value range of the polynomial coefficient a_(n-1) is defined. It can prevent the numerical value from increasing indefinitely during the calculation, and “restrict” the operation within a controllable range, thereby realizing the basis of the homomorphic encryption property. is a variable in the to-be-calculated polynomial; k=log2n; n is the number of points of the polynomial multiplication accelerator; and m is a set value, which is the dimension of switching to a quotient ring.

[0067] wherein, defines the “cyclic” or “folding” rule of the polynomial multiplication. It indicates that in the operation system, + 1 = 0, i.e. = -1. When two polynomials of the highest n-1 degree are multiplied, the highest degree of the result reaches 2n-2. The above rule is used to show how to handle the term whose degree is greater than or equal to n. For example, when is encountered, it is replaced by -1; and when is encountered, it becomes -1x , i.e. . So any operation result can be "folded" back to a polynomial of degree less than n, ensuring that the operation result always remains in the same "field". The above phenomenon is called negative convolution.

[0068] The iterative convolution unit 12 is configured to:

[0069] perform an iterative convolution operation on the first intermediate result in a quotient ring to obtain a second intermediate result; the quotient ring is: ;

[0070] wherein, = ; = ; is a twist factor; () represents an integer bit-reversal operation; represents the ring number of the quotient ring.

[0071] The inverse number theory transformation unit 13 is configured to:

[0072] perform an inverse number theory transformation operation on the second intermediate result in a global ring by using the second butterfly subunit 131 of the execution layer number to obtain a target result.

[0073] The following embodiment takes m = 4 as an example for illustration.

[0074] wherein, is a variable in a smaller polynomial ring, and the n-dimensional calculation problem (represented by A(X)) in the quotient ring is decomposed into independent 4-dimensional small problems (represented by A(X)). Therefore, A(X) corresponds to an n-1 degree polynomial, which is mapped to small 3-degree polynomials, for example, , , , , .

[0075] wherein, and there is a mathematical mapping relationship between is a certain high power of . Specifically, can be regarded as power of , i.e. . Through this substitution, the high power polynomial problem about is reconstructed into a group of problems about The problem of low-power polynomials.

[0076] For example, computations within a global ring occur within a polynomial ring. Within, polynomials A and B are respectively in the global ring. Internal execution The layer undergoes a number-theoretic transformation (NTT) operation, followed by a "ring switch" from the global ring. Switch to A separate four-cycle business ring Inside, among which After performing ICA (iterative convolution) operations in the four quotient rings, the remaining operations are then performed in the global ring. Layer inverse number theory transformation (INTT) operation.

[0077] Furthermore, this application evaluates the computational cost at different switching points between number-theoretic transformations and iterative convolution (ICA), as shown in the curves below. Figure 3 As shown in the figure, it can be seen that when the number of switching layers is 6, the computational load reaches the global minimum. However, considering that this application supports multiple point count specifications, such as ( Choosing 4 layers as the actual number of layers to switch can ensure computational efficiency (while still achieving a reduction of approximately 22.20% in computational load), and also provides better flexibility and scalability, making the internal polynomial multiplication accelerator architecture more easily adaptable to polynomial multiplication computation needs of different scales.

[0078] In this embodiment, the first butterfly subunit 111 and the second butterfly subunit 131 include:

[0079] Multiplier 1311, configured to perform modular multiplication operation; first adder 1312, configured to perform modular addition operation; first subtractor 1313, configured to perform modular subtraction operation.

[0080] In this embodiment, the iterative convolution unit 12 is provided with a plurality of second adders 121 and second subtractors 122; the second adders 121 are configured to perform modular addition operations; and the second subtractors 122 are configured to perform modular subtraction operations.

[0081] like Figure 2 As shown, the computational flow of number-theoretical transformation and iterative convolution is introduced using two stages as examples. The number-theoretical transformation / inverse number-theoretical transformation is performed based on the first butterfly subunit 111 and the second butterfly subunit 131, and each of the first butterfly subunit 111 and the second butterfly subunit 131 contains one adder, one multiplier, and one subtractor; the iterative convolution algorithm relies on addition and subtraction operations to complete the corresponding transformation.

[0082] In this embodiment, the number theoretic transform unit 11 is configured with a rotation factor table, which is configured with original rotation factors used to perform the modulo multiplication operation in the number theoretic transform operation.

[0083] The polynomial multiplication accelerator further comprises:

[0084] The first memory 2 is configured to:

[0085] The original rotation factors and twist factors are obtained, and a target rotation factor is calculated and stored based on the original rotation factors and the twist factors.

[0086] In this embodiment, the inverse number theoretic transform unit 13 is configured with an inverse rotation factor table, which is configured with original inverse rotation factors used to perform the modulo multiplication operation in the inverse number theoretic transform operation.

[0087] The polynomial multiplication accelerator further comprises:

[0088] The second memory 3 is configured to:

[0089] The original inverse rotation factors and twist factors are obtained, and a target inverse rotation factor is calculated and stored based on the original inverse rotation factors and the twist factors.

[0090] Specifically, in the global ring , the calculation of polynomial multiplication belongs to a negative convolution with a length of , and a general practice is to add a preprocessing operation and a post-processing operation to the operations of the number theoretic transform and the inverse number theoretic transform, both of which need to traverse each coefficient in the polynomial and complete a modulo multiplication, becoming a memory access and time delay bottleneck. The present application absorbs the preprocessing operation and the post-processing operation into the rotation factor table and the inverse rotation factor table corresponding to the number theoretic transform and the inverse number theoretic transform, so that the butterfly operation implicitly completes the twist processing required by the negative convolution while performing the discrete transform.

[0091] Specifically, the specific process of the preprocessing operation includes: first selecting a special constant as a "twist factor ", satisfying mod q = 1; then multiplying the polynomial coefficients of the polynomial A(X) by ; generating a new polynomial A'(X) with coefficients a'_(n-1)=a_(n-1)× . The above operation needs to traverse each coefficient of the polynomial A(X), and on the hardware, it means that N coefficients need to be read from the memory, N times of modulo multiplication is performed, and the result is written back to the memory.

[0092] Specifically, the post-processing operation specific process includes: selecting the intermediate result polynomial C(X) with the coefficient c'_(n-1); then multiplying the polynomial coefficient of the intermediate result polynomial C(X) by ; generating a new polynomial C'(X) with the coefficient c_(n-1) = c'_(n-1) x . The above operation needs to traverse each coefficient of the polynomial C(X), and on the hardware, it is a complete reading of N coefficients, N times of modular multiplication and one write operation.

[0093] In summary, the above operation process needs additional clock cycles to complete the 2N times (A(X) and C(X) each once) multiplication operation, needs to read and write the polynomial data completely twice, greatly increases the memory access pressure and becomes a performance bottleneck. The present application omits the pre-processing and post-processing operations, calculates the target rotation factor and the target inverse rotation factor, stores the target rotation factor and the target inverse rotation factor in the first memory 2 and the second memory 3, and directly obtains the rotation factor with the twisted effect, i.e. the target rotation factor and the target inverse rotation factor, from the first memory 2 and the second memory 3 when performing the number theory transformation calculation or the inverse number theory transformation. The polynomial A(X) implicitly and without additional overhead completes the pre-processing and post-processing operations when performing the number theory transformation calculation or the inverse number theory transformation, greatly reducing the calculation time.

[0094] In this embodiment, the polynomial multiplication accelerator further includes:

[0095] The third memory 4 is configured to:

[0096] store the to-be-calculated polynomial coefficients.

[0097] In this embodiment, the third memory 4 is configured with 16 memory banks, and the memory banks are provided with 4096 addresses; the polynomial multiplication accelerator accesses 16 different to-be-calculated polynomial coefficients in parallel through the memory banks in one clock cycle.

[0098] Specifically, the application provides a conflict-free memory access scheme to support full pipelining operation mode and optimize the utilization of on-chip storage resources. To meet the throughput requirement of each cycle processing 16 data of the three arithmetic units of number theoretic transform / inverse number theoretic transform / iterative convolution, to ensure that the pipeline is not blocked, the third memory 4 is divided into 16 independent memory banks (Bank), each of which contains 4096 addresses. This multi-bank structure enables the polynomial multiplier to access 16 different coefficients in parallel in one clock cycle, thereby matching the processing capacity of the arithmetic unit. To reduce the on-chip storage resources, the application adopts an in-place storage structure, and all intermediate coefficients in the transformation process are updated in place in the same third memory 4.

[0099] Exemplarily, the polynomial multiplier provided by the application has the most significant improvement, which is the time delay reduction caused by the introduction of the iterative convolution unit 12. Figure 4 is In the case of timeline analysis, the current polynomial multiplier pure number theoretic transform scheme needs to perform complete number theoretic transform / inverse number theoretic transform, which requires 4 stages in this case, and each stage occupies 4096 clock cycles; the introduction of the iterative convolution unit 12 realizes efficient shunting and parallel processing of the calculation task, and the iterative convolution unit 12 can undertake kernel operations that originally need to be performed in the sequentially executed number theoretic transform / inverse number theoretic transform stage. Through this parallelization strategy, the calculation time delay on the critical path of data processing is greatly reduced.

[0100] The polynomial multiplier provided by the application realizes the improvement of time delay performance under different sizes (N) of polynomial points, as shown in FIG. 3. Figure 5 In the medium and large-scale scenarios, the optimization effect is significant, and the performance is improved by 53.5% and 44.3%, respectively; even in the small-scale scenario, the polynomial multiplier provided by the application can still provide a performance improvement of 20.0%.

[0101] In this embodiment, the third memory 4 adopts an in-place storage structure.

[0102] The third memory 4 is further configured to:

[0103] update the intermediate coefficients generated in the process of performing the number theoretic transform operation, the iterative convolution operation, and the inverse number theoretic transform operation on the to-be-calculated polynomial to the location of the to-be-calculated polynomial coefficients in the third memory 4.

[0104] ​​​In this embodiment, the data transfer time is reduced by setting the third memory 4 of the in-place storage structure. The intermediate coefficients are directly updated to the original positions of the polynomial coefficients to be calculated in the third memory 4, avoiding the cumbersome process of first storing the intermediate coefficients in other temporary positions and then transferring them back to the original positions for subsequent calculations. The reduction in the number of data transfers directly reduces the time overhead of data transmission, making the calculation process more compact and significantly improving the overall calculation speed. For example, in cryptographic algorithms, if the number theory transform operation can reduce data transfer, the encryption or decryption time can be greatly shortened. And improve the potential of parallel computing, this updating method is beneficial to the design and implementation of parallel computing architecture. Since the intermediate coefficients are directly updated to the original positions, different computing units can simultaneously perform number theory transform, iterative convolution or inverse number theory transform operations on different parts of the polynomial coefficients without worrying about data storage location conflicts or additional data synchronization problems. The advantages of parallel computing are fully utilized, further accelerating the calculation speed.

[0105] In this embodiment, the polynomial multiplication accelerator further comprises:

[0106] The control module 5 is configured to:

[0107] Control the data flow inside the polynomial multiplication accelerator in the form of a finite state machine.

[0108] In this embodiment, the data flow inside the polynomial multiplication accelerator is controlled in the form of a finite state machine, which can accurately control the calculation process. The finite state machine subdivides the calculation process of the polynomial multiplication accelerator into multiple explicit states, such as data reading, coefficient preprocessing, multiplication operation, result accumulation, data output, etc. In each state, the accelerator only performs specific operations related to that state, and strictly follows the pre-set state transition sequence to advance the calculation. This precise control avoids unnecessary waiting and idle time, ensuring a compact and efficient calculation process, reducing the calculation period, and significantly improving the overall calculation speed. And the finite state machine can intelligently arrange the data access order and frequency according to the needs of the calculation state. For example, in the preprocessing state, the data required for subsequent calculations is read into the cache in advance, reducing the data access delay in the subsequent calculation process. By optimizing the data access mode, the impact of data transmission on calculation performance is reduced, and the data flow processing efficiency is improved.

[0109] The present application provides a polynomial multiplication accelerator, which truncates the polynomial multiplication based on the number theory transform and splices it with the iterative convolution algorithm under the premise of keeping the polynomial ring dimension and the number theory domain parameters unchanged, that is, adding an iterative convolution unit 12 to the calculation module 1, thereby reducing the calculation complexity.

[0110] The above detailed description of the embodiments of the present application is merely intended to provide a further detailed description of the purpose, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above is only a specific implementation of the embodiments of the present application, and is not used to limit the protection scope of the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A polynomial multiplication accelerator applied to encryption and decryption; characterized in that, The application relates to a polynomial multiplication accelerator. The polynomial multiplication accelerator comprises: a calculation module (1) comprising: a number theory transformation unit (11), an iterative convolution unit (12) and an inverse number theory transformation unit (13); the number theory transformation unit (11) is provided with a plurality of layers of first butterfly subunits (111); the inverse number theory transformation unit (13) is provided with a plurality of layers of second butterfly subunits (131); the number theory transformation unit (11) is configured to: perform a number theory transformation operation on a to-be-calculated polynomial in a global ring by using the first butterfly subunits (111) of an execution layer number, to obtain a first intermediate result; the execution layer number is k-m; wherein k=log2n; n is the point number of the polynomial multiplication accelerator; and m is a set value; the iterative convolution unit (12) is configured to: perform an iterative convolution operation on the first intermediate result in a quotient ring, to obtain a second intermediate result; the inverse number theory transformation unit (13) is configured to: perform an inverse number theory transformation operation on the second intermediate result in the global ring by using the second butterfly subunits (131) of an execution layer number, to obtain a target result; a third memory (4) configured with a plurality of storage banks provided with a plurality of addresses; the third memory (4) adopts an in-place storage structure; the polynomial multiplication accelerator accesses a plurality of different to-be-calculated polynomial coefficients in parallel in one clock cycle through the storage banks; the third memory (4) is configured to: store the to-be-calculated polynomial coefficients; 2. A polynomial multiplication accelerator according to claim 1, wherein, The global ring is: ; In the formula, characterized as an integer set of the value range of the polynomial coefficients to be calculated; characterized as a variable in the polynomial to be calculated; The business ring is: ; wherein ; ; is a twist factor; () represents an integer bit-reversal operation; represents the ring number of the quotient ring.

3. A polynomial multiplication accelerator according to claim 1, wherein, update intermediate coefficients generated in the process of performing the number theory transformation operation, the iterative convolution operation and the inverse number theory transformation operation on the to-be-calculated polynomial to the positions of the to-be-calculated polynomial coefficients in the third memory (4). the first butterfly subunits (111) and the second butterfly subunits (131) comprise: a multiplier (1311) configured to perform a modulo multiplication operation; a first adder (1312) configured to perform a modulo addition operation; 4. The polynomial multiplication accelerator of claim 1, wherein, a first subtracter (1313) configured to perform a modulo subtraction operation. the iterative convolution unit (12) is provided with a plurality of second adders (121) and second subtracters (122); the second adders (121) are configured to perform modulo addition operations; 5. The polynomial multiplication accelerator of claim 1, wherein, the second subtracters (122) are configured to perform modulo subtraction operations. the number theory transformation unit (11) is provided with a rotation factor table configured with original rotation factors used for performing the modulo multiplication operation in the number theory transformation operation; the polynomial multiplication accelerator further comprises: a first memory (2) configured to: obtain the original rotation factors and twist factors; 6. The polynomial multiplication accelerator of claim 1, wherein, calculate target rotation factors based on the original rotation factors and the twist factors and store the target rotation factors. the inverse number theory transformation unit (13) is provided with an inverse rotation factor table configured with original inverse rotation factors used for performing the modulo multiplication operation in the inverse number theory transformation operation; The polynomial multiplication accelerator further comprises: a second memory (3) configured to: obtain the original inverse rotation factor and a twist factor; based on the original inverse rotation factor and the twist factor, calculate a target inverse rotation factor and store.

7. The polynomial multiplication accelerator of claim 1, wherein, Further comprising: a control module (5) configured to: control the data flow inside the polynomial multiplication accelerator in the form of a finite state machine.

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