A thread scheduling system and method, electronic device and storage medium

Abstract

The present disclosure relates to a thread scheduling system and method, an electronic device and a storage medium, the system comprising: an instruction cache module, an instruction register module, an execution module; the instruction cache module is configured to pre-read instruction data of a plurality of threads; the instruction register module is configured to store the pre-read instruction data of the plurality of threads, and in one clock cycle, determine a target thread and a target instruction of the target thread according to the instruction data of the plurality of threads; and the instruction register module is configured to send the target instruction of the target thread to the execution module. The embodiment of the present disclosure effectively reduces the thread scheduling time in the instruction pipeline scenario, and improves the utilization rate of the execution module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a thread scheduling system and method, an electronic device and a storage medium. BACKGROUND

[0002] In the design of a graphics processing unit (GPU), instruction cache is crucial to the efficiency of thread execution in the instruction pipeline of a streaming multiprocessor (SM). The instruction pipeline of a traditional GPU has a large delay. For common high-concurrency graphics scenarios, the delay can be masked by high thread parallelism. However, under new requirements, common computing tasks do not have high thread parallelism. At this time, if the delay of the instruction pipeline is large, many problems are exposed, such as insufficient utilization of arithmetic and logic unit (ALU) resources and long total execution time. Therefore, in order to better serve new requirements, higher requirements are put forward for the delay of the instruction pipeline. SUMMARY

[0003] The present disclosure provides a thread scheduling system and method, an electronic device and a storage medium.

[0004] According to an aspect of the present disclosure, a thread scheduling system is provided, comprising: an instruction cache module, an instruction register module, and an execution module; the instruction cache module is configured to pre-read instruction data of a plurality of threads; the instruction register module is configured to store the pre-read instruction data of the plurality of threads, and determine a target thread and a target instruction of the target thread according to the instruction data of the plurality of threads within one clock cycle; and the instruction register module is configured to send the target instruction of the target thread to the execution module.

[0005] In a possible implementation, the instruction register module is specifically configured to: within one clock cycle, perform instruction dependency checking on an instruction with the highest instruction order priority in the stored instruction data of each thread; determine a thread passing the instruction dependency checking as the target thread, and determine an instruction with the highest instruction order priority in the instruction data of the thread as the target instruction of the target thread.

[0006] In a possible implementation, the system comprises: a thread scheduling module; the thread scheduling module is configured to determine a thread in a current scheduling according to a preset scheduling rule in a clock cycle, and allocate a register pointer for the thread in the current scheduling, wherein the register pointer allocated for the thread in the current scheduling is used to indicate an instruction order priority of an instruction to be read by the thread in the current scheduling.

[0007] In a possible implementation, the instruction cache module is specifically configured to: for any scheduling of any thread, read an instruction to be read by the thread in the current scheduling according to a program counter (PC) address of the thread in the current scheduling; and send the instruction read by the thread in the current scheduling to the instruction register module for storage according to the register pointer allocated for the thread in the current scheduling.

[0008] In a possible implementation, the instruction cache module comprises: an instruction cache tag submodule, a judgment submodule, and an instruction cache storage submodule; the instruction cache tag submodule is configured to, for any scheduling of any thread, perform cache lookup on the thread in the current scheduling according to a PC address of the thread in the current scheduling, and determine a cache lookup result of the thread in the current scheduling; and the judgment submodule is configured to, for any scheduling of any thread, read an instruction to be read by the thread in the current scheduling from the instruction cache storage submodule based on a first instruction read request of the thread in the current scheduling.

[0009] In a possible implementation, the instruction cache tag submodule is specifically configured to: for any scheduling of any thread, if the cache lookup result of the thread in the current scheduling is cache hit, send a first instruction read request of the thread in the current scheduling to the judgment submodule, wherein the first instruction read request of the thread in the current scheduling comprises a cache line identifier of the thread in the current scheduling that is hit, and a PC address of the thread in the current scheduling.

[0010] In a possible implementation, the instruction cache module comprises a lookup failure processing submodule; and the instruction cache tag submodule is specifically configured to: for any scheduling of any thread, if the cache lookup result of the thread in the current scheduling is cache miss, determine a target cache line for the thread in the current scheduling; and send a lookup failure record request of the thread in the current scheduling to the lookup failure processing submodule, wherein the lookup failure record request of the thread in the current scheduling comprises a target cache line identifier corresponding to the thread in the current scheduling, and a PC address of the thread in the current scheduling.

[0011] In a possible implementation, the instruction cache tag sub-module is further configured to: in the case that the cache lookup result of the current scheduling of any one thread is cache miss, send, to a next-level instruction storage module corresponding to the instruction cache module, a second instruction read request of the current scheduling of the thread, wherein the second instruction read request of the current scheduling of the thread comprises a PC address of the current scheduling of the thread.

[0012] In a possible implementation, the lookup failure processing sub-module is specifically configured to: record lookup failure record requests of a plurality of threads; check, in a clock cycle, whether the earliest lookup failure record request of each thread corresponding to a scheduling time meets a preset condition, wherein the preset condition is used to indicate that data corresponding to the current scheduling of the thread has been stored in the cache storage module; determine a thread meeting the preset condition; and send, to the decision sub-module, a first instruction read request of the current scheduling of the thread.

[0013] In a possible implementation, in the case that the decision sub-module simultaneously receives, in a clock cycle, the first instruction read request sent by the instruction cache tag sub-module and the first instruction read request sent by the lookup failure processing sub-module, the priority of the first instruction read request sent by the lookup failure processing sub-module is higher than that of the first instruction read request sent by the instruction cache tag sub-module.

[0014] According to an aspect of the present disclosure, a thread scheduling method is provided, comprising: pre-reading instruction data of a plurality of threads by using an instruction cache module; storing the pre-read instruction data of the plurality of threads by using an instruction register module, and determining, in a clock cycle, a target thread and a target instruction of the target thread according to the instruction data of the plurality of threads; and sending, by using the instruction register module, the target instruction of the target thread to an execution module.

[0015] According to an aspect of the present disclosure, an electronic device is provided, comprising the above thread scheduling system.

[0016] According to an aspect of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above method.

[0017] According to an aspect of the present disclosure, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the above method.

[0018] In the embodiments of the present disclosure, the thread scheduling system comprises: an instruction cache module, an instruction register module, and an execution module; the instruction cache module is configured to pre-read instruction data of a plurality of threads, and store the pre-read instruction data of the plurality of threads in the instruction register module, so that the instruction register module can determine a target thread and a target instruction of the target thread from the stored instruction data of the plurality of threads in one clock cycle, and send the target instruction of the target thread to the execution module, thereby effectively reducing thread scheduling time in an instruction pipeline scenario, and improving utilization of the execution module.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the present disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the technical solutions of the present disclosure.

[0021] Figure 1 A block diagram of a thread scheduling system according to an embodiment of the present disclosure is shown.

[0022] Figure 2 A schematic diagram of a thread scheduling system according to an embodiment of the present disclosure is shown.

[0023] Figure 3 A flowchart of a thread scheduling method according to an embodiment of the present disclosure is shown.

[0024] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference signs in the drawings represent functionally identical or similar elements. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0026] The word "exemplary" is used herein in the sense of being an example, illustration, or demonstration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0027] The term "and / or", merely describes association relationship of associated objects, and indicates that three relationships can exist, for example, A and / or B can indicate that A exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" in this paper indicates any one of multiple or any combination of at least two of multiple, for example, at least one of A, B and C includes any one or more elements selected from the set consisting of A, B and C.

[0028] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the specific embodiments below. Those skilled in the art should understand that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, elements and circuits well known to those skilled in the art are not described in detail, in order to highlight the main idea of the present disclosure.

[0029] A plurality of computing tasks can be executed in one SM, and one computing task (for example, a segment of assembly instructions) can be executed by several threads, and each thread executes the same code segment (for example, each thread corresponds to the same 1000 instructions). The thread is the smallest unit of scheduling by the operating system, and a thread includes a thread identity (Identity Document, ID) and a current instruction pointer (used to indicate the address of the next instruction to be executed by the thread). Each thread has its own independent program counter (Program Counter, PC), also known as instruction pointer register. The main function of PC is to store the address of the next instruction to be executed. For any thread, when the CPU finishes executing the current instruction of the thread, it reads the address of the next instruction from the PC of the thread, so that the CPU can correctly execute the next instruction. During the running of the thread, the PC of the thread is constantly updated to point to the address of the next instruction to be executed, so as to ensure that the thread can execute the instructions in the correct order.

[0030] The instruction pipeline is a way to divide the operation of an instruction into several small steps, each step is completed by a special circuit. For example, the execution of an instruction needs to go through three stages: instruction fetching, decoding, and execution, and each stage takes one clock cycle. If the instruction pipeline technology is not used, the execution of this instruction needs 3 clock cycles; if the instruction pipeline technology is used, when this instruction completes "fetching" and enters "decoding", the next instruction can perform "fetching" at the same time, so that the execution efficiency of the instruction is improved.

[0031] Stream Processors (SMs) generally refer to hardware units specially designed for processing data streams (e.g., video, audio, or graphics data). They perform a large number of simple operations in a highly parallelized manner to achieve fast processing of data streams. Stream processors are widely used in high-performance computing devices such as GPUs, application-specific integrated circuits (ASICs), and the like.

[0032] In a GPU design, an instruction cache is a module in an SM for fetching instructions, and its upstream is a thread scheduling module. When the thread scheduling module schedules a current instruction pointer (PC address) of a thread, a cache lookup needs to be performed in the instruction cache. When the cache hits, the corresponding instruction is read and transmitted downstream. When the cache misses, a failure flag is also transmitted downstream, and after being uniformly processed by the downstream module, the thread scheduling module is fed back. In the related art, for the PC address of the cache miss, the thread needs to be scheduled again to be successfully executed by the subsequent module, which wastes a scheduling opportunity.

[0033] Therefore, a certain instruction may be scheduled again because the instruction cache does not have information of the instruction at the first scheduling. Since each scheduling can be considered as a valuable opportunity, it is necessary to improve the scheduling efficiency. In a traditional instruction pipeline, a thread is serially and sequentially scheduled in a pipeline structure. If a certain instruction cache misses, the subsequent instructions cannot be scheduled and read instruction information, which is not conducive to reducing the delay of the entire thread.

[0034] For example, a current computing task corresponds to 10 threads, and in a clock cycle, a thread scheduling module selects one thread from the 10 threads for scheduling. If the instruction to be read by the thread in this scheduling hits in the instruction cache, the thread scheduling module further performs instruction dependency checking on the instruction read from the instruction cache for this scheduling. If the instruction dependency checking fails, the PC address of the instruction and related reasons are fed back to the thread scheduling module, and the thread scheduling module has the opportunity to schedule the PC address again when the related reasons meet the conditions. The thread scheduling module fails to schedule the thread this time, and the scheduling of the thread this time causes the threads in the other 9 threads that have cache hits and pass the instruction dependency checking to lose an opportunity to be scheduled out.

[0035] To solve the above problems, the thread scheduling system provided in the embodiments of the present disclosure can reduce the time consumption of thread scheduling in an instruction pipeline scenario and improve the utilization rate of an execution module. The thread scheduling system provided in the embodiments of the present disclosure is described in detail below.

[0036] Figure 1 A block diagram of a thread scheduling system according to an embodiment of the present disclosure is shown. As shown in FIG. 1, the thread scheduling system includes a thread scheduling module 101, an instruction cache 102, and an execution module 103.Figure 1 As shown, the thread scheduling system comprises: an instruction cache module, an instruction register module, and an execution module; the instruction cache module is configured to pre-read instruction data of multiple threads; the instruction register module is configured to store the pre-read instruction data of the multiple threads, and determine, in one clock cycle, a target thread and a target instruction of the target thread according to the instruction data of the multiple threads; and the instruction register module is configured to send the target instruction of the target thread to the execution module.

[0037] In the embodiments of the present disclosure, the thread scheduling system comprises: an instruction cache module, an instruction register module, and an execution module; the instruction cache module is configured to pre-read instruction data of multiple threads, and store the pre-read instruction data of the multiple threads in the instruction register module; thus, the instruction register module can determine, in one clock cycle, a target thread and a target instruction of the target thread from the stored instruction data of the multiple threads, and send the target instruction of the target thread to the execution module, thereby effectively reducing thread scheduling time in an instruction pipeline scenario and improving utilization of the execution module.

[0038] In a possible implementation, the instruction register module is specifically configured to: perform instruction dependency checking on an instruction with the highest instruction sequence priority in the instruction data of each thread stored in one clock cycle; determine a thread passing the instruction dependency checking as the target thread, and determine an instruction with the highest instruction sequence priority in the instruction data of the thread as the target instruction of the target thread.

[0039] Since the instruction register module stores the instruction data of the multiple threads, the instruction register can perform instruction dependency checking on an instruction with the highest instruction sequence priority in the instruction data of each thread stored in one clock cycle. As long as any one of the multiple threads passes the dependency checking, the thread is determined as the target thread, and an instruction with the highest instruction sequence priority in the thread is determined as the target instruction of the target thread, thereby completing scheduling of the target instruction in the target thread. Compared with the thread scheduling manner in the related art, the embodiments of the present disclosure utilize the instruction register module to reduce the probability that threads meeting the scheduling condition cannot be scheduled out.

[0040] In addition, in the related art, since there is a case that threads meeting the scheduling condition cannot be scheduled out, the utilization rate of the execution module is low. For example, if the success rate of the thread scheduling module is 70%, the utilization rate of the execution module can be simply considered as 70%.

[0041] The embodiment of the present disclosure can be considered that the instruction register module can always select the target instruction of the target thread and issue the target instruction to the execution module in each clock cycle during stable operation, so the utilization rate of the execution module can be considered to be approximately 100%.

[0042] In an example, in a clock cycle, when it is determined that there are multiple threads passing the dependency check, a thread passing the dependency check is selected as the target thread according to a preset selection condition, and the target instruction of the target thread is sent to the execution module. The preset selection condition can be flexibly set according to an actual application scenario, and the present disclosure does not make a specific limitation.

[0043] In a possible implementation, the thread scheduling system includes: a thread scheduling module; the thread scheduling module is configured to determine a thread in a clock cycle according to a preset scheduling rule, and allocate a register pointer for the thread in the clock cycle, where the register pointer allocated for the thread in the clock cycle is used to indicate an instruction order priority of an instruction to be read by the thread in the clock cycle.

[0044] The thread scheduling module in the thread scheduling system is an upstream module of the instruction cache module, and the thread scheduling module is configured to schedule each thread in the SM. In a clock cycle, the thread scheduling module selects a thread meeting a condition from multiple threads to be scheduled according to a preset scheduling rule. The preset scheduling rule can be flexibly set according to an actual application scenario, and the present disclosure does not make a specific limitation.

[0045] The thread scheduling module allocates a register pointer for each scheduling of each thread, to indicate an instruction order priority of multiple instructions in each thread, so as to ensure an execution order of the multiple instructions in each thread.

[0046] For example, thread 1 includes 1000 instructions. When the thread scheduling module schedules a first instruction (ins1) in thread 1, the thread scheduling module allocates a register pointer 1 for ins1; when the thread scheduling module schedules a second instruction (ins2) in thread 1, the thread scheduling module allocates a register pointer 2 for ins2; when the thread scheduling module schedules a third instruction (ins3) in thread 1, the thread scheduling module allocates a register pointer 3 for ins3; and so on, which will not be described in detail.

[0047] Since the register pointer is assigned for each instruction of thread 1, it is assumed that, for the above three instructions, the first instruction cache hits (ins1 hit), the second instruction cache misses (ins2 miss), and the third instruction cache hits (ins3 hit). In this case, ins3 can be implemented to overtake into the instruction register. That is, ins3 enters the instruction register for storage before ins2, but ins2 can still find the correct storage location according to the assigned register pointer 2 to indicate that the instruction order priority of ins2 is prior to ins3 when ins2 enters the instruction register.

[0048] Figure 2 A schematic diagram of a thread scheduling system according to an embodiment of the present disclosure is shown. As shown, the thread scheduling system includes a thread scheduling module, an instruction cache module. Figure 2

[0049] In one clock cycle, for the thread selected by the thread scheduling module for the current scheduling, the thread scheduling module sends the PC address of the thread to the downstream instruction cache module according to the current instruction pointer of the thread, so as to complete the instruction fetching operation of the thread for the current scheduling based on the instruction cache module.

[0050] For example, in one clock cycle, the thread scheduling module selects thread 1 for scheduling from a plurality of threads that need to be scheduled according to a preset scheduling rule, and then the thread scheduling module sends a scheduling request to the instruction cache module, where the scheduling request includes: thread 1 (thread identifier), and the PC address of thread 1 for the current scheduling.

[0051] As shown, the thread scheduling module sends a scheduling request to the instruction cache module. Figure 2

[0052] In addition, the thread scheduling module can also send the relevant information of thread 1 for the current scheduling to the instruction register module: thread 1 (thread identifier), the PC address of thread 1 for the current scheduling, and the register pointer allocated for the current scheduling of thread 1, so as to accurately store the instructions of thread 1 for the current scheduling in the corresponding position of the instruction register module.

[0053] In a possible implementation, the instruction cache module is specifically configured to: for any scheduling of any thread, read the instructions to be read by the thread for the current scheduling according to the PC address of the current scheduling of the thread; and send the instructions read by the thread for the current scheduling to the instruction register module for storage according to the register pointer allocated for the current scheduling of the thread.

[0054] ​​For any one thread for any one scheduling, the instruction cache module reads the instructions that the thread needs to read according to the PC address of the thread this time, and completes the instruction fetching operation of the thread this time. Further, the instruction cache module sends the instructions read by the thread this time to the instruction register module for storage according to the register pointer allocated by the thread this time, and prepares for the subsequent execution of the instructions of the thread this time.

[0055] As shown in Figure 2 The thread scheduling system includes an instruction register module. The instruction register module is used to store the instruction data of multiple threads read from the instruction cache module.

[0056] In a possible implementation, the instruction cache module includes an instruction cache tag submodule, a decision submodule, and an instruction cache storage submodule. The instruction cache tag submodule is used to, for any one thread for any one scheduling, perform cache lookup on the thread this time according to the PC address of the thread this time, and determine the cache lookup result of the thread this time. The decision submodule is used to, for any one thread for any one scheduling, read the instructions that the thread this time needs to read from the instruction cache storage submodule based on the first instruction read request of the thread this time.

[0057] The instruction cache storage submodule includes multiple cache lines, and each cache line is used to store instruction data. The instruction cache tag submodule has the same cache line structure as the instruction cache storage submodule, but the instruction cache tag submodule does not store instruction data, but is used to record the cache line information of each cache line in the instruction cache storage submodule.

[0058] For example, the instruction cache storage submodule includes N cache lines: cache lines 1-N, and each cache line is used to store instruction data. The instruction cache tag submodule also includes N cache lines, which correspond to the N cache lines included in the instruction cache storage submodule one by one, and are used to record the cache line information of the N cache lines in the instruction cache storage submodule. The cache line information in the instruction cache tag submodule can be as shown in Table 1.

[0059] Table 1

[0060] Cache line identification Cache line state Tag Lock count (lock_cnt) Cache line 1 Valid tag 1 1 Cache line 2 Invalid 0 0 Cache line 3 Invalid 0 0 …… …… …… …… Cache line N Invalid 0 0

[0061] As shown in Table 1, for any one cache line, the cache line state of the cache line in the instruction cache tag submodule is used to indicate whether the instruction data in the cache line in the instruction cache storage submodule is valid or has expired, etc. The cache line state of cache line 1 in the instruction cache tag submodule is valid, which is used to indicate that the instruction data in cache line 1 in the instruction cache storage submodule is valid; the cache line states of cache lines 2 / 3 in the instruction cache tag submodule are invalid, which are used to indicate that the instruction data in cache lines 2 / 3 in the instruction cache storage submodule is invalid, or the instruction data in cache lines 2 / 3 has expired, or there is no instruction data in cache lines 2 / 3. Similarly, no further description is given.

[0062] As shown in Table 1, for any one cache line, if the instruction data is stored in the cache line in the instruction cache storage submodule, the corresponding tag field in the cache line in the instruction cache tag submodule stores the corresponding tag, which is the high bits of the PC address.

[0063] As shown in Table 1, for any one cache line, if the lock count corresponding to the cache line in the instruction cache tag submodule is not 0, the instruction data stored in the cache line in the instruction cache storage submodule cannot be replaced.

[0064] For any one thread and any one scheduling, the thread scheduling module sends the PC address of the current scheduling of the thread to the instruction cache tag submodule, and the instruction cache tag submodule performs cache lookup on the current scheduling of the thread according to the tag (high bits) in the PC address to determine the cache lookup result of the current scheduling of the thread.

[0065] For any one thread and any one scheduling, when the tag in the PC address of the current scheduling of the thread is stored in the instruction cache tag submodule, it is determined that the cache lookup result of the current scheduling of the thread is cache hit; otherwise, it is determined that the cache lookup result of the current scheduling of the thread is cache miss.

[0066] Taking Table 1 above as an example, for the scheduling of PC address 1 by thread 1, when the tag in PC address 1 is tag 1, since tag 1 is stored in the instruction cache tag submodule, it is determined that the cache lookup result of the scheduling of PC address 1 by thread 1 is cache hit, and the cache line of the hit is cache line 1.

[0067] Taking Table 1 above as an example, for the scheduling of PC address 2 by thread 2, when the tag in PC address 2 is tag 2, since tag 2 is not stored in the instruction cache tag submodule, it is determined that the cache lookup result of the scheduling of PC address 2 by thread 2 is cache miss.

[0068] In a possible implementation, the instruction cache tag submodule is specifically configured to: in the case of a cache hit in the cache lookup result of the current scheduling of any thread, send, to the decision submodule, a first instruction read request of the current scheduling of the thread, where the first instruction read request of the current scheduling of the thread includes the cache line identifier of the current scheduling of the thread and the PC address of the current scheduling of the thread.

[0069] In the case of a cache hit in the cache lookup result of the current scheduling of any thread, the instruction cache tag submodule sends, to the decision submodule, a first instruction read request of the current scheduling of the thread, so that the decision submodule can execute the subsequent operation of fetching an instruction from the instruction cache storage submodule based on the cache line identifier of the current scheduling of the thread included in the first instruction read request and the PC address of the current scheduling of the thread.

[0070] Taking the scheduling of thread 1 to PC address 1 as an example, since the cache lookup result of the scheduling of thread 1 to PC address 1 is a cache hit, and the hit cache line is cache line 1, the instruction cache tag submodule sends, to the decision submodule, a first instruction read request of the scheduling of thread 1 to PC address 1, which includes thread 1 (thread identifier), cache line 1 (hit cache line identifier), and PC address 1.

[0071] As shown in FIG. 6, the instruction cache module includes an instruction cache tag submodule and a decision submodule, and the instruction cache tag submodule sends a first instruction read request to the decision submodule. Figure 2

[0072] In a possible implementation, the instruction cache module includes a lookup failure processing submodule and an instruction cache tag submodule, which is specifically configured to: in the case of a cache miss in the cache lookup result of the current scheduling of any thread, determine a target cache line for the current scheduling of the thread; and send, to the lookup failure processing submodule, a lookup failure record request of the current scheduling of the thread, where the lookup failure record request of the current scheduling of the thread includes the target cache line identifier corresponding to the current scheduling of the thread and the PC address of the current scheduling of the thread.

[0073] In the case of a cache miss in the cache lookup result of the current scheduling of any thread, the instruction cache tag submodule determines a target cache line for the current scheduling of the thread, which is used to store the instruction corresponding to the PC address of the current scheduling of the thread in the subsequent operation.

[0074] ​Taking the scheduling of the PC address 2 by the thread 2 as an example, since the cache lookup result of the thread 2 scheduling the PC address 2 is a cache miss, the instruction cache tag sub-module determines a target cache line for the thread 2 scheduling the PC address 2, that is, the cache line 2, and updates the cache line state of the cache line 2 to a fetched state, the tag to tag2, and the lock count to 1. At this time, the table 1 in the instruction cache tag sub-module is updated to the following table 2.

[0075] Table 2

[0076] Cache line identification Cache line state Tag Lock count (lock_cnt) Cache line 1 Valid tag 1 1 Cache line 2 Fetched tag 2 1 Cache line 3 Invalid 0 0 …… …… …… …… Cache line N Invalid 0 0

[0077] In a possible implementation, the lookup failure processing sub-module is specifically configured to record the lookup failure record request of each thread.

[0078] The lookup failure processing sub-module can record the lookup failure record of each thread. The following table 3 can exemplarily represent the lookup failure record of each thread by the lookup failure processing sub-module.

[0079] Table 3

[0080]

[0081] As shown in Table 3, the lookup failure processing sub-module records N entries, that is, entry(1) to entry(N), for each thread, which sequentially indicate the scheduling time sequence of each lookup failure record in the thread. The specific value of N can be flexibly set according to actual conditions, and the present disclosure does not make a specific limitation on this.

[0082] As shown in Table 3, the valid state corresponding to each record entry of each thread is used to indicate whether the current lookup failure record is valid. When the valid state is 1, it indicates that the current lookup failure record is valid; when the valid state is 0, it indicates that the current lookup failure record is invalid.

[0083] For any record entry of any thread, if the valid state corresponding to the record entry is 1, it indicates that the scheduling instruction corresponding to the record entry has not been stored in the instruction cache storage sub-module.

[0084] For any scheduling of any thread, if the cache lookup result of the current scheduling of the thread is a cache miss, the instruction cache tag sub-module sends a lookup failure record request of the current scheduling of the thread to the lookup failure processing sub-module, where the lookup failure record request of the current scheduling of the thread includes: the target cache line identifier corresponding to the current scheduling of the thread, and the PC address of the current scheduling of the thread.

[0085] Taking the scheduling of the PC address 2 by the thread 2 as an example, since the cache lookup result of the thread 2 scheduling the PC address 2 is a cache miss, the instruction cache tag sub-module sends a lookup failure record request of the thread 2 scheduling the PC address 2 to the lookup failure processing sub-module, and the lookup failure record request of the thread 2 scheduling the PC address 2 includes: the thread 2 (thread identification), the cache line 2 (target cache line identification), and the PC address 2. Assuming that the scheduling of the PC address 2 by the thread 2 is the first time that a cache miss occurs in the thread 2, at this time, the above table 3 in the lookup failure processing sub-module is updated to the following table 4.

[0086] Table 4

[0087]

[0088] As shown in table 4, the first record entry (1) corresponding to the thread 2 is updated to tag2, and the valid state is updated to 1. At this time, it indicates that the instruction corresponding to the thread 2 scheduling the PC address 2 has not been stored in the instruction cache storage sub-module.

[0089] In a possible implementation, the instruction cache tag sub-module is further configured to: for any one thread and any one scheduling, if the cache lookup result of the current scheduling of the thread is a cache miss, send a second instruction read request of the current scheduling of the thread to a next-level instruction storage module corresponding to the instruction cache module, and the second instruction read request of the current scheduling of the thread includes a PC address of the current scheduling of the thread.

[0090] For any one thread and any one scheduling, if the cache lookup result of the current scheduling of the thread is a cache miss, the instruction cache tag sub-module sends a second instruction read request of the current scheduling of the thread to a next-level instruction storage module corresponding to the instruction cache module, so as to read the instruction of the current scheduling of the thread from the next-level instruction storage module to the instruction cache storage sub-module.

[0091] As shown in table 4, the instruction cache tag sub-module sends a second instruction read request to the next-level instruction storage module. Figure 2

[0092] Taking the scheduling of the PC address 2 by the thread 2 as an example, since the cache lookup result of the thread 2 scheduling the PC address 2 is a cache miss, the instruction cache tag sub-module sends a second instruction read request of the thread 2 scheduling the PC address 2 to a next-level instruction storage module corresponding to the instruction cache module, and the second instruction read request of the thread 2 scheduling the PC address 2 includes: the thread 2 (thread identification), the cache line 2 (target cache line identification), and the PC address 2.

[0093] ​The specific form of the next-level instruction storage module can be flexibly set according to an actual scene, and the next-level instruction storage module can serve one SM or multiple SMs, and the present disclosure does not make a specific limitation in this regard.

[0094] The next-level instruction storage module sends the instruction corresponding to the PC address 2 of thread 2 to the cache line 2 in the instruction cache storage submodule for storage in response to the second instruction reading request of the PC address 2 of thread 2.

[0095] When the instruction corresponding to the PC address 2 of thread 2 is stored in the cache line 2 in the instruction cache storage submodule, the table 2 in the instruction cache tag submodule is updated to the following table 5.

[0096] Table 5

[0097] Cache line identification Cache line state Tag Lock count (lock_cnt) Cache line 1 Valid tag 1 1 Cache line 2 Valid tag 2 1 Cache line 3 Invalid 0 0 …… …… …… …… Cache line N Invalid 0 0

[0098] As shown in Table 5, the cache line state corresponding to the cache line 2 is updated to valid.

[0099] In a possible implementation, the lookup failure processing submodule is specifically configured to: in one clock cycle, check whether the earliest lookup failure record request of each thread corresponding to a scheduling time meets a preset condition, where the preset condition is used to indicate that the data corresponding to this scheduling of the thread has been stored in the cache storage module; determine a thread meeting the preset condition, and send a first instruction reading request of this scheduling of the thread to the decision submodule.

[0100] Since the lookup failure processing submodule records the lookup failure record request of each scheduling corresponding to the cache miss of each thread, in one clock cycle, the lookup failure processing submodule can check whether the earliest lookup failure record request of each thread corresponding to a scheduling time meets a preset condition.

[0101] Taking the above thread 2 as an example, the earliest lookup failure record request of thread 2 corresponding to a scheduling time recorded in the lookup failure processing submodule is the lookup failure record request of thread 2 scheduling the PC address 2. Therefore, the lookup failure processing submodule checks whether the lookup failure record request of thread 2 scheduling the PC address 2 meets a preset condition.

[0102] The lookup failure processing submodule checks, according to the tag 2 indicated by the PC address 2, whether the cache line state corresponding to the tag 2 in the instruction cache tag submodule is in a valid state. When the cache line state corresponding to the tag 2 in the instruction cache tag submodule is in a valid state, it is determined that thread 2 scheduling the PC address 2 meets the preset condition; otherwise, the preset condition is not met.

[0103] The lookup failure processing submodule determines that the thread 2 scheduling PC address 2 meets the preset condition, and sends a first instruction reading request of the thread 2 scheduling PC address 2 to the decision submodule. The first instruction reading request includes: thread 2 (thread identifier), cache line 2 (target cache line identifier), and PC address 2.

[0104] In an example, in one clock cycle, the lookup failure processing submodule determines that there are multiple threads meeting the preset condition, selects one of the threads meeting the preset condition at random, and sends a first instruction reading request of this time scheduling of the thread to the decision submodule.

[0105] As shown in FIG. 6, the instruction cache module includes a lookup failure processing submodule. The lookup failure processing submodule sends a first instruction reading request to the decision submodule. Figure 2

[0106] In a possible implementation, when the decision submodule simultaneously receives the first instruction reading request sent by the instruction cache tag submodule and the first instruction reading request sent by the lookup failure processing submodule in one clock cycle, the priority of the first instruction reading request sent by the lookup failure processing submodule is higher than that of the first instruction reading request sent by the instruction cache tag submodule.

[0107] As described above, the first instruction reading request sent by the instruction cache tag submodule to the decision submodule is sent after a cache hit, and the first instruction reading request sent by the lookup failure processing submodule to the decision submodule is sent after reading data from a next-level instruction storage module after a cache miss. That is, the thread scheduling time (the time when the scheduling request is issued by the thread scheduling module) corresponding to the first instruction reading request sent by the lookup failure processing submodule to the decision submodule is necessarily earlier than the thread scheduling time corresponding to the first instruction reading request sent by the instruction cache tag submodule to the decision submodule. Therefore, in order to read data of an earlier thread scheduling time as soon as possible, when the decision submodule simultaneously receives the first instruction reading request sent by the instruction cache tag submodule and the first instruction reading request sent by the lookup failure processing submodule in one clock cycle, the priority of the first instruction reading request sent by the lookup failure processing submodule is higher than that of the first instruction reading request sent by the instruction cache tag submodule. That is, the decision submodule preferentially sends the first instruction reading request sent by the lookup failure processing submodule to the instruction cache storage submodule.

[0108] ​In an example, the instruction cache storage submodule is specifically configured to: for any one thread in any one scheduling, in response to a first instruction reading request of the thread in the current scheduling, reading instructions required to be read by the thread in the current scheduling according to a cache line identifier and a PC address included in the first instruction reading request of the thread in the current scheduling; sending the read instructions of the thread in the current scheduling, the PC address, and a thread identifier to the instruction register module; and determining, by the instruction register module, a register pointer allocated to the thread in the current scheduling according to the PC address and the thread identifier of the thread in the current scheduling, and storing the read instructions of the thread in the current scheduling to a storage position indicated by the register pointer.

[0109] Suppose that the thread scheduling module schedules a thread, the delay of the instructions of the thread in each scheduling through the instruction cache module is 3 clock cycles, the thread has 1000 instructions, and the thread can always be cached in the instruction cache. The instruction dependency check of the thread in each scheduling can be successful. In the related art, the total time length of the thread in the scheduling part is 3000 clock cycles in the serial scheduling mode. In the embodiment of the present disclosure, the thread is scheduled in the pipelining mode, and the total time length of the thread in the scheduling part is (3+1000) clock cycles, which effectively reduces the thread scheduling time consumption in the instruction pipelining scenario.

[0110] In the embodiment of the present disclosure, the thread scheduling system includes an instruction cache module, an instruction register module, and an execution module. The instruction data of multiple threads is pre-read by the instruction cache module, and the pre-read instruction data of the multiple threads is stored in the instruction register module, so that the instruction register module can determine a target thread and a target instruction of the target thread from the stored instruction data of the multiple threads in one clock cycle, and send the target instruction of the target thread to the execution module, which effectively reduces the thread scheduling time consumption in the instruction pipelining scenario and improves the utilization of the execution module.

[0111] Figure 3 A flowchart of a thread scheduling method according to an embodiment of the present disclosure is shown. The method can be applied to the thread scheduling system shown in the above Figure 1 and / or Figure 2 As shown in the above Figure 3 , the method includes the following steps.

[0112] In step S31, the instruction data of multiple threads is pre-read by using the instruction cache module.

[0113] In step S32, the pre-read instruction data of the multiple threads is stored by using the instruction register module, and in one clock cycle, a target thread and a target instruction of the target thread are determined according to the instruction data of the multiple threads.

[0114] In step S33, the target instruction of the target thread is sent to the execution module by the instruction register module.

[0115] In a possible implementation, the instruction register module is configured to store the pre-read instruction data of the plurality of threads, and determine, in one clock cycle, the target thread and the target instruction of the target thread according to the instruction data of the plurality of threads, including:

[0116] The instruction register module is configured to perform, in one clock cycle, instruction dependency checking on the instruction with the highest instruction sequential priority in the stored instruction data of each thread;

[0117] The thread passing the instruction dependency checking is determined as the target thread, and the instruction with the highest instruction sequential priority in the instruction data of the thread is determined as the target instruction of the target thread.

[0118] In a possible implementation, the method further includes:

[0119] The thread scheduling module is configured to determine, in one clock cycle, one thread for the current scheduling according to a preset scheduling rule, and allocate a register pointer for the current scheduling of the thread, where the register pointer allocated for the current scheduling of the thread is used to indicate the instruction sequential priority of the instruction to be read by the current scheduling of the thread.

[0120] In a possible implementation, the instruction cache module is configured to pre-read the instruction data of the plurality of threads, including: for any one thread and any one scheduling, the instruction cache module is configured to read the instruction to be read by the current scheduling of the thread according to a program counter (PC) address of the current scheduling of the thread.

[0121] The instruction read by the current scheduling of the thread is sent to the instruction register module for storage according to the register pointer allocated for the current scheduling of the thread.

[0122] In a possible implementation, for any one thread and any one scheduling, the instruction cache module is configured to read the instruction to be read by the current scheduling of the thread according to a program counter (PC) address of the current scheduling of the thread.

[0123] For any one thread and any one scheduling, the instruction cache tag sub-module in the instruction cache module is configured to perform cache searching on the current scheduling of the thread according to the PC address of the current scheduling of the thread, to determine a cache searching result of the current scheduling of the thread.

[0124] For any one thread, the first instruction read request of the thread is sent to the decision submodule based on the cache lookup result of the thread determined by the instruction cache tag submodule, wherein the first instruction read request of the thread includes the cache line identifier of the thread and the PC address of the thread.

[0125] In a possible implementation, the method further includes:

[0126] For any one thread, the first instruction read request of the thread is sent to the decision submodule based on the cache lookup result of the thread determined by the instruction cache tag submodule, wherein the first instruction read request of the thread includes the cache line identifier of the thread and the PC address of the thread.

[0127] In a possible implementation, the method further includes:

[0128] For any one thread, the first instruction read request of the thread is sent to the decision submodule based on the cache lookup result of the thread determined by the instruction cache tag submodule, wherein the first instruction read request of the thread includes the cache line identifier of the thread and the PC address of the thread.

[0129] The lookup failure record request of the thread is sent to the lookup failure processing submodule in the instruction cache module, wherein the lookup failure record request of the thread includes the target cache line identifier corresponding to the thread and the PC address of the thread.

[0130] In a possible implementation, the method further includes:

[0131] For any one thread, the first instruction read request of the thread is sent to the decision submodule based on the cache lookup result of the thread determined by the instruction cache tag submodule, wherein the first instruction read request of the thread includes the cache line identifier of the thread and the PC address of the thread.

[0132] In a possible implementation, the method further includes:

[0133] The lookup failure record request of the thread is sent to the lookup failure processing submodule in the instruction cache module, wherein the lookup failure record request of the thread includes the target cache line identifier corresponding to the thread and the PC address of the thread.

[0134] In a clock cycle, it is checked whether the earliest lookup failure record request of each thread at the scheduling time meets a preset condition, wherein the preset condition is used to indicate that the data corresponding to the thread has been stored in the cache storage module.

[0135] Determine a thread meeting a preset condition, and send a first instruction read request of this time scheduling of the thread to the decision submodule.

[0136] In a possible implementation, the method further includes:

[0137] In a case where the decision submodule simultaneously receives the first instruction read request sent by the instruction cache tag submodule and the first instruction read request sent by the lookup failure processing submodule within one clock cycle, the priority of the first instruction read request sent by the lookup failure processing submodule is higher than that of the first instruction read request sent by the instruction cache tag submodule.

[0138] It can be understood that the above-mentioned various method embodiments mentioned in the disclosure can be combined with each other to form combined embodiments without deviating from the principle logic. Limited by the length, the disclosure will not be repeated. Those skilled in the art can understand that in the above-mentioned method of the specific implementation, the specific execution order of each step should be determined according to its function and possible internal logic.

[0139] In addition, the disclosure also provides an electronic device, a computer readable storage medium, and a program, all of which can be used to implement any of the thread scheduling methods provided by the disclosure. The corresponding technical solutions and descriptions are described in the method section and will not be repeated here.

[0140] The method has specific technical association with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware operation efficiency or execution effect (including reducing data storage amount, reducing data transmission amount, improving hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the natural law.

[0141] In some embodiments, the apparatus provided by the embodiments of the disclosure has functions or includes modules that can be used to execute the methods described in the above method embodiments, and the specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0142] The embodiments of the disclosure also provide a computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions are executed by a processor to implement the above method. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0143] The embodiments of the disclosure also provide an electronic device, which includes the thread scheduling system shown in the above Figure 1 and / or Figure 2 The thread scheduling system.

[0144] The electronic device according to the embodiments of the present disclosure can be provided as a terminal, a server, or other forms of devices.

[0145] The embodiments of the present disclosure further provide a computer program product, including computer readable code or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is run in the processor of the electronic device, the processor in the electronic device performs the above method.

[0146] The electronic device can be provided as a terminal, a server or other forms of devices.

[0147] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Referring to Figure 4 , the electronic device 1900 can be provided as a server or a terminal device. Referring to Figure 4 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932, for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0148] The electronic device 1900 can also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 can operate based on an operating system stored in the memory 1932, such as Microsoft Server Operating System (Windows Server TM ), Apple's graphical user interface-based operating system (Mac OS X TM ), multi-user multi-process computer operating system (Unix TM ), free and open source Unix-like operating system (Linux TM ), open source Unix-like operating system (FreeBSD TM ) or the like.

[0149] In an exemplary embodiment, a non-volatile computer readable storage medium, such as the memory 1932 including computer program instructions executable by the processing component 1922 of the electronic device 1900 to complete the above method, is also provided.

[0150] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0151] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or punched tape, a

[0152] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0153] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0154] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0155] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0156] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0157] The flow diagrams and the block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0158] The computer program product can be embodied in a tangible medium of

[0159] The above description of the various embodiments is intended to be illustrative in all respects, rather than being restrictive, as it is readily possible to make modifications of the various embodiments, as those skilled in the art would realize upon reading the above description. The scope of the application should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0160] Those skilled in the art can understand that, in the above-described method of the specific embodiments, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process, and the specific execution order of each step should be determined according to its function and possible inherent logic.

[0161] If the technical solutions of the present application involve personal information, the product applying the technical solutions of the present application has been explicitly informed of the personal information processing rules before processing the personal information, and has obtained the personal independent consent. If the technical solutions of the present application involve sensitive personal information, the product applying the technical solutions of the present application has obtained the personal independent consent before processing the sensitive personal information, and at the same time meets the requirement of "explicit consent". For example, at the personal information collection device such as camera, a clear and prominent mark is set to inform that it has entered the personal information collection range and will collect personal information. If the individual voluntarily enters the collection range, it is considered to agree to collect personal information. Or on the device for processing personal information, through the pop-up information or by asking the individual to upload his personal information, the individual's authorization is obtained under the condition that the device uses obvious mark / information to inform the individual of the personal information processing rules. The personal information processing rules can include personal information processor, personal information processing purpose, processing method and personal information type, etc.

[0162] The above has described various embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles, practical application or improvement of technology in the market of the embodiments, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.

Claims

1. A thread scheduling system, characterized in that, include: Instruction cache module, instruction register module, execution module; The instruction cache module is used to pre-fetch instruction data from multiple threads; The instruction register module is used to store the instruction data of the multiple threads to be pre-fetched, and to determine the target thread and the target instruction of the target thread based on the instruction data of the multiple threads within one clock cycle. The instruction register module is used to send the target instruction of the target thread to the execution module; The system includes: a thread scheduling module; The thread scheduling module is used to determine a thread to be scheduled in one clock cycle according to a preset scheduling rule, and to allocate a register pointer for the thread in this scheduling. The register pointer allocated to the thread in this scheduling is used to indicate the instruction order priority of the instructions that the thread needs to read in this scheduling.

2. The system according to claim 1, characterized in that, The instruction register module is specifically used for: Within one clock cycle, perform instruction dependency checks on the instruction with the highest instruction priority in the instruction data stored for each thread; The thread that passes the instruction dependency check is identified as the target thread, and the instruction with the highest instruction order priority in the instruction data of that thread is identified as the target instruction of the target thread.

3. The system according to claim 1, characterized in that, The instruction cache module is specifically used for: For any given thread and any given scheduling, read the instructions that the thread needs to read in this scheduling based on the program counter (PC) address of the thread in this current scheduling. Based on the register pointer allocated to the thread in this scheduling, the instructions read by the thread in this scheduling are sent to the instruction register module for storage.

4. The system according to claim 3, characterized in that, The instruction cache module includes: an instruction cache tag submodule, a decision submodule, and an instruction cache storage submodule; The instruction cache tag submodule is used to perform a cache lookup for any thread in any scheduling, based on the PC address of the current scheduling of the thread, and determine the cache lookup result of the current scheduling of the thread. The decision submodule is used to read the instructions that the thread needs to read in this scheduling based on the first instruction read request of the thread in this scheduling for any scheduling of any thread.

5. The system according to claim 4, characterized in that, The instruction cache tag submodule is specifically used for: For any scheduling of any thread, if the cache lookup result of the current scheduling of the thread is a cache hit, a first instruction read request for the current scheduling of the thread is sent to the decision submodule. The first instruction read request for the current scheduling of the thread includes: the cache line identifier of the current scheduling of the thread and the PC address of the current scheduling of the thread.

6. The system according to claim 4, characterized in that, The instruction cache module includes: a lookup failure handling submodule; The instruction cache tag submodule is specifically used for: For any given thread and any given scheduling, if the cache lookup result for this thread is a cache miss, determine a target cache line for this thread's scheduling. Send a lookup failure record request for the current scheduling of the thread to the lookup failure handling submodule. The lookup failure record request for the current scheduling of the thread includes: the target cache line identifier corresponding to the current scheduling of the thread and the PC address of the current scheduling of the thread.

7. The system according to claim 6, characterized in that, The instruction cache tag submodule is also used for: For any scheduling of any thread, if the cache lookup result of the current scheduling of the thread is a cache miss, a second instruction read request for the current scheduling of the thread is sent to the next-level instruction storage module corresponding to the instruction cache module. The second instruction read request for the current scheduling of the thread includes the PC address of the current scheduling of the thread.

8. The system according to claim 6, characterized in that, The failure handling submodule is specifically used for: Record failed lookup requests from multiple threads; Within one clock cycle, check whether the earliest lookup failure record request corresponding to the scheduling time of each thread meets the preset conditions, wherein the preset conditions are used to indicate that the data corresponding to the current scheduling of the thread has been stored in the cache storage module; Identify a thread that meets the preset conditions and send the first instruction read request for this thread's current scheduling to the decision submodule.

9. The system according to claim 6, characterized in that, If the decision submodule receives both the first instruction read request sent by the instruction cache tag submodule and the first instruction read request sent by the lookup failure handling submodule within one clock cycle, the priority of the first instruction read request sent by the lookup failure handling submodule is higher than that of the first instruction read request sent by the instruction cache tag submodule.

10. A thread scheduling method, characterized in that, include: The instruction cache module is used to prefetch instruction data from multiple threads; The instruction register module is used to store the instruction data of the multiple threads that are to be pre-fetched, and within one clock cycle, the target thread and the target instruction of the target thread are determined based on the instruction data of the multiple threads. The target instruction of the target thread is sent to the execution module using the instruction register module. The method further includes: Using the thread scheduling module, within one clock cycle, a thread is determined for this scheduling according to the preset scheduling rules, and a register pointer is allocated for this thread for this scheduling. The register pointer allocated for this thread for this scheduling is used to indicate the instruction order priority of the instructions that the thread needs to read in this scheduling.

11. An electronic device, characterized in that, include: The thread scheduling system according to any one of claims 1-9.

12. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method of claim 10.

13. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method of claim 10.

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